1 /* 2 * linux/arch/arm/mach-pxa/pxa25x.c 3 * 4 * Author: Nicolas Pitre 5 * Created: Jun 15, 2001 6 * Copyright: MontaVista Software Inc. 7 * 8 * Code specific to PXA21x/25x/26x variants. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * Since this file should be linked before any other machine specific file, 15 * the __initcall() here will be executed first. This serves as default 16 * initialization stuff for PXA machines which can be overridden later if 17 * need be. 18 */ 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/platform_device.h> 23 #include <linux/suspend.h> 24 #include <linux/sysdev.h> 25 26 #include <mach/hardware.h> 27 #include <mach/irqs.h> 28 #include <mach/pxa-regs.h> 29 #include <mach/pxa2xx-regs.h> 30 #include <mach/mfp-pxa25x.h> 31 #include <mach/reset.h> 32 #include <mach/pm.h> 33 #include <mach/dma.h> 34 35 #include "generic.h" 36 #include "devices.h" 37 #include "clock.h" 38 39 int cpu_is_pxa26x(void) 40 { 41 return cpu_is_pxa250() && ((BOOT_DEF & 0x8) == 0); 42 } 43 EXPORT_SYMBOL_GPL(cpu_is_pxa26x); 44 45 /* 46 * Various clock factors driven by the CCCR register. 47 */ 48 49 /* Crystal Frequency to Memory Frequency Multiplier (L) */ 50 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, }; 51 52 /* Memory Frequency to Run Mode Frequency Multiplier (M) */ 53 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 }; 54 55 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */ 56 /* Note: we store the value N * 2 here. */ 57 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; 58 59 /* Crystal clock */ 60 #define BASE_CLK 3686400 61 62 /* 63 * Get the clock frequency as reflected by CCCR and the turbo flag. 64 * We assume these values have been applied via a fcs. 65 * If info is not 0 we also display the current settings. 66 */ 67 unsigned int pxa25x_get_clk_frequency_khz(int info) 68 { 69 unsigned long cccr, turbo; 70 unsigned int l, L, m, M, n2, N; 71 72 cccr = CCCR; 73 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) ); 74 75 l = L_clk_mult[(cccr >> 0) & 0x1f]; 76 m = M_clk_mult[(cccr >> 5) & 0x03]; 77 n2 = N2_clk_mult[(cccr >> 7) & 0x07]; 78 79 L = l * BASE_CLK; 80 M = m * L; 81 N = n2 * M / 2; 82 83 if(info) 84 { 85 L += 5000; 86 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n", 87 L / 1000000, (L % 1000000) / 10000, l ); 88 M += 5000; 89 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", 90 M / 1000000, (M % 1000000) / 10000, m ); 91 N += 5000; 92 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", 93 N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5, 94 (turbo & 1) ? "" : "in" ); 95 } 96 97 return (turbo & 1) ? (N/1000) : (M/1000); 98 } 99 100 /* 101 * Return the current memory clock frequency in units of 10kHz 102 */ 103 unsigned int pxa25x_get_memclk_frequency_10khz(void) 104 { 105 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; 106 } 107 108 static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) 109 { 110 return pxa25x_get_memclk_frequency_10khz() * 10000; 111 } 112 113 static const struct clkops clk_pxa25x_lcd_ops = { 114 .enable = clk_cken_enable, 115 .disable = clk_cken_disable, 116 .getrate = clk_pxa25x_lcd_getrate, 117 }; 118 119 static unsigned long gpio12_config_32k[] = { 120 GPIO12_32KHz, 121 }; 122 123 static unsigned long gpio12_config_gpio[] = { 124 GPIO12_GPIO, 125 }; 126 127 static void clk_gpio12_enable(struct clk *clk) 128 { 129 pxa2xx_mfp_config(gpio12_config_32k, 1); 130 } 131 132 static void clk_gpio12_disable(struct clk *clk) 133 { 134 pxa2xx_mfp_config(gpio12_config_gpio, 1); 135 } 136 137 static const struct clkops clk_pxa25x_gpio12_ops = { 138 .enable = clk_gpio12_enable, 139 .disable = clk_gpio12_disable, 140 }; 141 142 static unsigned long gpio11_config_3m6[] = { 143 GPIO11_3_6MHz, 144 }; 145 146 static unsigned long gpio11_config_gpio[] = { 147 GPIO11_GPIO, 148 }; 149 150 static void clk_gpio11_enable(struct clk *clk) 151 { 152 pxa2xx_mfp_config(gpio11_config_3m6, 1); 153 } 154 155 static void clk_gpio11_disable(struct clk *clk) 156 { 157 pxa2xx_mfp_config(gpio11_config_gpio, 1); 158 } 159 160 static const struct clkops clk_pxa25x_gpio11_ops = { 161 .enable = clk_gpio11_enable, 162 .disable = clk_gpio11_disable, 163 }; 164 165 /* 166 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz) 167 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz 168 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) 169 */ 170 static struct clk pxa25x_hwuart_clk = 171 INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev) 172 ; 173 174 /* 175 * PXA 2xx clock declarations. 176 */ 177 static struct clk pxa25x_clks[] = { 178 INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), 179 INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), 180 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), 181 INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), 182 INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev), 183 INIT_CLK("GPIO11_CLK", &clk_pxa25x_gpio11_ops, 3686400, 0, NULL), 184 INIT_CLK("GPIO12_CLK", &clk_pxa25x_gpio12_ops, 32768, 0, NULL), 185 INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), 186 INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), 187 188 INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev), 189 INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), 190 INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), 191 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev), 192 INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev), 193 194 INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), 195 196 /* 197 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), 198 */ 199 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), 200 }; 201 202 #ifdef CONFIG_PM 203 204 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 205 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 206 207 /* 208 * List of global PXA peripheral registers to preserve. 209 * More ones like CP and general purpose register values are preserved 210 * with the stack pointer in sleep.S. 211 */ 212 enum { 213 SLEEP_SAVE_PSTR, 214 SLEEP_SAVE_CKEN, 215 SLEEP_SAVE_COUNT 216 }; 217 218 219 static void pxa25x_cpu_pm_save(unsigned long *sleep_save) 220 { 221 SAVE(CKEN); 222 SAVE(PSTR); 223 } 224 225 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) 226 { 227 RESTORE(CKEN); 228 RESTORE(PSTR); 229 } 230 231 static void pxa25x_cpu_pm_enter(suspend_state_t state) 232 { 233 /* Clear reset status */ 234 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; 235 236 switch (state) { 237 case PM_SUSPEND_MEM: 238 pxa25x_cpu_suspend(PWRMODE_SLEEP); 239 break; 240 } 241 } 242 243 static int pxa25x_cpu_pm_prepare(void) 244 { 245 /* set resume return address */ 246 PSPR = virt_to_phys(pxa_cpu_resume); 247 return 0; 248 } 249 250 static void pxa25x_cpu_pm_finish(void) 251 { 252 /* ensure not to come back here if it wasn't intended */ 253 PSPR = 0; 254 } 255 256 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = { 257 .save_count = SLEEP_SAVE_COUNT, 258 .valid = suspend_valid_only_mem, 259 .save = pxa25x_cpu_pm_save, 260 .restore = pxa25x_cpu_pm_restore, 261 .enter = pxa25x_cpu_pm_enter, 262 .prepare = pxa25x_cpu_pm_prepare, 263 .finish = pxa25x_cpu_pm_finish, 264 }; 265 266 static void __init pxa25x_init_pm(void) 267 { 268 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns; 269 } 270 #else 271 static inline void pxa25x_init_pm(void) {} 272 #endif 273 274 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm 275 */ 276 277 static int pxa25x_set_wake(unsigned int irq, unsigned int on) 278 { 279 int gpio = IRQ_TO_GPIO(irq); 280 uint32_t mask = 0; 281 282 if (gpio >= 0 && gpio < 85) 283 return gpio_set_wake(gpio, on); 284 285 if (irq == IRQ_RTCAlrm) { 286 mask = PWER_RTC; 287 goto set_pwer; 288 } 289 290 return -EINVAL; 291 292 set_pwer: 293 if (on) 294 PWER |= mask; 295 else 296 PWER &=~mask; 297 298 return 0; 299 } 300 301 void __init pxa25x_init_irq(void) 302 { 303 pxa_init_irq(32, pxa25x_set_wake); 304 pxa_init_gpio(85, pxa25x_set_wake); 305 } 306 307 static struct platform_device *pxa25x_devices[] __initdata = { 308 &pxa25x_device_udc, 309 &pxa_device_ffuart, 310 &pxa_device_btuart, 311 &pxa_device_stuart, 312 &pxa_device_i2s, 313 &pxa_device_rtc, 314 &pxa25x_device_ssp, 315 &pxa25x_device_nssp, 316 &pxa25x_device_assp, 317 &pxa25x_device_pwm0, 318 &pxa25x_device_pwm1, 319 }; 320 321 static struct sys_device pxa25x_sysdev[] = { 322 { 323 .cls = &pxa_irq_sysclass, 324 }, { 325 .cls = &pxa2xx_mfp_sysclass, 326 }, { 327 .cls = &pxa_gpio_sysclass, 328 }, 329 }; 330 331 static int __init pxa25x_init(void) 332 { 333 int i, ret = 0; 334 335 if (cpu_is_pxa25x()) { 336 337 reset_status = RCSR; 338 339 clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); 340 341 if ((ret = pxa_init_dma(16))) 342 return ret; 343 344 pxa25x_init_pm(); 345 346 for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) { 347 ret = sysdev_register(&pxa25x_sysdev[i]); 348 if (ret) 349 pr_err("failed to register sysdev[%d]\n", i); 350 } 351 352 ret = platform_add_devices(pxa25x_devices, 353 ARRAY_SIZE(pxa25x_devices)); 354 if (ret) 355 return ret; 356 } 357 358 /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */ 359 if (cpu_is_pxa255() || cpu_is_pxa26x()) { 360 clks_register(&pxa25x_hwuart_clk, 1); 361 ret = platform_device_register(&pxa_device_hwuart); 362 } 363 364 return ret; 365 } 366 367 postcore_initcall(pxa25x_init); 368