1 /* 2 * linux/arch/arm/mach-pxa/pxa25x.c 3 * 4 * Author: Nicolas Pitre 5 * Created: Jun 15, 2001 6 * Copyright: MontaVista Software Inc. 7 * 8 * Code specific to PXA21x/25x/26x variants. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * Since this file should be linked before any other machine specific file, 15 * the __initcall() here will be executed first. This serves as default 16 * initialization stuff for PXA machines which can be overridden later if 17 * need be. 18 */ 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm.h> 24 25 #include <asm/hardware.h> 26 #include <asm/arch/irqs.h> 27 #include <asm/arch/pxa-regs.h> 28 #include <asm/arch/pm.h> 29 #include <asm/arch/dma.h> 30 31 #include "generic.h" 32 #include "devices.h" 33 34 /* 35 * Various clock factors driven by the CCCR register. 36 */ 37 38 /* Crystal Frequency to Memory Frequency Multiplier (L) */ 39 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, }; 40 41 /* Memory Frequency to Run Mode Frequency Multiplier (M) */ 42 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 }; 43 44 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */ 45 /* Note: we store the value N * 2 here. */ 46 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; 47 48 /* Crystal clock */ 49 #define BASE_CLK 3686400 50 51 /* 52 * Get the clock frequency as reflected by CCCR and the turbo flag. 53 * We assume these values have been applied via a fcs. 54 * If info is not 0 we also display the current settings. 55 */ 56 unsigned int pxa25x_get_clk_frequency_khz(int info) 57 { 58 unsigned long cccr, turbo; 59 unsigned int l, L, m, M, n2, N; 60 61 cccr = CCCR; 62 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) ); 63 64 l = L_clk_mult[(cccr >> 0) & 0x1f]; 65 m = M_clk_mult[(cccr >> 5) & 0x03]; 66 n2 = N2_clk_mult[(cccr >> 7) & 0x07]; 67 68 L = l * BASE_CLK; 69 M = m * L; 70 N = n2 * M / 2; 71 72 if(info) 73 { 74 L += 5000; 75 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n", 76 L / 1000000, (L % 1000000) / 10000, l ); 77 M += 5000; 78 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", 79 M / 1000000, (M % 1000000) / 10000, m ); 80 N += 5000; 81 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", 82 N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5, 83 (turbo & 1) ? "" : "in" ); 84 } 85 86 return (turbo & 1) ? (N/1000) : (M/1000); 87 } 88 89 /* 90 * Return the current memory clock frequency in units of 10kHz 91 */ 92 unsigned int pxa25x_get_memclk_frequency_10khz(void) 93 { 94 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; 95 } 96 97 #ifdef CONFIG_PM 98 99 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 100 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 101 102 #define RESTORE_GPLEVEL(n) do { \ 103 GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \ 104 GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \ 105 } while (0) 106 107 /* 108 * List of global PXA peripheral registers to preserve. 109 * More ones like CP and general purpose register values are preserved 110 * with the stack pointer in sleep.S. 111 */ 112 enum { SLEEP_SAVE_START = 0, 113 114 SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, 115 SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, 116 SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, 117 SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, 118 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, 119 120 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, 121 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, 122 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, 123 124 SLEEP_SAVE_PSTR, 125 126 SLEEP_SAVE_ICMR, 127 SLEEP_SAVE_CKEN, 128 129 SLEEP_SAVE_SIZE 130 }; 131 132 133 static void pxa25x_cpu_pm_save(unsigned long *sleep_save) 134 { 135 SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); 136 SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); 137 SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); 138 SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); 139 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); 140 141 SAVE(GAFR0_L); SAVE(GAFR0_U); 142 SAVE(GAFR1_L); SAVE(GAFR1_U); 143 SAVE(GAFR2_L); SAVE(GAFR2_U); 144 145 SAVE(ICMR); 146 SAVE(CKEN); 147 SAVE(PSTR); 148 } 149 150 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) 151 { 152 /* restore registers */ 153 RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2); 154 RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); 155 RESTORE(GAFR0_L); RESTORE(GAFR0_U); 156 RESTORE(GAFR1_L); RESTORE(GAFR1_U); 157 RESTORE(GAFR2_L); RESTORE(GAFR2_U); 158 RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); 159 RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); 160 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); 161 162 RESTORE(CKEN); 163 RESTORE(ICMR); 164 RESTORE(PSTR); 165 } 166 167 static void pxa25x_cpu_pm_enter(suspend_state_t state) 168 { 169 CKEN = 0; 170 171 switch (state) { 172 case PM_SUSPEND_MEM: 173 /* set resume return address */ 174 PSPR = virt_to_phys(pxa_cpu_resume); 175 pxa25x_cpu_suspend(PWRMODE_SLEEP); 176 break; 177 } 178 } 179 180 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = { 181 .save_size = SLEEP_SAVE_SIZE, 182 .valid = pm_valid_only_mem, 183 .save = pxa25x_cpu_pm_save, 184 .restore = pxa25x_cpu_pm_restore, 185 .enter = pxa25x_cpu_pm_enter, 186 }; 187 188 static void __init pxa25x_init_pm(void) 189 { 190 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns; 191 } 192 #endif 193 194 void __init pxa25x_init_irq(void) 195 { 196 pxa_init_irq_low(); 197 pxa_init_irq_gpio(85); 198 } 199 200 static struct platform_device *pxa25x_devices[] __initdata = { 201 &pxa_device_mci, 202 &pxa_device_udc, 203 &pxa_device_fb, 204 &pxa_device_ffuart, 205 &pxa_device_btuart, 206 &pxa_device_stuart, 207 &pxa_device_i2c, 208 &pxa_device_i2s, 209 &pxa_device_ficp, 210 &pxa_device_rtc, 211 }; 212 213 static int __init pxa25x_init(void) 214 { 215 int ret = 0; 216 217 if (cpu_is_pxa21x() || cpu_is_pxa25x()) { 218 if ((ret = pxa_init_dma(16))) 219 return ret; 220 #ifdef CONFIG_PM 221 pxa25x_init_pm(); 222 #endif 223 ret = platform_add_devices(pxa25x_devices, 224 ARRAY_SIZE(pxa25x_devices)); 225 } 226 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ 227 if (cpu_is_pxa25x()) 228 ret = platform_device_register(&pxa_device_hwuart); 229 230 return ret; 231 } 232 233 subsys_initcall(pxa25x_init); 234