1 /* 2 * linux/arch/arm/mach-pxa/generic.c 3 * 4 * Author: Nicolas Pitre 5 * Created: Jun 15, 2001 6 * Copyright: MontaVista Software Inc. 7 * 8 * Code common to all PXA machines. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * Since this file should be linked before any other machine specific file, 15 * the __initcall() here will be executed first. This serves as default 16 * initialization stuff for PXA machines which can be overridden later if 17 * need be. 18 */ 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/platform_device.h> 24 #include <linux/ioport.h> 25 #include <linux/pm.h> 26 #include <linux/string.h> 27 28 #include <linux/sched.h> 29 #include <asm/cnt32_to_63.h> 30 #include <asm/div64.h> 31 32 #include <asm/hardware.h> 33 #include <asm/irq.h> 34 #include <asm/system.h> 35 #include <asm/pgtable.h> 36 #include <asm/mach/map.h> 37 38 #include <asm/arch/pxa-regs.h> 39 #include <asm/arch/gpio.h> 40 #include <asm/arch/udc.h> 41 #include <asm/arch/pxafb.h> 42 #include <asm/arch/mmc.h> 43 #include <asm/arch/irda.h> 44 #include <asm/arch/i2c.h> 45 46 #include "devices.h" 47 #include "generic.h" 48 49 /* 50 * This is the PXA2xx sched_clock implementation. This has a resolution 51 * of at least 308ns and a maximum value that depends on the value of 52 * CLOCK_TICK_RATE. 53 * 54 * The return value is guaranteed to be monotonic in that range as 55 * long as there is always less than 582 seconds between successive 56 * calls to this function. 57 */ 58 unsigned long long sched_clock(void) 59 { 60 unsigned long long v = cnt32_to_63(OSCR); 61 /* Note: top bit ov v needs cleared unless multiplier is even. */ 62 63 #if CLOCK_TICK_RATE == 3686400 64 /* 1E9 / 3686400 => 78125 / 288, max value = 32025597s (370 days). */ 65 /* The <<1 is used to get rid of tick.hi top bit */ 66 v *= 78125<<1; 67 do_div(v, 288<<1); 68 #elif CLOCK_TICK_RATE == 3250000 69 /* 1E9 / 3250000 => 4000 / 13, max value = 709490156s (8211 days) */ 70 v *= 4000; 71 do_div(v, 13); 72 #elif CLOCK_TICK_RATE == 3249600 73 /* 1E9 / 3249600 => 625000 / 2031, max value = 4541295s (52 days) */ 74 v *= 625000; 75 do_div(v, 2031); 76 #else 77 #warning "consider fixing sched_clock for your value of CLOCK_TICK_RATE" 78 /* 79 * 96-bit math to perform tick * NSEC_PER_SEC / CLOCK_TICK_RATE for 80 * any value of CLOCK_TICK_RATE. Max value is in the 80 thousand 81 * years range and truncation to unsigned long long limits it to 82 * sched_clock's max range of ~584 years. This is nice but with 83 * higher computation cost. 84 */ 85 { 86 union { 87 unsigned long long val; 88 struct { unsigned long lo, hi; }; 89 } x; 90 unsigned long long y; 91 92 x.val = v; 93 x.hi &= 0x7fffffff; 94 y = (unsigned long long)x.lo * NSEC_PER_SEC; 95 x.lo = y; 96 y = (y >> 32) + (unsigned long long)x.hi * NSEC_PER_SEC; 97 x.hi = do_div(y, CLOCK_TICK_RATE); 98 do_div(x.val, CLOCK_TICK_RATE); 99 x.hi += y; 100 v = x.val; 101 } 102 #endif 103 104 return v; 105 } 106 107 /* 108 * Handy function to set GPIO alternate functions 109 */ 110 111 int pxa_gpio_mode(int gpio_mode) 112 { 113 unsigned long flags; 114 int gpio = gpio_mode & GPIO_MD_MASK_NR; 115 int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; 116 int gafr; 117 118 if (gpio > PXA_LAST_GPIO) 119 return -EINVAL; 120 121 local_irq_save(flags); 122 if (gpio_mode & GPIO_DFLT_LOW) 123 GPCR(gpio) = GPIO_bit(gpio); 124 else if (gpio_mode & GPIO_DFLT_HIGH) 125 GPSR(gpio) = GPIO_bit(gpio); 126 if (gpio_mode & GPIO_MD_MASK_DIR) 127 GPDR(gpio) |= GPIO_bit(gpio); 128 else 129 GPDR(gpio) &= ~GPIO_bit(gpio); 130 gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); 131 GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); 132 local_irq_restore(flags); 133 134 return 0; 135 } 136 137 EXPORT_SYMBOL(pxa_gpio_mode); 138 139 /* 140 * Return GPIO level 141 */ 142 int pxa_gpio_get_value(unsigned gpio) 143 { 144 return __gpio_get_value(gpio); 145 } 146 147 EXPORT_SYMBOL(pxa_gpio_get_value); 148 149 /* 150 * Set output GPIO level 151 */ 152 void pxa_gpio_set_value(unsigned gpio, int value) 153 { 154 __gpio_set_value(gpio, value); 155 } 156 157 EXPORT_SYMBOL(pxa_gpio_set_value); 158 159 /* 160 * Routine to safely enable or disable a clock in the CKEN 161 */ 162 void pxa_set_cken(int clock, int enable) 163 { 164 unsigned long flags; 165 local_irq_save(flags); 166 167 if (enable) 168 CKEN |= (1 << clock); 169 else 170 CKEN &= ~(1 << clock); 171 172 local_irq_restore(flags); 173 } 174 175 EXPORT_SYMBOL(pxa_set_cken); 176 177 /* 178 * Intel PXA2xx internal register mapping. 179 * 180 * Note 1: not all PXA2xx variants implement all those addresses. 181 * 182 * Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table 183 * and cache flush area. 184 */ 185 static struct map_desc standard_io_desc[] __initdata = { 186 { /* Devs */ 187 .virtual = 0xf2000000, 188 .pfn = __phys_to_pfn(0x40000000), 189 .length = 0x02000000, 190 .type = MT_DEVICE 191 }, { /* LCD */ 192 .virtual = 0xf4000000, 193 .pfn = __phys_to_pfn(0x44000000), 194 .length = 0x00100000, 195 .type = MT_DEVICE 196 }, { /* Mem Ctl */ 197 .virtual = 0xf6000000, 198 .pfn = __phys_to_pfn(0x48000000), 199 .length = 0x00100000, 200 .type = MT_DEVICE 201 }, { /* USB host */ 202 .virtual = 0xf8000000, 203 .pfn = __phys_to_pfn(0x4c000000), 204 .length = 0x00100000, 205 .type = MT_DEVICE 206 }, { /* Camera */ 207 .virtual = 0xfa000000, 208 .pfn = __phys_to_pfn(0x50000000), 209 .length = 0x00100000, 210 .type = MT_DEVICE 211 }, { /* IMem ctl */ 212 .virtual = 0xfe000000, 213 .pfn = __phys_to_pfn(0x58000000), 214 .length = 0x00100000, 215 .type = MT_DEVICE 216 }, { /* UNCACHED_PHYS_0 */ 217 .virtual = 0xff000000, 218 .pfn = __phys_to_pfn(0x00000000), 219 .length = 0x00100000, 220 .type = MT_DEVICE 221 } 222 }; 223 224 void __init pxa_map_io(void) 225 { 226 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 227 get_clk_frequency_khz(1); 228 } 229 230 231 static struct resource pxamci_resources[] = { 232 [0] = { 233 .start = 0x41100000, 234 .end = 0x41100fff, 235 .flags = IORESOURCE_MEM, 236 }, 237 [1] = { 238 .start = IRQ_MMC, 239 .end = IRQ_MMC, 240 .flags = IORESOURCE_IRQ, 241 }, 242 }; 243 244 static u64 pxamci_dmamask = 0xffffffffUL; 245 246 struct platform_device pxa_device_mci = { 247 .name = "pxa2xx-mci", 248 .id = -1, 249 .dev = { 250 .dma_mask = &pxamci_dmamask, 251 .coherent_dma_mask = 0xffffffff, 252 }, 253 .num_resources = ARRAY_SIZE(pxamci_resources), 254 .resource = pxamci_resources, 255 }; 256 257 void __init pxa_set_mci_info(struct pxamci_platform_data *info) 258 { 259 pxa_device_mci.dev.platform_data = info; 260 } 261 262 263 static struct pxa2xx_udc_mach_info pxa_udc_info; 264 265 void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info) 266 { 267 memcpy(&pxa_udc_info, info, sizeof *info); 268 } 269 270 static struct resource pxa2xx_udc_resources[] = { 271 [0] = { 272 .start = 0x40600000, 273 .end = 0x4060ffff, 274 .flags = IORESOURCE_MEM, 275 }, 276 [1] = { 277 .start = IRQ_USB, 278 .end = IRQ_USB, 279 .flags = IORESOURCE_IRQ, 280 }, 281 }; 282 283 static u64 udc_dma_mask = ~(u32)0; 284 285 struct platform_device pxa_device_udc = { 286 .name = "pxa2xx-udc", 287 .id = -1, 288 .resource = pxa2xx_udc_resources, 289 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources), 290 .dev = { 291 .platform_data = &pxa_udc_info, 292 .dma_mask = &udc_dma_mask, 293 } 294 }; 295 296 static struct resource pxafb_resources[] = { 297 [0] = { 298 .start = 0x44000000, 299 .end = 0x4400ffff, 300 .flags = IORESOURCE_MEM, 301 }, 302 [1] = { 303 .start = IRQ_LCD, 304 .end = IRQ_LCD, 305 .flags = IORESOURCE_IRQ, 306 }, 307 }; 308 309 static u64 fb_dma_mask = ~(u64)0; 310 311 struct platform_device pxa_device_fb = { 312 .name = "pxa2xx-fb", 313 .id = -1, 314 .dev = { 315 .dma_mask = &fb_dma_mask, 316 .coherent_dma_mask = 0xffffffff, 317 }, 318 .num_resources = ARRAY_SIZE(pxafb_resources), 319 .resource = pxafb_resources, 320 }; 321 322 void __init set_pxa_fb_info(struct pxafb_mach_info *info) 323 { 324 pxa_device_fb.dev.platform_data = info; 325 } 326 327 void __init set_pxa_fb_parent(struct device *parent_dev) 328 { 329 pxa_device_fb.dev.parent = parent_dev; 330 } 331 332 struct platform_device pxa_device_ffuart= { 333 .name = "pxa2xx-uart", 334 .id = 0, 335 }; 336 struct platform_device pxa_device_btuart = { 337 .name = "pxa2xx-uart", 338 .id = 1, 339 }; 340 struct platform_device pxa_device_stuart = { 341 .name = "pxa2xx-uart", 342 .id = 2, 343 }; 344 struct platform_device pxa_device_hwuart = { 345 .name = "pxa2xx-uart", 346 .id = 3, 347 }; 348 349 static struct resource pxai2c_resources[] = { 350 { 351 .start = 0x40301680, 352 .end = 0x403016a3, 353 .flags = IORESOURCE_MEM, 354 }, { 355 .start = IRQ_I2C, 356 .end = IRQ_I2C, 357 .flags = IORESOURCE_IRQ, 358 }, 359 }; 360 361 struct platform_device pxa_device_i2c = { 362 .name = "pxa2xx-i2c", 363 .id = 0, 364 .resource = pxai2c_resources, 365 .num_resources = ARRAY_SIZE(pxai2c_resources), 366 }; 367 368 void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) 369 { 370 pxa_device_i2c.dev.platform_data = info; 371 } 372 373 static struct resource pxai2s_resources[] = { 374 { 375 .start = 0x40400000, 376 .end = 0x40400083, 377 .flags = IORESOURCE_MEM, 378 }, { 379 .start = IRQ_I2S, 380 .end = IRQ_I2S, 381 .flags = IORESOURCE_IRQ, 382 }, 383 }; 384 385 struct platform_device pxa_device_i2s = { 386 .name = "pxa2xx-i2s", 387 .id = -1, 388 .resource = pxai2s_resources, 389 .num_resources = ARRAY_SIZE(pxai2s_resources), 390 }; 391 392 static u64 pxaficp_dmamask = ~(u32)0; 393 394 struct platform_device pxa_device_ficp = { 395 .name = "pxa2xx-ir", 396 .id = -1, 397 .dev = { 398 .dma_mask = &pxaficp_dmamask, 399 .coherent_dma_mask = 0xffffffff, 400 }, 401 }; 402 403 void __init pxa_set_ficp_info(struct pxaficp_platform_data *info) 404 { 405 pxa_device_ficp.dev.platform_data = info; 406 } 407 408 struct platform_device pxa_device_rtc = { 409 .name = "sa1100-rtc", 410 .id = -1, 411 }; 412