xref: /linux/arch/arm/mach-pxa/devices.c (revision 28afe961a18f77b2249062499bdbf70fd2ec6bba) 
1 #include <linux/module.h>
2 #include <linux/kernel.h>
3 #include <linux/init.h>
4 #include <linux/platform_device.h>
5 #include <linux/dma-mapping.h>
6 
7 #include <asm/arch/gpio.h>
8 #include <asm/arch/udc.h>
9 #include <asm/arch/pxafb.h>
10 #include <asm/arch/mmc.h>
11 #include <asm/arch/irda.h>
12 #include <asm/arch/i2c.h>
13 #include <asm/arch/mfp-pxa27x.h>
14 #include <asm/arch/ohci.h>
15 #include <asm/arch/pxa27x_keypad.h>
16 #include <asm/arch/pxa2xx_spi.h>
17 #include <asm/arch/camera.h>
18 #include <asm/arch/audio.h>
19 #include <asm/arch/pxa3xx_nand.h>
20 
21 #include "devices.h"
22 #include "generic.h"
23 
24 void __init pxa_register_device(struct platform_device *dev, void *data)
25 {
26 	int ret;
27 
28 	dev->dev.platform_data = data;
29 
30 	ret = platform_device_register(dev);
31 	if (ret)
32 		dev_err(&dev->dev, "unable to register device: %d\n", ret);
33 }
34 
35 static struct resource pxamci_resources[] = {
36 	[0] = {
37 		.start	= 0x41100000,
38 		.end	= 0x41100fff,
39 		.flags	= IORESOURCE_MEM,
40 	},
41 	[1] = {
42 		.start	= IRQ_MMC,
43 		.end	= IRQ_MMC,
44 		.flags	= IORESOURCE_IRQ,
45 	},
46 	[2] = {
47 		.start	= 21,
48 		.end	= 21,
49 		.flags	= IORESOURCE_DMA,
50 	},
51 	[3] = {
52 		.start	= 22,
53 		.end	= 22,
54 		.flags	= IORESOURCE_DMA,
55 	},
56 };
57 
58 static u64 pxamci_dmamask = 0xffffffffUL;
59 
60 struct platform_device pxa_device_mci = {
61 	.name		= "pxa2xx-mci",
62 	.id		= 0,
63 	.dev		= {
64 		.dma_mask = &pxamci_dmamask,
65 		.coherent_dma_mask = 0xffffffff,
66 	},
67 	.num_resources	= ARRAY_SIZE(pxamci_resources),
68 	.resource	= pxamci_resources,
69 };
70 
71 void __init pxa_set_mci_info(struct pxamci_platform_data *info)
72 {
73 	pxa_register_device(&pxa_device_mci, info);
74 }
75 
76 
77 static struct pxa2xx_udc_mach_info pxa_udc_info;
78 
79 void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
80 {
81 	memcpy(&pxa_udc_info, info, sizeof *info);
82 }
83 
84 static struct resource pxa2xx_udc_resources[] = {
85 	[0] = {
86 		.start	= 0x40600000,
87 		.end	= 0x4060ffff,
88 		.flags	= IORESOURCE_MEM,
89 	},
90 	[1] = {
91 		.start	= IRQ_USB,
92 		.end	= IRQ_USB,
93 		.flags	= IORESOURCE_IRQ,
94 	},
95 };
96 
97 static u64 udc_dma_mask = ~(u32)0;
98 
99 struct platform_device pxa25x_device_udc = {
100 	.name		= "pxa25x-udc",
101 	.id		= -1,
102 	.resource	= pxa2xx_udc_resources,
103 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
104 	.dev		=  {
105 		.platform_data	= &pxa_udc_info,
106 		.dma_mask	= &udc_dma_mask,
107 	}
108 };
109 
110 struct platform_device pxa27x_device_udc = {
111 	.name		= "pxa27x-udc",
112 	.id		= -1,
113 	.resource	= pxa2xx_udc_resources,
114 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
115 	.dev		=  {
116 		.platform_data	= &pxa_udc_info,
117 		.dma_mask	= &udc_dma_mask,
118 	}
119 };
120 
121 static struct resource pxafb_resources[] = {
122 	[0] = {
123 		.start	= 0x44000000,
124 		.end	= 0x4400ffff,
125 		.flags	= IORESOURCE_MEM,
126 	},
127 	[1] = {
128 		.start	= IRQ_LCD,
129 		.end	= IRQ_LCD,
130 		.flags	= IORESOURCE_IRQ,
131 	},
132 };
133 
134 static u64 fb_dma_mask = ~(u64)0;
135 
136 struct platform_device pxa_device_fb = {
137 	.name		= "pxa2xx-fb",
138 	.id		= -1,
139 	.dev		= {
140 		.dma_mask	= &fb_dma_mask,
141 		.coherent_dma_mask = 0xffffffff,
142 	},
143 	.num_resources	= ARRAY_SIZE(pxafb_resources),
144 	.resource	= pxafb_resources,
145 };
146 
147 void __init set_pxa_fb_info(struct pxafb_mach_info *info)
148 {
149 	pxa_register_device(&pxa_device_fb, info);
150 }
151 
152 void __init set_pxa_fb_parent(struct device *parent_dev)
153 {
154 	pxa_device_fb.dev.parent = parent_dev;
155 }
156 
157 static struct resource pxa_resource_ffuart[] = {
158 	{
159 		.start	= __PREG(FFUART),
160 		.end	= __PREG(FFUART) + 35,
161 		.flags	= IORESOURCE_MEM,
162 	}, {
163 		.start	= IRQ_FFUART,
164 		.end	= IRQ_FFUART,
165 		.flags	= IORESOURCE_IRQ,
166 	}
167 };
168 
169 struct platform_device pxa_device_ffuart= {
170 	.name		= "pxa2xx-uart",
171 	.id		= 0,
172 	.resource	= pxa_resource_ffuart,
173 	.num_resources	= ARRAY_SIZE(pxa_resource_ffuart),
174 };
175 
176 static struct resource pxa_resource_btuart[] = {
177 	{
178 		.start	= __PREG(BTUART),
179 		.end	= __PREG(BTUART) + 35,
180 		.flags	= IORESOURCE_MEM,
181 	}, {
182 		.start	= IRQ_BTUART,
183 		.end	= IRQ_BTUART,
184 		.flags	= IORESOURCE_IRQ,
185 	}
186 };
187 
188 struct platform_device pxa_device_btuart = {
189 	.name		= "pxa2xx-uart",
190 	.id		= 1,
191 	.resource	= pxa_resource_btuart,
192 	.num_resources	= ARRAY_SIZE(pxa_resource_btuart),
193 };
194 
195 static struct resource pxa_resource_stuart[] = {
196 	{
197 		.start	= __PREG(STUART),
198 		.end	= __PREG(STUART) + 35,
199 		.flags	= IORESOURCE_MEM,
200 	}, {
201 		.start	= IRQ_STUART,
202 		.end	= IRQ_STUART,
203 		.flags	= IORESOURCE_IRQ,
204 	}
205 };
206 
207 struct platform_device pxa_device_stuart = {
208 	.name		= "pxa2xx-uart",
209 	.id		= 2,
210 	.resource	= pxa_resource_stuart,
211 	.num_resources	= ARRAY_SIZE(pxa_resource_stuart),
212 };
213 
214 static struct resource pxa_resource_hwuart[] = {
215 	{
216 		.start	= __PREG(HWUART),
217 		.end	= __PREG(HWUART) + 47,
218 		.flags	= IORESOURCE_MEM,
219 	}, {
220 		.start	= IRQ_HWUART,
221 		.end	= IRQ_HWUART,
222 		.flags	= IORESOURCE_IRQ,
223 	}
224 };
225 
226 struct platform_device pxa_device_hwuart = {
227 	.name		= "pxa2xx-uart",
228 	.id		= 3,
229 	.resource	= pxa_resource_hwuart,
230 	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
231 };
232 
233 static struct resource pxai2c_resources[] = {
234 	{
235 		.start	= 0x40301680,
236 		.end	= 0x403016a3,
237 		.flags	= IORESOURCE_MEM,
238 	}, {
239 		.start	= IRQ_I2C,
240 		.end	= IRQ_I2C,
241 		.flags	= IORESOURCE_IRQ,
242 	},
243 };
244 
245 struct platform_device pxa_device_i2c = {
246 	.name		= "pxa2xx-i2c",
247 	.id		= 0,
248 	.resource	= pxai2c_resources,
249 	.num_resources	= ARRAY_SIZE(pxai2c_resources),
250 };
251 
252 static unsigned long pxa27x_i2c_mfp_cfg[] = {
253 	GPIO117_I2C_SCL,
254 	GPIO118_I2C_SDA,
255 };
256 
257 void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
258 {
259 	if (cpu_is_pxa27x())
260 		pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg));
261 	pxa_register_device(&pxa_device_i2c, info);
262 }
263 
264 static struct resource pxai2s_resources[] = {
265 	{
266 		.start	= 0x40400000,
267 		.end	= 0x40400083,
268 		.flags	= IORESOURCE_MEM,
269 	}, {
270 		.start	= IRQ_I2S,
271 		.end	= IRQ_I2S,
272 		.flags	= IORESOURCE_IRQ,
273 	},
274 };
275 
276 struct platform_device pxa_device_i2s = {
277 	.name		= "pxa2xx-i2s",
278 	.id		= -1,
279 	.resource	= pxai2s_resources,
280 	.num_resources	= ARRAY_SIZE(pxai2s_resources),
281 };
282 
283 static u64 pxaficp_dmamask = ~(u32)0;
284 
285 struct platform_device pxa_device_ficp = {
286 	.name		= "pxa2xx-ir",
287 	.id		= -1,
288 	.dev		= {
289 		.dma_mask = &pxaficp_dmamask,
290 		.coherent_dma_mask = 0xffffffff,
291 	},
292 };
293 
294 void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
295 {
296 	pxa_register_device(&pxa_device_ficp, info);
297 }
298 
299 struct platform_device pxa_device_rtc = {
300 	.name		= "sa1100-rtc",
301 	.id		= -1,
302 };
303 
304 static struct resource pxa_ac97_resources[] = {
305 	[0] = {
306 		.start  = 0x40500000,
307 		.end	= 0x40500000 + 0xfff,
308 		.flags  = IORESOURCE_MEM,
309 	},
310 	[1] = {
311 		.start  = IRQ_AC97,
312 		.end    = IRQ_AC97,
313 		.flags  = IORESOURCE_IRQ,
314 	},
315 };
316 
317 static u64 pxa_ac97_dmamask = 0xffffffffUL;
318 
319 struct platform_device pxa_device_ac97 = {
320 	.name           = "pxa2xx-ac97",
321 	.id             = -1,
322 	.dev            = {
323 		.dma_mask = &pxa_ac97_dmamask,
324 		.coherent_dma_mask = 0xffffffff,
325 	},
326 	.num_resources  = ARRAY_SIZE(pxa_ac97_resources),
327 	.resource       = pxa_ac97_resources,
328 };
329 
330 void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
331 {
332 	pxa_register_device(&pxa_device_ac97, ops);
333 }
334 
335 #ifdef CONFIG_PXA25x
336 
337 static struct resource pxa25x_resource_pwm0[] = {
338 	[0] = {
339 		.start	= 0x40b00000,
340 		.end	= 0x40b0000f,
341 		.flags	= IORESOURCE_MEM,
342 	},
343 };
344 
345 struct platform_device pxa25x_device_pwm0 = {
346 	.name		= "pxa25x-pwm",
347 	.id		= 0,
348 	.resource	= pxa25x_resource_pwm0,
349 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm0),
350 };
351 
352 static struct resource pxa25x_resource_pwm1[] = {
353 	[0] = {
354 		.start	= 0x40c00000,
355 		.end	= 0x40c0000f,
356 		.flags	= IORESOURCE_MEM,
357 	},
358 };
359 
360 struct platform_device pxa25x_device_pwm1 = {
361 	.name		= "pxa25x-pwm",
362 	.id		= 1,
363 	.resource	= pxa25x_resource_pwm1,
364 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm1),
365 };
366 
367 static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
368 
369 static struct resource pxa25x_resource_ssp[] = {
370 	[0] = {
371 		.start	= 0x41000000,
372 		.end	= 0x4100001f,
373 		.flags	= IORESOURCE_MEM,
374 	},
375 	[1] = {
376 		.start	= IRQ_SSP,
377 		.end	= IRQ_SSP,
378 		.flags	= IORESOURCE_IRQ,
379 	},
380 	[2] = {
381 		/* DRCMR for RX */
382 		.start	= 13,
383 		.end	= 13,
384 		.flags	= IORESOURCE_DMA,
385 	},
386 	[3] = {
387 		/* DRCMR for TX */
388 		.start	= 14,
389 		.end	= 14,
390 		.flags	= IORESOURCE_DMA,
391 	},
392 };
393 
394 struct platform_device pxa25x_device_ssp = {
395 	.name		= "pxa25x-ssp",
396 	.id		= 0,
397 	.dev		= {
398 		.dma_mask = &pxa25x_ssp_dma_mask,
399 		.coherent_dma_mask = DMA_BIT_MASK(32),
400 	},
401 	.resource	= pxa25x_resource_ssp,
402 	.num_resources	= ARRAY_SIZE(pxa25x_resource_ssp),
403 };
404 
405 static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
406 
407 static struct resource pxa25x_resource_nssp[] = {
408 	[0] = {
409 		.start	= 0x41400000,
410 		.end	= 0x4140002f,
411 		.flags	= IORESOURCE_MEM,
412 	},
413 	[1] = {
414 		.start	= IRQ_NSSP,
415 		.end	= IRQ_NSSP,
416 		.flags	= IORESOURCE_IRQ,
417 	},
418 	[2] = {
419 		/* DRCMR for RX */
420 		.start	= 15,
421 		.end	= 15,
422 		.flags	= IORESOURCE_DMA,
423 	},
424 	[3] = {
425 		/* DRCMR for TX */
426 		.start	= 16,
427 		.end	= 16,
428 		.flags	= IORESOURCE_DMA,
429 	},
430 };
431 
432 struct platform_device pxa25x_device_nssp = {
433 	.name		= "pxa25x-nssp",
434 	.id		= 1,
435 	.dev		= {
436 		.dma_mask = &pxa25x_nssp_dma_mask,
437 		.coherent_dma_mask = DMA_BIT_MASK(32),
438 	},
439 	.resource	= pxa25x_resource_nssp,
440 	.num_resources	= ARRAY_SIZE(pxa25x_resource_nssp),
441 };
442 
443 static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
444 
445 static struct resource pxa25x_resource_assp[] = {
446 	[0] = {
447 		.start	= 0x41500000,
448 		.end	= 0x4150002f,
449 		.flags	= IORESOURCE_MEM,
450 	},
451 	[1] = {
452 		.start	= IRQ_ASSP,
453 		.end	= IRQ_ASSP,
454 		.flags	= IORESOURCE_IRQ,
455 	},
456 	[2] = {
457 		/* DRCMR for RX */
458 		.start	= 23,
459 		.end	= 23,
460 		.flags	= IORESOURCE_DMA,
461 	},
462 	[3] = {
463 		/* DRCMR for TX */
464 		.start	= 24,
465 		.end	= 24,
466 		.flags	= IORESOURCE_DMA,
467 	},
468 };
469 
470 struct platform_device pxa25x_device_assp = {
471 	/* ASSP is basically equivalent to NSSP */
472 	.name		= "pxa25x-nssp",
473 	.id		= 2,
474 	.dev		= {
475 		.dma_mask = &pxa25x_assp_dma_mask,
476 		.coherent_dma_mask = DMA_BIT_MASK(32),
477 	},
478 	.resource	= pxa25x_resource_assp,
479 	.num_resources	= ARRAY_SIZE(pxa25x_resource_assp),
480 };
481 #endif /* CONFIG_PXA25x */
482 
483 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
484 
485 static struct resource pxa27x_resource_keypad[] = {
486 	[0] = {
487 		.start	= 0x41500000,
488 		.end	= 0x4150004c,
489 		.flags	= IORESOURCE_MEM,
490 	},
491 	[1] = {
492 		.start	= IRQ_KEYPAD,
493 		.end	= IRQ_KEYPAD,
494 		.flags	= IORESOURCE_IRQ,
495 	},
496 };
497 
498 struct platform_device pxa27x_device_keypad = {
499 	.name		= "pxa27x-keypad",
500 	.id		= -1,
501 	.resource	= pxa27x_resource_keypad,
502 	.num_resources	= ARRAY_SIZE(pxa27x_resource_keypad),
503 };
504 
505 void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
506 {
507 	pxa_register_device(&pxa27x_device_keypad, info);
508 }
509 
510 static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
511 
512 static struct resource pxa27x_resource_ohci[] = {
513 	[0] = {
514 		.start  = 0x4C000000,
515 		.end    = 0x4C00ff6f,
516 		.flags  = IORESOURCE_MEM,
517 	},
518 	[1] = {
519 		.start  = IRQ_USBH1,
520 		.end    = IRQ_USBH1,
521 		.flags  = IORESOURCE_IRQ,
522 	},
523 };
524 
525 struct platform_device pxa27x_device_ohci = {
526 	.name		= "pxa27x-ohci",
527 	.id		= -1,
528 	.dev		= {
529 		.dma_mask = &pxa27x_ohci_dma_mask,
530 		.coherent_dma_mask = DMA_BIT_MASK(32),
531 	},
532 	.num_resources  = ARRAY_SIZE(pxa27x_resource_ohci),
533 	.resource       = pxa27x_resource_ohci,
534 };
535 
536 void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
537 {
538 	pxa_register_device(&pxa27x_device_ohci, info);
539 }
540 
541 static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
542 
543 static struct resource pxa27x_resource_ssp1[] = {
544 	[0] = {
545 		.start	= 0x41000000,
546 		.end	= 0x4100003f,
547 		.flags	= IORESOURCE_MEM,
548 	},
549 	[1] = {
550 		.start	= IRQ_SSP,
551 		.end	= IRQ_SSP,
552 		.flags	= IORESOURCE_IRQ,
553 	},
554 	[2] = {
555 		/* DRCMR for RX */
556 		.start	= 13,
557 		.end	= 13,
558 		.flags	= IORESOURCE_DMA,
559 	},
560 	[3] = {
561 		/* DRCMR for TX */
562 		.start	= 14,
563 		.end	= 14,
564 		.flags	= IORESOURCE_DMA,
565 	},
566 };
567 
568 struct platform_device pxa27x_device_ssp1 = {
569 	.name		= "pxa27x-ssp",
570 	.id		= 0,
571 	.dev		= {
572 		.dma_mask = &pxa27x_ssp1_dma_mask,
573 		.coherent_dma_mask = DMA_BIT_MASK(32),
574 	},
575 	.resource	= pxa27x_resource_ssp1,
576 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
577 };
578 
579 static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
580 
581 static struct resource pxa27x_resource_ssp2[] = {
582 	[0] = {
583 		.start	= 0x41700000,
584 		.end	= 0x4170003f,
585 		.flags	= IORESOURCE_MEM,
586 	},
587 	[1] = {
588 		.start	= IRQ_SSP2,
589 		.end	= IRQ_SSP2,
590 		.flags	= IORESOURCE_IRQ,
591 	},
592 	[2] = {
593 		/* DRCMR for RX */
594 		.start	= 15,
595 		.end	= 15,
596 		.flags	= IORESOURCE_DMA,
597 	},
598 	[3] = {
599 		/* DRCMR for TX */
600 		.start	= 16,
601 		.end	= 16,
602 		.flags	= IORESOURCE_DMA,
603 	},
604 };
605 
606 struct platform_device pxa27x_device_ssp2 = {
607 	.name		= "pxa27x-ssp",
608 	.id		= 1,
609 	.dev		= {
610 		.dma_mask = &pxa27x_ssp2_dma_mask,
611 		.coherent_dma_mask = DMA_BIT_MASK(32),
612 	},
613 	.resource	= pxa27x_resource_ssp2,
614 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
615 };
616 
617 static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
618 
619 static struct resource pxa27x_resource_ssp3[] = {
620 	[0] = {
621 		.start	= 0x41900000,
622 		.end	= 0x4190003f,
623 		.flags	= IORESOURCE_MEM,
624 	},
625 	[1] = {
626 		.start	= IRQ_SSP3,
627 		.end	= IRQ_SSP3,
628 		.flags	= IORESOURCE_IRQ,
629 	},
630 	[2] = {
631 		/* DRCMR for RX */
632 		.start	= 66,
633 		.end	= 66,
634 		.flags	= IORESOURCE_DMA,
635 	},
636 	[3] = {
637 		/* DRCMR for TX */
638 		.start	= 67,
639 		.end	= 67,
640 		.flags	= IORESOURCE_DMA,
641 	},
642 };
643 
644 struct platform_device pxa27x_device_ssp3 = {
645 	.name		= "pxa27x-ssp",
646 	.id		= 2,
647 	.dev		= {
648 		.dma_mask = &pxa27x_ssp3_dma_mask,
649 		.coherent_dma_mask = DMA_BIT_MASK(32),
650 	},
651 	.resource	= pxa27x_resource_ssp3,
652 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
653 };
654 
655 static struct resource pxa27x_resource_pwm0[] = {
656 	[0] = {
657 		.start	= 0x40b00000,
658 		.end	= 0x40b0001f,
659 		.flags	= IORESOURCE_MEM,
660 	},
661 };
662 
663 struct platform_device pxa27x_device_pwm0 = {
664 	.name		= "pxa27x-pwm",
665 	.id		= 0,
666 	.resource	= pxa27x_resource_pwm0,
667 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm0),
668 };
669 
670 static struct resource pxa27x_resource_pwm1[] = {
671 	[0] = {
672 		.start	= 0x40c00000,
673 		.end	= 0x40c0001f,
674 		.flags	= IORESOURCE_MEM,
675 	},
676 };
677 
678 struct platform_device pxa27x_device_pwm1 = {
679 	.name		= "pxa27x-pwm",
680 	.id		= 1,
681 	.resource	= pxa27x_resource_pwm1,
682 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm1),
683 };
684 
685 static struct resource pxa27x_resource_camera[] = {
686 	[0] = {
687 		.start	= 0x50000000,
688 		.end	= 0x50000fff,
689 		.flags	= IORESOURCE_MEM,
690 	},
691 	[1] = {
692 		.start	= IRQ_CAMERA,
693 		.end	= IRQ_CAMERA,
694 		.flags	= IORESOURCE_IRQ,
695 	},
696 };
697 
698 static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
699 
700 static struct platform_device pxa27x_device_camera = {
701 	.name		= "pxa27x-camera",
702 	.id		= 0, /* This is used to put cameras on this interface */
703 	.dev		= {
704 		.dma_mask      		= &pxa27x_dma_mask_camera,
705 		.coherent_dma_mask	= 0xffffffff,
706 	},
707 	.num_resources	= ARRAY_SIZE(pxa27x_resource_camera),
708 	.resource	= pxa27x_resource_camera,
709 };
710 
711 void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
712 {
713 	pxa_register_device(&pxa27x_device_camera, info);
714 }
715 #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
716 
717 #ifdef CONFIG_PXA3xx
718 static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
719 
720 static struct resource pxa3xx_resource_ssp4[] = {
721 	[0] = {
722 		.start	= 0x41a00000,
723 		.end	= 0x41a0003f,
724 		.flags	= IORESOURCE_MEM,
725 	},
726 	[1] = {
727 		.start	= IRQ_SSP4,
728 		.end	= IRQ_SSP4,
729 		.flags	= IORESOURCE_IRQ,
730 	},
731 	[2] = {
732 		/* DRCMR for RX */
733 		.start	= 2,
734 		.end	= 2,
735 		.flags	= IORESOURCE_DMA,
736 	},
737 	[3] = {
738 		/* DRCMR for TX */
739 		.start	= 3,
740 		.end	= 3,
741 		.flags	= IORESOURCE_DMA,
742 	},
743 };
744 
745 struct platform_device pxa3xx_device_ssp4 = {
746 	/* PXA3xx SSP is basically equivalent to PXA27x */
747 	.name		= "pxa27x-ssp",
748 	.id		= 3,
749 	.dev		= {
750 		.dma_mask = &pxa3xx_ssp4_dma_mask,
751 		.coherent_dma_mask = DMA_BIT_MASK(32),
752 	},
753 	.resource	= pxa3xx_resource_ssp4,
754 	.num_resources	= ARRAY_SIZE(pxa3xx_resource_ssp4),
755 };
756 
757 static struct resource pxa3xx_resources_mci2[] = {
758 	[0] = {
759 		.start	= 0x42000000,
760 		.end	= 0x42000fff,
761 		.flags	= IORESOURCE_MEM,
762 	},
763 	[1] = {
764 		.start	= IRQ_MMC2,
765 		.end	= IRQ_MMC2,
766 		.flags	= IORESOURCE_IRQ,
767 	},
768 	[2] = {
769 		.start	= 93,
770 		.end	= 93,
771 		.flags	= IORESOURCE_DMA,
772 	},
773 	[3] = {
774 		.start	= 94,
775 		.end	= 94,
776 		.flags	= IORESOURCE_DMA,
777 	},
778 };
779 
780 struct platform_device pxa3xx_device_mci2 = {
781 	.name		= "pxa2xx-mci",
782 	.id		= 1,
783 	.dev		= {
784 		.dma_mask = &pxamci_dmamask,
785 		.coherent_dma_mask =	0xffffffff,
786 	},
787 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci2),
788 	.resource	= pxa3xx_resources_mci2,
789 };
790 
791 void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
792 {
793 	pxa_register_device(&pxa3xx_device_mci2, info);
794 }
795 
796 static struct resource pxa3xx_resources_mci3[] = {
797 	[0] = {
798 		.start	= 0x42500000,
799 		.end	= 0x42500fff,
800 		.flags	= IORESOURCE_MEM,
801 	},
802 	[1] = {
803 		.start	= IRQ_MMC3,
804 		.end	= IRQ_MMC3,
805 		.flags	= IORESOURCE_IRQ,
806 	},
807 	[2] = {
808 		.start	= 100,
809 		.end	= 100,
810 		.flags	= IORESOURCE_DMA,
811 	},
812 	[3] = {
813 		.start	= 101,
814 		.end	= 101,
815 		.flags	= IORESOURCE_DMA,
816 	},
817 };
818 
819 struct platform_device pxa3xx_device_mci3 = {
820 	.name		= "pxa2xx-mci",
821 	.id		= 2,
822 	.dev		= {
823 		.dma_mask = &pxamci_dmamask,
824 		.coherent_dma_mask = 0xffffffff,
825 	},
826 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci3),
827 	.resource	= pxa3xx_resources_mci3,
828 };
829 
830 void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
831 {
832 	pxa_register_device(&pxa3xx_device_mci3, info);
833 }
834 
835 static struct resource pxa3xx_resources_nand[] = {
836 	[0] = {
837 		.start	= 0x43100000,
838 		.end	= 0x43100053,
839 		.flags	= IORESOURCE_MEM,
840 	},
841 	[1] = {
842 		.start	= IRQ_NAND,
843 		.end	= IRQ_NAND,
844 		.flags	= IORESOURCE_IRQ,
845 	},
846 	[2] = {
847 		/* DRCMR for Data DMA */
848 		.start	= 97,
849 		.end	= 97,
850 		.flags	= IORESOURCE_DMA,
851 	},
852 	[3] = {
853 		/* DRCMR for Command DMA */
854 		.start	= 99,
855 		.end	= 99,
856 		.flags	= IORESOURCE_DMA,
857 	},
858 };
859 
860 static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
861 
862 struct platform_device pxa3xx_device_nand = {
863 	.name		= "pxa3xx-nand",
864 	.id		= -1,
865 	.dev		= {
866 		.dma_mask = &pxa3xx_nand_dma_mask,
867 		.coherent_dma_mask = DMA_BIT_MASK(32),
868 	},
869 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_nand),
870 	.resource	= pxa3xx_resources_nand,
871 };
872 
873 void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
874 {
875 	pxa_register_device(&pxa3xx_device_nand, info);
876 }
877 #endif /* CONFIG_PXA3xx */
878 
879 /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
880  * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
881 void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
882 {
883 	struct platform_device *pd;
884 
885 	pd = platform_device_alloc("pxa2xx-spi", id);
886 	if (pd == NULL) {
887 		printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
888 		       id);
889 		return;
890 	}
891 
892 	pd->dev.platform_data = info;
893 	platform_device_add(pd);
894 }
895