18f58de7cSeric miao #include <linux/module.h> 28f58de7cSeric miao #include <linux/kernel.h> 38f58de7cSeric miao #include <linux/init.h> 48f58de7cSeric miao #include <linux/platform_device.h> 58f58de7cSeric miao #include <linux/dma-mapping.h> 68f58de7cSeric miao 7a09e64fbSRussell King #include <mach/udc.h> 8a09e64fbSRussell King #include <mach/pxafb.h> 9a09e64fbSRussell King #include <mach/mmc.h> 10a09e64fbSRussell King #include <mach/irda.h> 11a09e64fbSRussell King #include <mach/ohci.h> 12a09e64fbSRussell King #include <mach/pxa27x_keypad.h> 13a09e64fbSRussell King #include <mach/pxa2xx_spi.h> 14a09e64fbSRussell King #include <mach/camera.h> 15a09e64fbSRussell King #include <mach/audio.h> 1675e874c6SEric Miao #include <mach/hardware.h> 1782b95ecbSHaojian Zhuang #include <plat/i2c.h> 1882b95ecbSHaojian Zhuang #include <plat/pxa3xx_nand.h> 198f58de7cSeric miao 208f58de7cSeric miao #include "devices.h" 21bc3a5959SPhilipp Zabel #include "generic.h" 228f58de7cSeric miao 238f58de7cSeric miao void __init pxa_register_device(struct platform_device *dev, void *data) 248f58de7cSeric miao { 258f58de7cSeric miao int ret; 268f58de7cSeric miao 278f58de7cSeric miao dev->dev.platform_data = data; 288f58de7cSeric miao 298f58de7cSeric miao ret = platform_device_register(dev); 308f58de7cSeric miao if (ret) 318f58de7cSeric miao dev_err(&dev->dev, "unable to register device: %d\n", ret); 328f58de7cSeric miao } 338f58de7cSeric miao 348f58de7cSeric miao static struct resource pxamci_resources[] = { 358f58de7cSeric miao [0] = { 368f58de7cSeric miao .start = 0x41100000, 378f58de7cSeric miao .end = 0x41100fff, 388f58de7cSeric miao .flags = IORESOURCE_MEM, 398f58de7cSeric miao }, 408f58de7cSeric miao [1] = { 418f58de7cSeric miao .start = IRQ_MMC, 428f58de7cSeric miao .end = IRQ_MMC, 438f58de7cSeric miao .flags = IORESOURCE_IRQ, 448f58de7cSeric miao }, 458f58de7cSeric miao [2] = { 468f58de7cSeric miao .start = 21, 478f58de7cSeric miao .end = 21, 488f58de7cSeric miao .flags = IORESOURCE_DMA, 498f58de7cSeric miao }, 508f58de7cSeric miao [3] = { 518f58de7cSeric miao .start = 22, 528f58de7cSeric miao .end = 22, 538f58de7cSeric miao .flags = IORESOURCE_DMA, 548f58de7cSeric miao }, 558f58de7cSeric miao }; 568f58de7cSeric miao 578f58de7cSeric miao static u64 pxamci_dmamask = 0xffffffffUL; 588f58de7cSeric miao 598f58de7cSeric miao struct platform_device pxa_device_mci = { 608f58de7cSeric miao .name = "pxa2xx-mci", 61fafc9d3fSBridge Wu .id = 0, 628f58de7cSeric miao .dev = { 638f58de7cSeric miao .dma_mask = &pxamci_dmamask, 648f58de7cSeric miao .coherent_dma_mask = 0xffffffff, 658f58de7cSeric miao }, 668f58de7cSeric miao .num_resources = ARRAY_SIZE(pxamci_resources), 678f58de7cSeric miao .resource = pxamci_resources, 688f58de7cSeric miao }; 698f58de7cSeric miao 708f58de7cSeric miao void __init pxa_set_mci_info(struct pxamci_platform_data *info) 718f58de7cSeric miao { 728f58de7cSeric miao pxa_register_device(&pxa_device_mci, info); 738f58de7cSeric miao } 748f58de7cSeric miao 758f58de7cSeric miao 761257629bSPhilipp Zabel static struct pxa2xx_udc_mach_info pxa_udc_info = { 771257629bSPhilipp Zabel .gpio_pullup = -1, 781257629bSPhilipp Zabel .gpio_vbus = -1, 791257629bSPhilipp Zabel }; 808f58de7cSeric miao 818f58de7cSeric miao void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info) 828f58de7cSeric miao { 838f58de7cSeric miao memcpy(&pxa_udc_info, info, sizeof *info); 848f58de7cSeric miao } 858f58de7cSeric miao 868f58de7cSeric miao static struct resource pxa2xx_udc_resources[] = { 878f58de7cSeric miao [0] = { 888f58de7cSeric miao .start = 0x40600000, 898f58de7cSeric miao .end = 0x4060ffff, 908f58de7cSeric miao .flags = IORESOURCE_MEM, 918f58de7cSeric miao }, 928f58de7cSeric miao [1] = { 938f58de7cSeric miao .start = IRQ_USB, 948f58de7cSeric miao .end = IRQ_USB, 958f58de7cSeric miao .flags = IORESOURCE_IRQ, 968f58de7cSeric miao }, 978f58de7cSeric miao }; 988f58de7cSeric miao 998f58de7cSeric miao static u64 udc_dma_mask = ~(u32)0; 1008f58de7cSeric miao 1017a857620SPhilipp Zabel struct platform_device pxa25x_device_udc = { 1027a857620SPhilipp Zabel .name = "pxa25x-udc", 1037a857620SPhilipp Zabel .id = -1, 1047a857620SPhilipp Zabel .resource = pxa2xx_udc_resources, 1057a857620SPhilipp Zabel .num_resources = ARRAY_SIZE(pxa2xx_udc_resources), 1067a857620SPhilipp Zabel .dev = { 1077a857620SPhilipp Zabel .platform_data = &pxa_udc_info, 1087a857620SPhilipp Zabel .dma_mask = &udc_dma_mask, 1097a857620SPhilipp Zabel } 1107a857620SPhilipp Zabel }; 1117a857620SPhilipp Zabel 1127a857620SPhilipp Zabel struct platform_device pxa27x_device_udc = { 1137a857620SPhilipp Zabel .name = "pxa27x-udc", 1148f58de7cSeric miao .id = -1, 1158f58de7cSeric miao .resource = pxa2xx_udc_resources, 1168f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa2xx_udc_resources), 1178f58de7cSeric miao .dev = { 1188f58de7cSeric miao .platform_data = &pxa_udc_info, 1198f58de7cSeric miao .dma_mask = &udc_dma_mask, 1208f58de7cSeric miao } 1218f58de7cSeric miao }; 1228f58de7cSeric miao 1238f58de7cSeric miao static struct resource pxafb_resources[] = { 1248f58de7cSeric miao [0] = { 1258f58de7cSeric miao .start = 0x44000000, 1268f58de7cSeric miao .end = 0x4400ffff, 1278f58de7cSeric miao .flags = IORESOURCE_MEM, 1288f58de7cSeric miao }, 1298f58de7cSeric miao [1] = { 1308f58de7cSeric miao .start = IRQ_LCD, 1318f58de7cSeric miao .end = IRQ_LCD, 1328f58de7cSeric miao .flags = IORESOURCE_IRQ, 1338f58de7cSeric miao }, 1348f58de7cSeric miao }; 1358f58de7cSeric miao 1368f58de7cSeric miao static u64 fb_dma_mask = ~(u64)0; 1378f58de7cSeric miao 1388f58de7cSeric miao struct platform_device pxa_device_fb = { 1398f58de7cSeric miao .name = "pxa2xx-fb", 1408f58de7cSeric miao .id = -1, 1418f58de7cSeric miao .dev = { 1428f58de7cSeric miao .dma_mask = &fb_dma_mask, 1438f58de7cSeric miao .coherent_dma_mask = 0xffffffff, 1448f58de7cSeric miao }, 1458f58de7cSeric miao .num_resources = ARRAY_SIZE(pxafb_resources), 1468f58de7cSeric miao .resource = pxafb_resources, 1478f58de7cSeric miao }; 1488f58de7cSeric miao 1498f58de7cSeric miao void __init set_pxa_fb_info(struct pxafb_mach_info *info) 1508f58de7cSeric miao { 1518f58de7cSeric miao pxa_register_device(&pxa_device_fb, info); 1528f58de7cSeric miao } 1538f58de7cSeric miao 1548f58de7cSeric miao void __init set_pxa_fb_parent(struct device *parent_dev) 1558f58de7cSeric miao { 1568f58de7cSeric miao pxa_device_fb.dev.parent = parent_dev; 1578f58de7cSeric miao } 1588f58de7cSeric miao 1598f58de7cSeric miao static struct resource pxa_resource_ffuart[] = { 1608f58de7cSeric miao { 16102f65262SEric Miao .start = 0x40100000, 16202f65262SEric Miao .end = 0x40100023, 1638f58de7cSeric miao .flags = IORESOURCE_MEM, 1648f58de7cSeric miao }, { 1658f58de7cSeric miao .start = IRQ_FFUART, 1668f58de7cSeric miao .end = IRQ_FFUART, 1678f58de7cSeric miao .flags = IORESOURCE_IRQ, 1688f58de7cSeric miao } 1698f58de7cSeric miao }; 1708f58de7cSeric miao 1718f58de7cSeric miao struct platform_device pxa_device_ffuart = { 1728f58de7cSeric miao .name = "pxa2xx-uart", 1738f58de7cSeric miao .id = 0, 1748f58de7cSeric miao .resource = pxa_resource_ffuart, 1758f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa_resource_ffuart), 1768f58de7cSeric miao }; 1778f58de7cSeric miao 178cc155c6fSRussell King void __init pxa_set_ffuart_info(void *info) 179cc155c6fSRussell King { 180cc155c6fSRussell King pxa_register_device(&pxa_device_ffuart, info); 181cc155c6fSRussell King } 182cc155c6fSRussell King 1838f58de7cSeric miao static struct resource pxa_resource_btuart[] = { 1848f58de7cSeric miao { 18502f65262SEric Miao .start = 0x40200000, 18602f65262SEric Miao .end = 0x40200023, 1878f58de7cSeric miao .flags = IORESOURCE_MEM, 1888f58de7cSeric miao }, { 1898f58de7cSeric miao .start = IRQ_BTUART, 1908f58de7cSeric miao .end = IRQ_BTUART, 1918f58de7cSeric miao .flags = IORESOURCE_IRQ, 1928f58de7cSeric miao } 1938f58de7cSeric miao }; 1948f58de7cSeric miao 1958f58de7cSeric miao struct platform_device pxa_device_btuart = { 1968f58de7cSeric miao .name = "pxa2xx-uart", 1978f58de7cSeric miao .id = 1, 1988f58de7cSeric miao .resource = pxa_resource_btuart, 1998f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa_resource_btuart), 2008f58de7cSeric miao }; 2018f58de7cSeric miao 202cc155c6fSRussell King void __init pxa_set_btuart_info(void *info) 203cc155c6fSRussell King { 204cc155c6fSRussell King pxa_register_device(&pxa_device_btuart, info); 205cc155c6fSRussell King } 206cc155c6fSRussell King 2078f58de7cSeric miao static struct resource pxa_resource_stuart[] = { 2088f58de7cSeric miao { 20902f65262SEric Miao .start = 0x40700000, 21002f65262SEric Miao .end = 0x40700023, 2118f58de7cSeric miao .flags = IORESOURCE_MEM, 2128f58de7cSeric miao }, { 2138f58de7cSeric miao .start = IRQ_STUART, 2148f58de7cSeric miao .end = IRQ_STUART, 2158f58de7cSeric miao .flags = IORESOURCE_IRQ, 2168f58de7cSeric miao } 2178f58de7cSeric miao }; 2188f58de7cSeric miao 2198f58de7cSeric miao struct platform_device pxa_device_stuart = { 2208f58de7cSeric miao .name = "pxa2xx-uart", 2218f58de7cSeric miao .id = 2, 2228f58de7cSeric miao .resource = pxa_resource_stuart, 2238f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa_resource_stuart), 2248f58de7cSeric miao }; 2258f58de7cSeric miao 226cc155c6fSRussell King void __init pxa_set_stuart_info(void *info) 227cc155c6fSRussell King { 228cc155c6fSRussell King pxa_register_device(&pxa_device_stuart, info); 229cc155c6fSRussell King } 230cc155c6fSRussell King 2318f58de7cSeric miao static struct resource pxa_resource_hwuart[] = { 2328f58de7cSeric miao { 23302f65262SEric Miao .start = 0x41600000, 23402f65262SEric Miao .end = 0x4160002F, 2358f58de7cSeric miao .flags = IORESOURCE_MEM, 2368f58de7cSeric miao }, { 2378f58de7cSeric miao .start = IRQ_HWUART, 2388f58de7cSeric miao .end = IRQ_HWUART, 2398f58de7cSeric miao .flags = IORESOURCE_IRQ, 2408f58de7cSeric miao } 2418f58de7cSeric miao }; 2428f58de7cSeric miao 2438f58de7cSeric miao struct platform_device pxa_device_hwuart = { 2448f58de7cSeric miao .name = "pxa2xx-uart", 2458f58de7cSeric miao .id = 3, 2468f58de7cSeric miao .resource = pxa_resource_hwuart, 2478f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa_resource_hwuart), 2488f58de7cSeric miao }; 2498f58de7cSeric miao 250cc155c6fSRussell King void __init pxa_set_hwuart_info(void *info) 251cc155c6fSRussell King { 252cc155c6fSRussell King if (cpu_is_pxa255()) 253cc155c6fSRussell King pxa_register_device(&pxa_device_hwuart, info); 254cc155c6fSRussell King else 255cc155c6fSRussell King pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware"); 256cc155c6fSRussell King } 257cc155c6fSRussell King 2588f58de7cSeric miao static struct resource pxai2c_resources[] = { 2598f58de7cSeric miao { 2608f58de7cSeric miao .start = 0x40301680, 2618f58de7cSeric miao .end = 0x403016a3, 2628f58de7cSeric miao .flags = IORESOURCE_MEM, 2638f58de7cSeric miao }, { 2648f58de7cSeric miao .start = IRQ_I2C, 2658f58de7cSeric miao .end = IRQ_I2C, 2668f58de7cSeric miao .flags = IORESOURCE_IRQ, 2678f58de7cSeric miao }, 2688f58de7cSeric miao }; 2698f58de7cSeric miao 2708f58de7cSeric miao struct platform_device pxa_device_i2c = { 2718f58de7cSeric miao .name = "pxa2xx-i2c", 2728f58de7cSeric miao .id = 0, 2738f58de7cSeric miao .resource = pxai2c_resources, 2748f58de7cSeric miao .num_resources = ARRAY_SIZE(pxai2c_resources), 2758f58de7cSeric miao }; 2768f58de7cSeric miao 2778f58de7cSeric miao void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) 2788f58de7cSeric miao { 2798f58de7cSeric miao pxa_register_device(&pxa_device_i2c, info); 2808f58de7cSeric miao } 2818f58de7cSeric miao 28299464293SEric Miao #ifdef CONFIG_PXA27x 28399464293SEric Miao static struct resource pxa27x_resources_i2c_power[] = { 28499464293SEric Miao { 28599464293SEric Miao .start = 0x40f00180, 28699464293SEric Miao .end = 0x40f001a3, 28799464293SEric Miao .flags = IORESOURCE_MEM, 28899464293SEric Miao }, { 28999464293SEric Miao .start = IRQ_PWRI2C, 29099464293SEric Miao .end = IRQ_PWRI2C, 29199464293SEric Miao .flags = IORESOURCE_IRQ, 29299464293SEric Miao }, 29399464293SEric Miao }; 29499464293SEric Miao 29599464293SEric Miao struct platform_device pxa27x_device_i2c_power = { 29699464293SEric Miao .name = "pxa2xx-i2c", 29799464293SEric Miao .id = 1, 29899464293SEric Miao .resource = pxa27x_resources_i2c_power, 29999464293SEric Miao .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power), 30099464293SEric Miao }; 30199464293SEric Miao #endif 30299464293SEric Miao 30399464293SEric Miao #ifdef CONFIG_PXA3xx 30499464293SEric Miao static struct resource pxa3xx_resources_i2c_power[] = { 30599464293SEric Miao { 30699464293SEric Miao .start = 0x40f500c0, 30799464293SEric Miao .end = 0x40f500d3, 30899464293SEric Miao .flags = IORESOURCE_MEM, 30999464293SEric Miao }, { 31099464293SEric Miao .start = IRQ_PWRI2C, 31199464293SEric Miao .end = IRQ_PWRI2C, 31299464293SEric Miao .flags = IORESOURCE_IRQ, 31399464293SEric Miao }, 31499464293SEric Miao }; 31599464293SEric Miao 31699464293SEric Miao struct platform_device pxa3xx_device_i2c_power = { 317f23d4911SEric Miao .name = "pxa3xx-pwri2c", 31899464293SEric Miao .id = 1, 31999464293SEric Miao .resource = pxa3xx_resources_i2c_power, 32099464293SEric Miao .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power), 32199464293SEric Miao }; 32299464293SEric Miao #endif 32399464293SEric Miao 3248f58de7cSeric miao static struct resource pxai2s_resources[] = { 3258f58de7cSeric miao { 3268f58de7cSeric miao .start = 0x40400000, 3278f58de7cSeric miao .end = 0x40400083, 3288f58de7cSeric miao .flags = IORESOURCE_MEM, 3298f58de7cSeric miao }, { 3308f58de7cSeric miao .start = IRQ_I2S, 3318f58de7cSeric miao .end = IRQ_I2S, 3328f58de7cSeric miao .flags = IORESOURCE_IRQ, 3338f58de7cSeric miao }, 3348f58de7cSeric miao }; 3358f58de7cSeric miao 3368f58de7cSeric miao struct platform_device pxa_device_i2s = { 3378f58de7cSeric miao .name = "pxa2xx-i2s", 3388f58de7cSeric miao .id = -1, 3398f58de7cSeric miao .resource = pxai2s_resources, 3408f58de7cSeric miao .num_resources = ARRAY_SIZE(pxai2s_resources), 3418f58de7cSeric miao }; 3428f58de7cSeric miao 343*f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp1 = { 344*f0fba2adSLiam Girdwood .name = "pxa-ssp-dai", 345*f0fba2adSLiam Girdwood .id = 0, 346*f0fba2adSLiam Girdwood }; 347*f0fba2adSLiam Girdwood 348*f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp2= { 349*f0fba2adSLiam Girdwood .name = "pxa-ssp-dai", 350*f0fba2adSLiam Girdwood .id = 1, 351*f0fba2adSLiam Girdwood }; 352*f0fba2adSLiam Girdwood 353*f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp3 = { 354*f0fba2adSLiam Girdwood .name = "pxa-ssp-dai", 355*f0fba2adSLiam Girdwood .id = 2, 356*f0fba2adSLiam Girdwood }; 357*f0fba2adSLiam Girdwood 358*f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp4 = { 359*f0fba2adSLiam Girdwood .name = "pxa-ssp-dai", 360*f0fba2adSLiam Girdwood .id = 3, 361*f0fba2adSLiam Girdwood }; 362*f0fba2adSLiam Girdwood 363*f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_platform = { 364*f0fba2adSLiam Girdwood .name = "pxa-pcm-audio", 365*f0fba2adSLiam Girdwood .id = -1, 366*f0fba2adSLiam Girdwood }; 367*f0fba2adSLiam Girdwood 3688f58de7cSeric miao static u64 pxaficp_dmamask = ~(u32)0; 3698f58de7cSeric miao 3708f58de7cSeric miao struct platform_device pxa_device_ficp = { 3718f58de7cSeric miao .name = "pxa2xx-ir", 3728f58de7cSeric miao .id = -1, 3738f58de7cSeric miao .dev = { 3748f58de7cSeric miao .dma_mask = &pxaficp_dmamask, 3758f58de7cSeric miao .coherent_dma_mask = 0xffffffff, 3768f58de7cSeric miao }, 3778f58de7cSeric miao }; 3788f58de7cSeric miao 3798f58de7cSeric miao void __init pxa_set_ficp_info(struct pxaficp_platform_data *info) 3808f58de7cSeric miao { 3818f58de7cSeric miao pxa_register_device(&pxa_device_ficp, info); 3828f58de7cSeric miao } 3838f58de7cSeric miao 38472493146SRobert Jarzmik static struct resource pxa_rtc_resources[] = { 38572493146SRobert Jarzmik [0] = { 38672493146SRobert Jarzmik .start = 0x40900000, 38772493146SRobert Jarzmik .end = 0x40900000 + 0x3b, 38872493146SRobert Jarzmik .flags = IORESOURCE_MEM, 38972493146SRobert Jarzmik }, 39072493146SRobert Jarzmik [1] = { 39172493146SRobert Jarzmik .start = IRQ_RTC1Hz, 39272493146SRobert Jarzmik .end = IRQ_RTC1Hz, 39372493146SRobert Jarzmik .flags = IORESOURCE_IRQ, 39472493146SRobert Jarzmik }, 39572493146SRobert Jarzmik [2] = { 39672493146SRobert Jarzmik .start = IRQ_RTCAlrm, 39772493146SRobert Jarzmik .end = IRQ_RTCAlrm, 39872493146SRobert Jarzmik .flags = IORESOURCE_IRQ, 39972493146SRobert Jarzmik }, 40072493146SRobert Jarzmik }; 40172493146SRobert Jarzmik 40272493146SRobert Jarzmik struct platform_device sa1100_device_rtc = { 4038f58de7cSeric miao .name = "sa1100-rtc", 4048f58de7cSeric miao .id = -1, 4058f58de7cSeric miao }; 4068f58de7cSeric miao 40772493146SRobert Jarzmik struct platform_device pxa_device_rtc = { 40872493146SRobert Jarzmik .name = "pxa-rtc", 40972493146SRobert Jarzmik .id = -1, 41072493146SRobert Jarzmik .num_resources = ARRAY_SIZE(pxa_rtc_resources), 41172493146SRobert Jarzmik .resource = pxa_rtc_resources, 41272493146SRobert Jarzmik }; 41372493146SRobert Jarzmik 4149f19d638SMark Brown static struct resource pxa_ac97_resources[] = { 4159f19d638SMark Brown [0] = { 4169f19d638SMark Brown .start = 0x40500000, 4179f19d638SMark Brown .end = 0x40500000 + 0xfff, 4189f19d638SMark Brown .flags = IORESOURCE_MEM, 4199f19d638SMark Brown }, 4209f19d638SMark Brown [1] = { 4219f19d638SMark Brown .start = IRQ_AC97, 4229f19d638SMark Brown .end = IRQ_AC97, 4239f19d638SMark Brown .flags = IORESOURCE_IRQ, 4249f19d638SMark Brown }, 4259f19d638SMark Brown }; 4269f19d638SMark Brown 4279f19d638SMark Brown static u64 pxa_ac97_dmamask = 0xffffffffUL; 4289f19d638SMark Brown 4299f19d638SMark Brown struct platform_device pxa_device_ac97 = { 4309f19d638SMark Brown .name = "pxa2xx-ac97", 4319f19d638SMark Brown .id = -1, 4329f19d638SMark Brown .dev = { 4339f19d638SMark Brown .dma_mask = &pxa_ac97_dmamask, 4349f19d638SMark Brown .coherent_dma_mask = 0xffffffff, 4359f19d638SMark Brown }, 4369f19d638SMark Brown .num_resources = ARRAY_SIZE(pxa_ac97_resources), 4379f19d638SMark Brown .resource = pxa_ac97_resources, 4389f19d638SMark Brown }; 4399f19d638SMark Brown 4409f19d638SMark Brown void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops) 4419f19d638SMark Brown { 4429f19d638SMark Brown pxa_register_device(&pxa_device_ac97, ops); 4439f19d638SMark Brown } 4449f19d638SMark Brown 4458f58de7cSeric miao #ifdef CONFIG_PXA25x 4468f58de7cSeric miao 44775540c1aSeric miao static struct resource pxa25x_resource_pwm0[] = { 44875540c1aSeric miao [0] = { 44975540c1aSeric miao .start = 0x40b00000, 45075540c1aSeric miao .end = 0x40b0000f, 45175540c1aSeric miao .flags = IORESOURCE_MEM, 45275540c1aSeric miao }, 45375540c1aSeric miao }; 45475540c1aSeric miao 45575540c1aSeric miao struct platform_device pxa25x_device_pwm0 = { 45675540c1aSeric miao .name = "pxa25x-pwm", 45775540c1aSeric miao .id = 0, 45875540c1aSeric miao .resource = pxa25x_resource_pwm0, 45975540c1aSeric miao .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0), 46075540c1aSeric miao }; 46175540c1aSeric miao 46275540c1aSeric miao static struct resource pxa25x_resource_pwm1[] = { 46375540c1aSeric miao [0] = { 46475540c1aSeric miao .start = 0x40c00000, 46575540c1aSeric miao .end = 0x40c0000f, 46675540c1aSeric miao .flags = IORESOURCE_MEM, 46775540c1aSeric miao }, 46875540c1aSeric miao }; 46975540c1aSeric miao 47075540c1aSeric miao struct platform_device pxa25x_device_pwm1 = { 47175540c1aSeric miao .name = "pxa25x-pwm", 47275540c1aSeric miao .id = 1, 47375540c1aSeric miao .resource = pxa25x_resource_pwm1, 47475540c1aSeric miao .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1), 47575540c1aSeric miao }; 47675540c1aSeric miao 4778f58de7cSeric miao static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32); 4788f58de7cSeric miao 4798f58de7cSeric miao static struct resource pxa25x_resource_ssp[] = { 4808f58de7cSeric miao [0] = { 4818f58de7cSeric miao .start = 0x41000000, 4828f58de7cSeric miao .end = 0x4100001f, 4838f58de7cSeric miao .flags = IORESOURCE_MEM, 4848f58de7cSeric miao }, 4858f58de7cSeric miao [1] = { 4868f58de7cSeric miao .start = IRQ_SSP, 4878f58de7cSeric miao .end = IRQ_SSP, 4888f58de7cSeric miao .flags = IORESOURCE_IRQ, 4898f58de7cSeric miao }, 4908f58de7cSeric miao [2] = { 4918f58de7cSeric miao /* DRCMR for RX */ 4928f58de7cSeric miao .start = 13, 4938f58de7cSeric miao .end = 13, 4948f58de7cSeric miao .flags = IORESOURCE_DMA, 4958f58de7cSeric miao }, 4968f58de7cSeric miao [3] = { 4978f58de7cSeric miao /* DRCMR for TX */ 4988f58de7cSeric miao .start = 14, 4998f58de7cSeric miao .end = 14, 5008f58de7cSeric miao .flags = IORESOURCE_DMA, 5018f58de7cSeric miao }, 5028f58de7cSeric miao }; 5038f58de7cSeric miao 5048f58de7cSeric miao struct platform_device pxa25x_device_ssp = { 5058f58de7cSeric miao .name = "pxa25x-ssp", 5068f58de7cSeric miao .id = 0, 5078f58de7cSeric miao .dev = { 5088f58de7cSeric miao .dma_mask = &pxa25x_ssp_dma_mask, 5098f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 5108f58de7cSeric miao }, 5118f58de7cSeric miao .resource = pxa25x_resource_ssp, 5128f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa25x_resource_ssp), 5138f58de7cSeric miao }; 5148f58de7cSeric miao 5158f58de7cSeric miao static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32); 5168f58de7cSeric miao 5178f58de7cSeric miao static struct resource pxa25x_resource_nssp[] = { 5188f58de7cSeric miao [0] = { 5198f58de7cSeric miao .start = 0x41400000, 5208f58de7cSeric miao .end = 0x4140002f, 5218f58de7cSeric miao .flags = IORESOURCE_MEM, 5228f58de7cSeric miao }, 5238f58de7cSeric miao [1] = { 5248f58de7cSeric miao .start = IRQ_NSSP, 5258f58de7cSeric miao .end = IRQ_NSSP, 5268f58de7cSeric miao .flags = IORESOURCE_IRQ, 5278f58de7cSeric miao }, 5288f58de7cSeric miao [2] = { 5298f58de7cSeric miao /* DRCMR for RX */ 5308f58de7cSeric miao .start = 15, 5318f58de7cSeric miao .end = 15, 5328f58de7cSeric miao .flags = IORESOURCE_DMA, 5338f58de7cSeric miao }, 5348f58de7cSeric miao [3] = { 5358f58de7cSeric miao /* DRCMR for TX */ 5368f58de7cSeric miao .start = 16, 5378f58de7cSeric miao .end = 16, 5388f58de7cSeric miao .flags = IORESOURCE_DMA, 5398f58de7cSeric miao }, 5408f58de7cSeric miao }; 5418f58de7cSeric miao 5428f58de7cSeric miao struct platform_device pxa25x_device_nssp = { 5438f58de7cSeric miao .name = "pxa25x-nssp", 5448f58de7cSeric miao .id = 1, 5458f58de7cSeric miao .dev = { 5468f58de7cSeric miao .dma_mask = &pxa25x_nssp_dma_mask, 5478f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 5488f58de7cSeric miao }, 5498f58de7cSeric miao .resource = pxa25x_resource_nssp, 5508f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa25x_resource_nssp), 5518f58de7cSeric miao }; 5528f58de7cSeric miao 5538f58de7cSeric miao static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32); 5548f58de7cSeric miao 5558f58de7cSeric miao static struct resource pxa25x_resource_assp[] = { 5568f58de7cSeric miao [0] = { 5578f58de7cSeric miao .start = 0x41500000, 5588f58de7cSeric miao .end = 0x4150002f, 5598f58de7cSeric miao .flags = IORESOURCE_MEM, 5608f58de7cSeric miao }, 5618f58de7cSeric miao [1] = { 5628f58de7cSeric miao .start = IRQ_ASSP, 5638f58de7cSeric miao .end = IRQ_ASSP, 5648f58de7cSeric miao .flags = IORESOURCE_IRQ, 5658f58de7cSeric miao }, 5668f58de7cSeric miao [2] = { 5678f58de7cSeric miao /* DRCMR for RX */ 5688f58de7cSeric miao .start = 23, 5698f58de7cSeric miao .end = 23, 5708f58de7cSeric miao .flags = IORESOURCE_DMA, 5718f58de7cSeric miao }, 5728f58de7cSeric miao [3] = { 5738f58de7cSeric miao /* DRCMR for TX */ 5748f58de7cSeric miao .start = 24, 5758f58de7cSeric miao .end = 24, 5768f58de7cSeric miao .flags = IORESOURCE_DMA, 5778f58de7cSeric miao }, 5788f58de7cSeric miao }; 5798f58de7cSeric miao 5808f58de7cSeric miao struct platform_device pxa25x_device_assp = { 5818f58de7cSeric miao /* ASSP is basically equivalent to NSSP */ 5828f58de7cSeric miao .name = "pxa25x-nssp", 5838f58de7cSeric miao .id = 2, 5848f58de7cSeric miao .dev = { 5858f58de7cSeric miao .dma_mask = &pxa25x_assp_dma_mask, 5868f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 5878f58de7cSeric miao }, 5888f58de7cSeric miao .resource = pxa25x_resource_assp, 5898f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa25x_resource_assp), 5908f58de7cSeric miao }; 5918f58de7cSeric miao #endif /* CONFIG_PXA25x */ 5928f58de7cSeric miao 5938f58de7cSeric miao #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 5948f58de7cSeric miao 59537320980Seric miao static struct resource pxa27x_resource_keypad[] = { 59637320980Seric miao [0] = { 59737320980Seric miao .start = 0x41500000, 59837320980Seric miao .end = 0x4150004c, 59937320980Seric miao .flags = IORESOURCE_MEM, 60037320980Seric miao }, 60137320980Seric miao [1] = { 60237320980Seric miao .start = IRQ_KEYPAD, 60337320980Seric miao .end = IRQ_KEYPAD, 60437320980Seric miao .flags = IORESOURCE_IRQ, 60537320980Seric miao }, 60637320980Seric miao }; 60737320980Seric miao 60837320980Seric miao struct platform_device pxa27x_device_keypad = { 60937320980Seric miao .name = "pxa27x-keypad", 61037320980Seric miao .id = -1, 61137320980Seric miao .resource = pxa27x_resource_keypad, 61237320980Seric miao .num_resources = ARRAY_SIZE(pxa27x_resource_keypad), 61337320980Seric miao }; 61437320980Seric miao 61537320980Seric miao void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info) 61637320980Seric miao { 61737320980Seric miao pxa_register_device(&pxa27x_device_keypad, info); 61837320980Seric miao } 61937320980Seric miao 620ec68e45bSeric miao static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32); 621ec68e45bSeric miao 622ec68e45bSeric miao static struct resource pxa27x_resource_ohci[] = { 623ec68e45bSeric miao [0] = { 624ec68e45bSeric miao .start = 0x4C000000, 625ec68e45bSeric miao .end = 0x4C00ff6f, 626ec68e45bSeric miao .flags = IORESOURCE_MEM, 627ec68e45bSeric miao }, 628ec68e45bSeric miao [1] = { 629ec68e45bSeric miao .start = IRQ_USBH1, 630ec68e45bSeric miao .end = IRQ_USBH1, 631ec68e45bSeric miao .flags = IORESOURCE_IRQ, 632ec68e45bSeric miao }, 633ec68e45bSeric miao }; 634ec68e45bSeric miao 635ec68e45bSeric miao struct platform_device pxa27x_device_ohci = { 636ec68e45bSeric miao .name = "pxa27x-ohci", 637ec68e45bSeric miao .id = -1, 638ec68e45bSeric miao .dev = { 639ec68e45bSeric miao .dma_mask = &pxa27x_ohci_dma_mask, 640ec68e45bSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 641ec68e45bSeric miao }, 642ec68e45bSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_ohci), 643ec68e45bSeric miao .resource = pxa27x_resource_ohci, 644ec68e45bSeric miao }; 645ec68e45bSeric miao 646ec68e45bSeric miao void __init pxa_set_ohci_info(struct pxaohci_platform_data *info) 647ec68e45bSeric miao { 648ec68e45bSeric miao pxa_register_device(&pxa27x_device_ohci, info); 649ec68e45bSeric miao } 650ec68e45bSeric miao 6518f58de7cSeric miao static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32); 6528f58de7cSeric miao 6538f58de7cSeric miao static struct resource pxa27x_resource_ssp1[] = { 6548f58de7cSeric miao [0] = { 6558f58de7cSeric miao .start = 0x41000000, 6568f58de7cSeric miao .end = 0x4100003f, 6578f58de7cSeric miao .flags = IORESOURCE_MEM, 6588f58de7cSeric miao }, 6598f58de7cSeric miao [1] = { 6608f58de7cSeric miao .start = IRQ_SSP, 6618f58de7cSeric miao .end = IRQ_SSP, 6628f58de7cSeric miao .flags = IORESOURCE_IRQ, 6638f58de7cSeric miao }, 6648f58de7cSeric miao [2] = { 6658f58de7cSeric miao /* DRCMR for RX */ 6668f58de7cSeric miao .start = 13, 6678f58de7cSeric miao .end = 13, 6688f58de7cSeric miao .flags = IORESOURCE_DMA, 6698f58de7cSeric miao }, 6708f58de7cSeric miao [3] = { 6718f58de7cSeric miao /* DRCMR for TX */ 6728f58de7cSeric miao .start = 14, 6738f58de7cSeric miao .end = 14, 6748f58de7cSeric miao .flags = IORESOURCE_DMA, 6758f58de7cSeric miao }, 6768f58de7cSeric miao }; 6778f58de7cSeric miao 6788f58de7cSeric miao struct platform_device pxa27x_device_ssp1 = { 6798f58de7cSeric miao .name = "pxa27x-ssp", 6808f58de7cSeric miao .id = 0, 6818f58de7cSeric miao .dev = { 6828f58de7cSeric miao .dma_mask = &pxa27x_ssp1_dma_mask, 6838f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 6848f58de7cSeric miao }, 6858f58de7cSeric miao .resource = pxa27x_resource_ssp1, 6868f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1), 6878f58de7cSeric miao }; 6888f58de7cSeric miao 6898f58de7cSeric miao static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32); 6908f58de7cSeric miao 6918f58de7cSeric miao static struct resource pxa27x_resource_ssp2[] = { 6928f58de7cSeric miao [0] = { 6938f58de7cSeric miao .start = 0x41700000, 6948f58de7cSeric miao .end = 0x4170003f, 6958f58de7cSeric miao .flags = IORESOURCE_MEM, 6968f58de7cSeric miao }, 6978f58de7cSeric miao [1] = { 6988f58de7cSeric miao .start = IRQ_SSP2, 6998f58de7cSeric miao .end = IRQ_SSP2, 7008f58de7cSeric miao .flags = IORESOURCE_IRQ, 7018f58de7cSeric miao }, 7028f58de7cSeric miao [2] = { 7038f58de7cSeric miao /* DRCMR for RX */ 7048f58de7cSeric miao .start = 15, 7058f58de7cSeric miao .end = 15, 7068f58de7cSeric miao .flags = IORESOURCE_DMA, 7078f58de7cSeric miao }, 7088f58de7cSeric miao [3] = { 7098f58de7cSeric miao /* DRCMR for TX */ 7108f58de7cSeric miao .start = 16, 7118f58de7cSeric miao .end = 16, 7128f58de7cSeric miao .flags = IORESOURCE_DMA, 7138f58de7cSeric miao }, 7148f58de7cSeric miao }; 7158f58de7cSeric miao 7168f58de7cSeric miao struct platform_device pxa27x_device_ssp2 = { 7178f58de7cSeric miao .name = "pxa27x-ssp", 7188f58de7cSeric miao .id = 1, 7198f58de7cSeric miao .dev = { 7208f58de7cSeric miao .dma_mask = &pxa27x_ssp2_dma_mask, 7218f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 7228f58de7cSeric miao }, 7238f58de7cSeric miao .resource = pxa27x_resource_ssp2, 7248f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2), 7258f58de7cSeric miao }; 7268f58de7cSeric miao 7278f58de7cSeric miao static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32); 7288f58de7cSeric miao 7298f58de7cSeric miao static struct resource pxa27x_resource_ssp3[] = { 7308f58de7cSeric miao [0] = { 7318f58de7cSeric miao .start = 0x41900000, 7328f58de7cSeric miao .end = 0x4190003f, 7338f58de7cSeric miao .flags = IORESOURCE_MEM, 7348f58de7cSeric miao }, 7358f58de7cSeric miao [1] = { 7368f58de7cSeric miao .start = IRQ_SSP3, 7378f58de7cSeric miao .end = IRQ_SSP3, 7388f58de7cSeric miao .flags = IORESOURCE_IRQ, 7398f58de7cSeric miao }, 7408f58de7cSeric miao [2] = { 7418f58de7cSeric miao /* DRCMR for RX */ 7428f58de7cSeric miao .start = 66, 7438f58de7cSeric miao .end = 66, 7448f58de7cSeric miao .flags = IORESOURCE_DMA, 7458f58de7cSeric miao }, 7468f58de7cSeric miao [3] = { 7478f58de7cSeric miao /* DRCMR for TX */ 7488f58de7cSeric miao .start = 67, 7498f58de7cSeric miao .end = 67, 7508f58de7cSeric miao .flags = IORESOURCE_DMA, 7518f58de7cSeric miao }, 7528f58de7cSeric miao }; 7538f58de7cSeric miao 7548f58de7cSeric miao struct platform_device pxa27x_device_ssp3 = { 7558f58de7cSeric miao .name = "pxa27x-ssp", 7568f58de7cSeric miao .id = 2, 7578f58de7cSeric miao .dev = { 7588f58de7cSeric miao .dma_mask = &pxa27x_ssp3_dma_mask, 7598f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 7608f58de7cSeric miao }, 7618f58de7cSeric miao .resource = pxa27x_resource_ssp3, 7628f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3), 7638f58de7cSeric miao }; 7643f3acefbSGuennadi Liakhovetski 76575540c1aSeric miao static struct resource pxa27x_resource_pwm0[] = { 76675540c1aSeric miao [0] = { 76775540c1aSeric miao .start = 0x40b00000, 76875540c1aSeric miao .end = 0x40b0001f, 76975540c1aSeric miao .flags = IORESOURCE_MEM, 77075540c1aSeric miao }, 77175540c1aSeric miao }; 77275540c1aSeric miao 77375540c1aSeric miao struct platform_device pxa27x_device_pwm0 = { 77475540c1aSeric miao .name = "pxa27x-pwm", 77575540c1aSeric miao .id = 0, 77675540c1aSeric miao .resource = pxa27x_resource_pwm0, 77775540c1aSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0), 77875540c1aSeric miao }; 77975540c1aSeric miao 78075540c1aSeric miao static struct resource pxa27x_resource_pwm1[] = { 78175540c1aSeric miao [0] = { 78275540c1aSeric miao .start = 0x40c00000, 78375540c1aSeric miao .end = 0x40c0001f, 78475540c1aSeric miao .flags = IORESOURCE_MEM, 78575540c1aSeric miao }, 78675540c1aSeric miao }; 78775540c1aSeric miao 78875540c1aSeric miao struct platform_device pxa27x_device_pwm1 = { 78975540c1aSeric miao .name = "pxa27x-pwm", 79075540c1aSeric miao .id = 1, 79175540c1aSeric miao .resource = pxa27x_resource_pwm1, 79275540c1aSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1), 79375540c1aSeric miao }; 79475540c1aSeric miao 7953f3acefbSGuennadi Liakhovetski static struct resource pxa27x_resource_camera[] = { 7963f3acefbSGuennadi Liakhovetski [0] = { 7973f3acefbSGuennadi Liakhovetski .start = 0x50000000, 7983f3acefbSGuennadi Liakhovetski .end = 0x50000fff, 7993f3acefbSGuennadi Liakhovetski .flags = IORESOURCE_MEM, 8003f3acefbSGuennadi Liakhovetski }, 8013f3acefbSGuennadi Liakhovetski [1] = { 8023f3acefbSGuennadi Liakhovetski .start = IRQ_CAMERA, 8033f3acefbSGuennadi Liakhovetski .end = IRQ_CAMERA, 8043f3acefbSGuennadi Liakhovetski .flags = IORESOURCE_IRQ, 8053f3acefbSGuennadi Liakhovetski }, 8063f3acefbSGuennadi Liakhovetski }; 8073f3acefbSGuennadi Liakhovetski 8083f3acefbSGuennadi Liakhovetski static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32); 8093f3acefbSGuennadi Liakhovetski 8103f3acefbSGuennadi Liakhovetski static struct platform_device pxa27x_device_camera = { 8113f3acefbSGuennadi Liakhovetski .name = "pxa27x-camera", 8123f3acefbSGuennadi Liakhovetski .id = 0, /* This is used to put cameras on this interface */ 8133f3acefbSGuennadi Liakhovetski .dev = { 8143f3acefbSGuennadi Liakhovetski .dma_mask = &pxa27x_dma_mask_camera, 8153f3acefbSGuennadi Liakhovetski .coherent_dma_mask = 0xffffffff, 8163f3acefbSGuennadi Liakhovetski }, 8173f3acefbSGuennadi Liakhovetski .num_resources = ARRAY_SIZE(pxa27x_resource_camera), 8183f3acefbSGuennadi Liakhovetski .resource = pxa27x_resource_camera, 8193f3acefbSGuennadi Liakhovetski }; 8203f3acefbSGuennadi Liakhovetski 8213f3acefbSGuennadi Liakhovetski void __init pxa_set_camera_info(struct pxacamera_platform_data *info) 8223f3acefbSGuennadi Liakhovetski { 8233f3acefbSGuennadi Liakhovetski pxa_register_device(&pxa27x_device_camera, info); 8243f3acefbSGuennadi Liakhovetski } 8258f58de7cSeric miao #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ 8268f58de7cSeric miao 8278f58de7cSeric miao #ifdef CONFIG_PXA3xx 8288f58de7cSeric miao static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32); 8298f58de7cSeric miao 8308f58de7cSeric miao static struct resource pxa3xx_resource_ssp4[] = { 8318f58de7cSeric miao [0] = { 8328f58de7cSeric miao .start = 0x41a00000, 8338f58de7cSeric miao .end = 0x41a0003f, 8348f58de7cSeric miao .flags = IORESOURCE_MEM, 8358f58de7cSeric miao }, 8368f58de7cSeric miao [1] = { 8378f58de7cSeric miao .start = IRQ_SSP4, 8388f58de7cSeric miao .end = IRQ_SSP4, 8398f58de7cSeric miao .flags = IORESOURCE_IRQ, 8408f58de7cSeric miao }, 8418f58de7cSeric miao [2] = { 8428f58de7cSeric miao /* DRCMR for RX */ 8438f58de7cSeric miao .start = 2, 8448f58de7cSeric miao .end = 2, 8458f58de7cSeric miao .flags = IORESOURCE_DMA, 8468f58de7cSeric miao }, 8478f58de7cSeric miao [3] = { 8488f58de7cSeric miao /* DRCMR for TX */ 8498f58de7cSeric miao .start = 3, 8508f58de7cSeric miao .end = 3, 8518f58de7cSeric miao .flags = IORESOURCE_DMA, 8528f58de7cSeric miao }, 8538f58de7cSeric miao }; 8548f58de7cSeric miao 8558f58de7cSeric miao struct platform_device pxa3xx_device_ssp4 = { 8568f58de7cSeric miao /* PXA3xx SSP is basically equivalent to PXA27x */ 8578f58de7cSeric miao .name = "pxa27x-ssp", 8588f58de7cSeric miao .id = 3, 8598f58de7cSeric miao .dev = { 8608f58de7cSeric miao .dma_mask = &pxa3xx_ssp4_dma_mask, 8618f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 8628f58de7cSeric miao }, 8638f58de7cSeric miao .resource = pxa3xx_resource_ssp4, 8648f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4), 8658f58de7cSeric miao }; 8668d33b055SBridge Wu 8678d33b055SBridge Wu static struct resource pxa3xx_resources_mci2[] = { 8688d33b055SBridge Wu [0] = { 8698d33b055SBridge Wu .start = 0x42000000, 8708d33b055SBridge Wu .end = 0x42000fff, 8718d33b055SBridge Wu .flags = IORESOURCE_MEM, 8728d33b055SBridge Wu }, 8738d33b055SBridge Wu [1] = { 8748d33b055SBridge Wu .start = IRQ_MMC2, 8758d33b055SBridge Wu .end = IRQ_MMC2, 8768d33b055SBridge Wu .flags = IORESOURCE_IRQ, 8778d33b055SBridge Wu }, 8788d33b055SBridge Wu [2] = { 8798d33b055SBridge Wu .start = 93, 8808d33b055SBridge Wu .end = 93, 8818d33b055SBridge Wu .flags = IORESOURCE_DMA, 8828d33b055SBridge Wu }, 8838d33b055SBridge Wu [3] = { 8848d33b055SBridge Wu .start = 94, 8858d33b055SBridge Wu .end = 94, 8868d33b055SBridge Wu .flags = IORESOURCE_DMA, 8878d33b055SBridge Wu }, 8888d33b055SBridge Wu }; 8898d33b055SBridge Wu 8908d33b055SBridge Wu struct platform_device pxa3xx_device_mci2 = { 8918d33b055SBridge Wu .name = "pxa2xx-mci", 8928d33b055SBridge Wu .id = 1, 8938d33b055SBridge Wu .dev = { 8948d33b055SBridge Wu .dma_mask = &pxamci_dmamask, 8958d33b055SBridge Wu .coherent_dma_mask = 0xffffffff, 8968d33b055SBridge Wu }, 8978d33b055SBridge Wu .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2), 8988d33b055SBridge Wu .resource = pxa3xx_resources_mci2, 8998d33b055SBridge Wu }; 9008d33b055SBridge Wu 9018d33b055SBridge Wu void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info) 9028d33b055SBridge Wu { 9038d33b055SBridge Wu pxa_register_device(&pxa3xx_device_mci2, info); 9048d33b055SBridge Wu } 9058d33b055SBridge Wu 9065a1f21b1SBridge Wu static struct resource pxa3xx_resources_mci3[] = { 9075a1f21b1SBridge Wu [0] = { 9085a1f21b1SBridge Wu .start = 0x42500000, 9095a1f21b1SBridge Wu .end = 0x42500fff, 9105a1f21b1SBridge Wu .flags = IORESOURCE_MEM, 9115a1f21b1SBridge Wu }, 9125a1f21b1SBridge Wu [1] = { 9135a1f21b1SBridge Wu .start = IRQ_MMC3, 9145a1f21b1SBridge Wu .end = IRQ_MMC3, 9155a1f21b1SBridge Wu .flags = IORESOURCE_IRQ, 9165a1f21b1SBridge Wu }, 9175a1f21b1SBridge Wu [2] = { 9185a1f21b1SBridge Wu .start = 100, 9195a1f21b1SBridge Wu .end = 100, 9205a1f21b1SBridge Wu .flags = IORESOURCE_DMA, 9215a1f21b1SBridge Wu }, 9225a1f21b1SBridge Wu [3] = { 9235a1f21b1SBridge Wu .start = 101, 9245a1f21b1SBridge Wu .end = 101, 9255a1f21b1SBridge Wu .flags = IORESOURCE_DMA, 9265a1f21b1SBridge Wu }, 9275a1f21b1SBridge Wu }; 9285a1f21b1SBridge Wu 9295a1f21b1SBridge Wu struct platform_device pxa3xx_device_mci3 = { 9305a1f21b1SBridge Wu .name = "pxa2xx-mci", 9315a1f21b1SBridge Wu .id = 2, 9325a1f21b1SBridge Wu .dev = { 9335a1f21b1SBridge Wu .dma_mask = &pxamci_dmamask, 9345a1f21b1SBridge Wu .coherent_dma_mask = 0xffffffff, 9355a1f21b1SBridge Wu }, 9365a1f21b1SBridge Wu .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3), 9375a1f21b1SBridge Wu .resource = pxa3xx_resources_mci3, 9385a1f21b1SBridge Wu }; 9395a1f21b1SBridge Wu 9405a1f21b1SBridge Wu void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info) 9415a1f21b1SBridge Wu { 9425a1f21b1SBridge Wu pxa_register_device(&pxa3xx_device_mci3, info); 9435a1f21b1SBridge Wu } 9445a1f21b1SBridge Wu 9459ae819a8SEric Miao static struct resource pxa3xx_resources_nand[] = { 9469ae819a8SEric Miao [0] = { 9479ae819a8SEric Miao .start = 0x43100000, 9489ae819a8SEric Miao .end = 0x43100053, 9499ae819a8SEric Miao .flags = IORESOURCE_MEM, 9509ae819a8SEric Miao }, 9519ae819a8SEric Miao [1] = { 9529ae819a8SEric Miao .start = IRQ_NAND, 9539ae819a8SEric Miao .end = IRQ_NAND, 9549ae819a8SEric Miao .flags = IORESOURCE_IRQ, 9559ae819a8SEric Miao }, 9569ae819a8SEric Miao [2] = { 9579ae819a8SEric Miao /* DRCMR for Data DMA */ 9589ae819a8SEric Miao .start = 97, 9599ae819a8SEric Miao .end = 97, 9609ae819a8SEric Miao .flags = IORESOURCE_DMA, 9619ae819a8SEric Miao }, 9629ae819a8SEric Miao [3] = { 9639ae819a8SEric Miao /* DRCMR for Command DMA */ 9649ae819a8SEric Miao .start = 99, 9659ae819a8SEric Miao .end = 99, 9669ae819a8SEric Miao .flags = IORESOURCE_DMA, 9679ae819a8SEric Miao }, 9689ae819a8SEric Miao }; 9699ae819a8SEric Miao 9709ae819a8SEric Miao static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32); 9719ae819a8SEric Miao 9729ae819a8SEric Miao struct platform_device pxa3xx_device_nand = { 9739ae819a8SEric Miao .name = "pxa3xx-nand", 9749ae819a8SEric Miao .id = -1, 9759ae819a8SEric Miao .dev = { 9769ae819a8SEric Miao .dma_mask = &pxa3xx_nand_dma_mask, 9779ae819a8SEric Miao .coherent_dma_mask = DMA_BIT_MASK(32), 9789ae819a8SEric Miao }, 9799ae819a8SEric Miao .num_resources = ARRAY_SIZE(pxa3xx_resources_nand), 9809ae819a8SEric Miao .resource = pxa3xx_resources_nand, 9819ae819a8SEric Miao }; 9829ae819a8SEric Miao 9839ae819a8SEric Miao void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info) 9849ae819a8SEric Miao { 9859ae819a8SEric Miao pxa_register_device(&pxa3xx_device_nand, info); 9869ae819a8SEric Miao } 9871ff2c33eSDaniel Mack 9881ff2c33eSDaniel Mack static struct resource pxa3xx_resources_gcu[] = { 9891ff2c33eSDaniel Mack { 9901ff2c33eSDaniel Mack .start = 0x54000000, 9911ff2c33eSDaniel Mack .end = 0x54000fff, 9921ff2c33eSDaniel Mack .flags = IORESOURCE_MEM, 9931ff2c33eSDaniel Mack }, 9941ff2c33eSDaniel Mack { 9951ff2c33eSDaniel Mack .start = IRQ_GCU, 9961ff2c33eSDaniel Mack .end = IRQ_GCU, 9971ff2c33eSDaniel Mack .flags = IORESOURCE_IRQ, 9981ff2c33eSDaniel Mack }, 9991ff2c33eSDaniel Mack }; 10001ff2c33eSDaniel Mack 10011ff2c33eSDaniel Mack static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32); 10021ff2c33eSDaniel Mack 10031ff2c33eSDaniel Mack struct platform_device pxa3xx_device_gcu = { 10041ff2c33eSDaniel Mack .name = "pxa3xx-gcu", 10051ff2c33eSDaniel Mack .id = -1, 10061ff2c33eSDaniel Mack .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu), 10071ff2c33eSDaniel Mack .resource = pxa3xx_resources_gcu, 10081ff2c33eSDaniel Mack .dev = { 10091ff2c33eSDaniel Mack .dma_mask = &pxa3xx_gcu_dmamask, 10101ff2c33eSDaniel Mack .coherent_dma_mask = 0xffffffff, 10111ff2c33eSDaniel Mack }, 10121ff2c33eSDaniel Mack }; 10131ff2c33eSDaniel Mack 10148f58de7cSeric miao #endif /* CONFIG_PXA3xx */ 1015e172274cSGuennadi Liakhovetski 1016e172274cSGuennadi Liakhovetski /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1. 1017e172274cSGuennadi Liakhovetski * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */ 1018e172274cSGuennadi Liakhovetski void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info) 1019e172274cSGuennadi Liakhovetski { 1020e172274cSGuennadi Liakhovetski struct platform_device *pd; 1021e172274cSGuennadi Liakhovetski 1022e172274cSGuennadi Liakhovetski pd = platform_device_alloc("pxa2xx-spi", id); 1023e172274cSGuennadi Liakhovetski if (pd == NULL) { 1024e172274cSGuennadi Liakhovetski printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n", 1025e172274cSGuennadi Liakhovetski id); 1026e172274cSGuennadi Liakhovetski return; 1027e172274cSGuennadi Liakhovetski } 1028e172274cSGuennadi Liakhovetski 1029e172274cSGuennadi Liakhovetski pd->dev.platform_data = info; 1030e172274cSGuennadi Liakhovetski platform_device_add(pd); 1031e172274cSGuennadi Liakhovetski } 1032