xref: /linux/arch/arm/mach-pxa/devices.c (revision df3d17e068bf69e3c5a53d52d30caad3d061b762)
18f58de7cSeric miao #include <linux/module.h>
28f58de7cSeric miao #include <linux/kernel.h>
38f58de7cSeric miao #include <linux/init.h>
48f58de7cSeric miao #include <linux/platform_device.h>
58f58de7cSeric miao #include <linux/dma-mapping.h>
68348c259SSebastian Andrzej Siewior #include <linux/spi/pxa2xx_spi.h>
7b459396eSSebastian Andrzej Siewior #include <linux/i2c/pxa-i2c.h>
88f58de7cSeric miao 
9a09e64fbSRussell King #include <mach/udc.h>
1069f22be7SIgor Grinberg #include <mach/pxa3xx-u2d.h>
11a09e64fbSRussell King #include <mach/pxafb.h>
12a09e64fbSRussell King #include <mach/mmc.h>
13a09e64fbSRussell King #include <mach/irda.h>
144e611091SRob Herring #include <mach/irqs.h>
15a09e64fbSRussell King #include <mach/ohci.h>
164a2490eaSMark F. Brown #include <plat/pxa27x_keypad.h>
17a09e64fbSRussell King #include <mach/camera.h>
18a09e64fbSRussell King #include <mach/audio.h>
1975e874c6SEric Miao #include <mach/hardware.h>
2082b95ecbSHaojian Zhuang #include <plat/pxa3xx_nand.h>
218f58de7cSeric miao 
228f58de7cSeric miao #include "devices.h"
23bc3a5959SPhilipp Zabel #include "generic.h"
248f58de7cSeric miao 
258f58de7cSeric miao void __init pxa_register_device(struct platform_device *dev, void *data)
268f58de7cSeric miao {
278f58de7cSeric miao 	int ret;
288f58de7cSeric miao 
298f58de7cSeric miao 	dev->dev.platform_data = data;
308f58de7cSeric miao 
318f58de7cSeric miao 	ret = platform_device_register(dev);
328f58de7cSeric miao 	if (ret)
338f58de7cSeric miao 		dev_err(&dev->dev, "unable to register device: %d\n", ret);
348f58de7cSeric miao }
358f58de7cSeric miao 
3609a5358dSEric Miao static struct resource pxa_resource_pmu = {
3709a5358dSEric Miao 	.start	= IRQ_PMU,
3809a5358dSEric Miao 	.end	= IRQ_PMU,
3909a5358dSEric Miao 	.flags	= IORESOURCE_IRQ,
4009a5358dSEric Miao };
4109a5358dSEric Miao 
4209a5358dSEric Miao struct platform_device pxa_device_pmu = {
4309a5358dSEric Miao 	.name		= "arm-pmu",
44*df3d17e0SSudeep KarkadaNagesha 	.id		= -1,
4509a5358dSEric Miao 	.resource	= &pxa_resource_pmu,
4609a5358dSEric Miao 	.num_resources	= 1,
4709a5358dSEric Miao };
4809a5358dSEric Miao 
498f58de7cSeric miao static struct resource pxamci_resources[] = {
508f58de7cSeric miao 	[0] = {
518f58de7cSeric miao 		.start	= 0x41100000,
528f58de7cSeric miao 		.end	= 0x41100fff,
538f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
548f58de7cSeric miao 	},
558f58de7cSeric miao 	[1] = {
568f58de7cSeric miao 		.start	= IRQ_MMC,
578f58de7cSeric miao 		.end	= IRQ_MMC,
588f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
598f58de7cSeric miao 	},
608f58de7cSeric miao 	[2] = {
618f58de7cSeric miao 		.start	= 21,
628f58de7cSeric miao 		.end	= 21,
638f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
648f58de7cSeric miao 	},
658f58de7cSeric miao 	[3] = {
668f58de7cSeric miao 		.start	= 22,
678f58de7cSeric miao 		.end	= 22,
688f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
698f58de7cSeric miao 	},
708f58de7cSeric miao };
718f58de7cSeric miao 
728f58de7cSeric miao static u64 pxamci_dmamask = 0xffffffffUL;
738f58de7cSeric miao 
748f58de7cSeric miao struct platform_device pxa_device_mci = {
758f58de7cSeric miao 	.name		= "pxa2xx-mci",
76fafc9d3fSBridge Wu 	.id		= 0,
778f58de7cSeric miao 	.dev		= {
788f58de7cSeric miao 		.dma_mask = &pxamci_dmamask,
798f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
808f58de7cSeric miao 	},
818f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxamci_resources),
828f58de7cSeric miao 	.resource	= pxamci_resources,
838f58de7cSeric miao };
848f58de7cSeric miao 
858f58de7cSeric miao void __init pxa_set_mci_info(struct pxamci_platform_data *info)
868f58de7cSeric miao {
878f58de7cSeric miao 	pxa_register_device(&pxa_device_mci, info);
888f58de7cSeric miao }
898f58de7cSeric miao 
908f58de7cSeric miao 
911257629bSPhilipp Zabel static struct pxa2xx_udc_mach_info pxa_udc_info = {
921257629bSPhilipp Zabel 	.gpio_pullup = -1,
931257629bSPhilipp Zabel };
948f58de7cSeric miao 
958f58de7cSeric miao void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
968f58de7cSeric miao {
978f58de7cSeric miao 	memcpy(&pxa_udc_info, info, sizeof *info);
988f58de7cSeric miao }
998f58de7cSeric miao 
1008f58de7cSeric miao static struct resource pxa2xx_udc_resources[] = {
1018f58de7cSeric miao 	[0] = {
1028f58de7cSeric miao 		.start	= 0x40600000,
1038f58de7cSeric miao 		.end	= 0x4060ffff,
1048f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1058f58de7cSeric miao 	},
1068f58de7cSeric miao 	[1] = {
1078f58de7cSeric miao 		.start	= IRQ_USB,
1088f58de7cSeric miao 		.end	= IRQ_USB,
1098f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1108f58de7cSeric miao 	},
1118f58de7cSeric miao };
1128f58de7cSeric miao 
1138f58de7cSeric miao static u64 udc_dma_mask = ~(u32)0;
1148f58de7cSeric miao 
1157a857620SPhilipp Zabel struct platform_device pxa25x_device_udc = {
1167a857620SPhilipp Zabel 	.name		= "pxa25x-udc",
1177a857620SPhilipp Zabel 	.id		= -1,
1187a857620SPhilipp Zabel 	.resource	= pxa2xx_udc_resources,
1197a857620SPhilipp Zabel 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
1207a857620SPhilipp Zabel 	.dev		=  {
1217a857620SPhilipp Zabel 		.platform_data	= &pxa_udc_info,
1227a857620SPhilipp Zabel 		.dma_mask	= &udc_dma_mask,
1237a857620SPhilipp Zabel 	}
1247a857620SPhilipp Zabel };
1257a857620SPhilipp Zabel 
1267a857620SPhilipp Zabel struct platform_device pxa27x_device_udc = {
1277a857620SPhilipp Zabel 	.name		= "pxa27x-udc",
1288f58de7cSeric miao 	.id		= -1,
1298f58de7cSeric miao 	.resource	= pxa2xx_udc_resources,
1308f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
1318f58de7cSeric miao 	.dev		=  {
1328f58de7cSeric miao 		.platform_data	= &pxa_udc_info,
1338f58de7cSeric miao 		.dma_mask	= &udc_dma_mask,
1348f58de7cSeric miao 	}
1358f58de7cSeric miao };
1368f58de7cSeric miao 
13769f22be7SIgor Grinberg #ifdef CONFIG_PXA3xx
13869f22be7SIgor Grinberg static struct resource pxa3xx_u2d_resources[] = {
13969f22be7SIgor Grinberg 	[0] = {
14069f22be7SIgor Grinberg 		.start	= 0x54100000,
14169f22be7SIgor Grinberg 		.end	= 0x54100fff,
14269f22be7SIgor Grinberg 		.flags	= IORESOURCE_MEM,
14369f22be7SIgor Grinberg 	},
14469f22be7SIgor Grinberg 	[1] = {
14569f22be7SIgor Grinberg 		.start	= IRQ_USB2,
14669f22be7SIgor Grinberg 		.end	= IRQ_USB2,
14769f22be7SIgor Grinberg 		.flags	= IORESOURCE_IRQ,
14869f22be7SIgor Grinberg 	},
14969f22be7SIgor Grinberg };
15069f22be7SIgor Grinberg 
15169f22be7SIgor Grinberg struct platform_device pxa3xx_device_u2d = {
15269f22be7SIgor Grinberg 	.name		= "pxa3xx-u2d",
15369f22be7SIgor Grinberg 	.id		= -1,
15469f22be7SIgor Grinberg 	.resource	= pxa3xx_u2d_resources,
15569f22be7SIgor Grinberg 	.num_resources	= ARRAY_SIZE(pxa3xx_u2d_resources),
15669f22be7SIgor Grinberg };
15769f22be7SIgor Grinberg 
15869f22be7SIgor Grinberg void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
15969f22be7SIgor Grinberg {
16069f22be7SIgor Grinberg 	pxa_register_device(&pxa3xx_device_u2d, info);
16169f22be7SIgor Grinberg }
16269f22be7SIgor Grinberg #endif /* CONFIG_PXA3xx */
16369f22be7SIgor Grinberg 
1648f58de7cSeric miao static struct resource pxafb_resources[] = {
1658f58de7cSeric miao 	[0] = {
1668f58de7cSeric miao 		.start	= 0x44000000,
1678f58de7cSeric miao 		.end	= 0x4400ffff,
1688f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1698f58de7cSeric miao 	},
1708f58de7cSeric miao 	[1] = {
1718f58de7cSeric miao 		.start	= IRQ_LCD,
1728f58de7cSeric miao 		.end	= IRQ_LCD,
1738f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1748f58de7cSeric miao 	},
1758f58de7cSeric miao };
1768f58de7cSeric miao 
1778f58de7cSeric miao static u64 fb_dma_mask = ~(u64)0;
1788f58de7cSeric miao 
1798f58de7cSeric miao struct platform_device pxa_device_fb = {
1808f58de7cSeric miao 	.name		= "pxa2xx-fb",
1818f58de7cSeric miao 	.id		= -1,
1828f58de7cSeric miao 	.dev		= {
1838f58de7cSeric miao 		.dma_mask	= &fb_dma_mask,
1848f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
1858f58de7cSeric miao 	},
1868f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxafb_resources),
1878f58de7cSeric miao 	.resource	= pxafb_resources,
1888f58de7cSeric miao };
1898f58de7cSeric miao 
1904321e1a1SRussell King - ARM Linux void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
1918f58de7cSeric miao {
1924321e1a1SRussell King - ARM Linux 	pxa_device_fb.dev.parent = parent;
1938f58de7cSeric miao 	pxa_register_device(&pxa_device_fb, info);
1948f58de7cSeric miao }
1958f58de7cSeric miao 
1968f58de7cSeric miao static struct resource pxa_resource_ffuart[] = {
1978f58de7cSeric miao 	{
19802f65262SEric Miao 		.start	= 0x40100000,
19902f65262SEric Miao 		.end	= 0x40100023,
2008f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2018f58de7cSeric miao 	}, {
2028f58de7cSeric miao 		.start	= IRQ_FFUART,
2038f58de7cSeric miao 		.end	= IRQ_FFUART,
2048f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2058f58de7cSeric miao 	}
2068f58de7cSeric miao };
2078f58de7cSeric miao 
2088f58de7cSeric miao struct platform_device pxa_device_ffuart = {
2098f58de7cSeric miao 	.name		= "pxa2xx-uart",
2108f58de7cSeric miao 	.id		= 0,
2118f58de7cSeric miao 	.resource	= pxa_resource_ffuart,
2128f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_ffuart),
2138f58de7cSeric miao };
2148f58de7cSeric miao 
215cc155c6fSRussell King void __init pxa_set_ffuart_info(void *info)
216cc155c6fSRussell King {
217cc155c6fSRussell King 	pxa_register_device(&pxa_device_ffuart, info);
218cc155c6fSRussell King }
219cc155c6fSRussell King 
2208f58de7cSeric miao static struct resource pxa_resource_btuart[] = {
2218f58de7cSeric miao 	{
22202f65262SEric Miao 		.start	= 0x40200000,
22302f65262SEric Miao 		.end	= 0x40200023,
2248f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2258f58de7cSeric miao 	}, {
2268f58de7cSeric miao 		.start	= IRQ_BTUART,
2278f58de7cSeric miao 		.end	= IRQ_BTUART,
2288f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2298f58de7cSeric miao 	}
2308f58de7cSeric miao };
2318f58de7cSeric miao 
2328f58de7cSeric miao struct platform_device pxa_device_btuart = {
2338f58de7cSeric miao 	.name		= "pxa2xx-uart",
2348f58de7cSeric miao 	.id		= 1,
2358f58de7cSeric miao 	.resource	= pxa_resource_btuart,
2368f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_btuart),
2378f58de7cSeric miao };
2388f58de7cSeric miao 
239cc155c6fSRussell King void __init pxa_set_btuart_info(void *info)
240cc155c6fSRussell King {
241cc155c6fSRussell King 	pxa_register_device(&pxa_device_btuart, info);
242cc155c6fSRussell King }
243cc155c6fSRussell King 
2448f58de7cSeric miao static struct resource pxa_resource_stuart[] = {
2458f58de7cSeric miao 	{
24602f65262SEric Miao 		.start	= 0x40700000,
24702f65262SEric Miao 		.end	= 0x40700023,
2488f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2498f58de7cSeric miao 	}, {
2508f58de7cSeric miao 		.start	= IRQ_STUART,
2518f58de7cSeric miao 		.end	= IRQ_STUART,
2528f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2538f58de7cSeric miao 	}
2548f58de7cSeric miao };
2558f58de7cSeric miao 
2568f58de7cSeric miao struct platform_device pxa_device_stuart = {
2578f58de7cSeric miao 	.name		= "pxa2xx-uart",
2588f58de7cSeric miao 	.id		= 2,
2598f58de7cSeric miao 	.resource	= pxa_resource_stuart,
2608f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_stuart),
2618f58de7cSeric miao };
2628f58de7cSeric miao 
263cc155c6fSRussell King void __init pxa_set_stuart_info(void *info)
264cc155c6fSRussell King {
265cc155c6fSRussell King 	pxa_register_device(&pxa_device_stuart, info);
266cc155c6fSRussell King }
267cc155c6fSRussell King 
2688f58de7cSeric miao static struct resource pxa_resource_hwuart[] = {
2698f58de7cSeric miao 	{
27002f65262SEric Miao 		.start	= 0x41600000,
27102f65262SEric Miao 		.end	= 0x4160002F,
2728f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2738f58de7cSeric miao 	}, {
2748f58de7cSeric miao 		.start	= IRQ_HWUART,
2758f58de7cSeric miao 		.end	= IRQ_HWUART,
2768f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2778f58de7cSeric miao 	}
2788f58de7cSeric miao };
2798f58de7cSeric miao 
2808f58de7cSeric miao struct platform_device pxa_device_hwuart = {
2818f58de7cSeric miao 	.name		= "pxa2xx-uart",
2828f58de7cSeric miao 	.id		= 3,
2838f58de7cSeric miao 	.resource	= pxa_resource_hwuart,
2848f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
2858f58de7cSeric miao };
2868f58de7cSeric miao 
287cc155c6fSRussell King void __init pxa_set_hwuart_info(void *info)
288cc155c6fSRussell King {
289cc155c6fSRussell King 	if (cpu_is_pxa255())
290cc155c6fSRussell King 		pxa_register_device(&pxa_device_hwuart, info);
291cc155c6fSRussell King 	else
292cc155c6fSRussell King 		pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
293cc155c6fSRussell King }
294cc155c6fSRussell King 
2958f58de7cSeric miao static struct resource pxai2c_resources[] = {
2968f58de7cSeric miao 	{
2978f58de7cSeric miao 		.start	= 0x40301680,
2988f58de7cSeric miao 		.end	= 0x403016a3,
2998f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3008f58de7cSeric miao 	}, {
3018f58de7cSeric miao 		.start	= IRQ_I2C,
3028f58de7cSeric miao 		.end	= IRQ_I2C,
3038f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3048f58de7cSeric miao 	},
3058f58de7cSeric miao };
3068f58de7cSeric miao 
3078f58de7cSeric miao struct platform_device pxa_device_i2c = {
3088f58de7cSeric miao 	.name		= "pxa2xx-i2c",
3098f58de7cSeric miao 	.id		= 0,
3108f58de7cSeric miao 	.resource	= pxai2c_resources,
3118f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2c_resources),
3128f58de7cSeric miao };
3138f58de7cSeric miao 
3148f58de7cSeric miao void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
3158f58de7cSeric miao {
3168f58de7cSeric miao 	pxa_register_device(&pxa_device_i2c, info);
3178f58de7cSeric miao }
3188f58de7cSeric miao 
31999464293SEric Miao #ifdef CONFIG_PXA27x
32099464293SEric Miao static struct resource pxa27x_resources_i2c_power[] = {
32199464293SEric Miao 	{
32299464293SEric Miao 		.start	= 0x40f00180,
32399464293SEric Miao 		.end	= 0x40f001a3,
32499464293SEric Miao 		.flags	= IORESOURCE_MEM,
32599464293SEric Miao 	}, {
32699464293SEric Miao 		.start	= IRQ_PWRI2C,
32799464293SEric Miao 		.end	= IRQ_PWRI2C,
32899464293SEric Miao 		.flags	= IORESOURCE_IRQ,
32999464293SEric Miao 	},
33099464293SEric Miao };
33199464293SEric Miao 
33299464293SEric Miao struct platform_device pxa27x_device_i2c_power = {
33399464293SEric Miao 	.name		= "pxa2xx-i2c",
33499464293SEric Miao 	.id		= 1,
33599464293SEric Miao 	.resource	= pxa27x_resources_i2c_power,
33699464293SEric Miao 	.num_resources	= ARRAY_SIZE(pxa27x_resources_i2c_power),
33799464293SEric Miao };
33899464293SEric Miao #endif
33999464293SEric Miao 
3408f58de7cSeric miao static struct resource pxai2s_resources[] = {
3418f58de7cSeric miao 	{
3428f58de7cSeric miao 		.start	= 0x40400000,
3438f58de7cSeric miao 		.end	= 0x40400083,
3448f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3458f58de7cSeric miao 	}, {
3468f58de7cSeric miao 		.start	= IRQ_I2S,
3478f58de7cSeric miao 		.end	= IRQ_I2S,
3488f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3498f58de7cSeric miao 	},
3508f58de7cSeric miao };
3518f58de7cSeric miao 
3528f58de7cSeric miao struct platform_device pxa_device_i2s = {
3538f58de7cSeric miao 	.name		= "pxa2xx-i2s",
3548f58de7cSeric miao 	.id		= -1,
3558f58de7cSeric miao 	.resource	= pxai2s_resources,
3568f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2s_resources),
3578f58de7cSeric miao };
3588f58de7cSeric miao 
359f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp1 = {
360f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
361f0fba2adSLiam Girdwood 	.id		= 0,
362f0fba2adSLiam Girdwood };
363f0fba2adSLiam Girdwood 
364f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp2= {
365f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
366f0fba2adSLiam Girdwood 	.id		= 1,
367f0fba2adSLiam Girdwood };
368f0fba2adSLiam Girdwood 
369f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp3 = {
370f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
371f0fba2adSLiam Girdwood 	.id		= 2,
372f0fba2adSLiam Girdwood };
373f0fba2adSLiam Girdwood 
374f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp4 = {
375f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
376f0fba2adSLiam Girdwood 	.id		= 3,
377f0fba2adSLiam Girdwood };
378f0fba2adSLiam Girdwood 
379f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_platform = {
380f0fba2adSLiam Girdwood 	.name		= "pxa-pcm-audio",
381f0fba2adSLiam Girdwood 	.id		= -1,
382f0fba2adSLiam Girdwood };
383f0fba2adSLiam Girdwood 
3848f58de7cSeric miao static u64 pxaficp_dmamask = ~(u32)0;
3858f58de7cSeric miao 
3868f58de7cSeric miao struct platform_device pxa_device_ficp = {
3878f58de7cSeric miao 	.name		= "pxa2xx-ir",
3888f58de7cSeric miao 	.id		= -1,
3898f58de7cSeric miao 	.dev		= {
3908f58de7cSeric miao 		.dma_mask = &pxaficp_dmamask,
3918f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
3928f58de7cSeric miao 	},
3938f58de7cSeric miao };
3948f58de7cSeric miao 
3958f58de7cSeric miao void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
3968f58de7cSeric miao {
3978f58de7cSeric miao 	pxa_register_device(&pxa_device_ficp, info);
3988f58de7cSeric miao }
3998f58de7cSeric miao 
40072493146SRobert Jarzmik static struct resource pxa_rtc_resources[] = {
40172493146SRobert Jarzmik 	[0] = {
40272493146SRobert Jarzmik 		.start  = 0x40900000,
40372493146SRobert Jarzmik 		.end	= 0x40900000 + 0x3b,
40472493146SRobert Jarzmik 		.flags  = IORESOURCE_MEM,
40572493146SRobert Jarzmik 	},
40672493146SRobert Jarzmik 	[1] = {
40772493146SRobert Jarzmik 		.start  = IRQ_RTC1Hz,
40872493146SRobert Jarzmik 		.end    = IRQ_RTC1Hz,
4093888c090SHaojian Zhuang 		.name	= "rtc 1Hz",
41072493146SRobert Jarzmik 		.flags  = IORESOURCE_IRQ,
41172493146SRobert Jarzmik 	},
41272493146SRobert Jarzmik 	[2] = {
41372493146SRobert Jarzmik 		.start  = IRQ_RTCAlrm,
41472493146SRobert Jarzmik 		.end    = IRQ_RTCAlrm,
4153888c090SHaojian Zhuang 		.name	= "rtc alarm",
41672493146SRobert Jarzmik 		.flags  = IORESOURCE_IRQ,
41772493146SRobert Jarzmik 	},
41872493146SRobert Jarzmik };
41972493146SRobert Jarzmik 
42072493146SRobert Jarzmik struct platform_device pxa_device_rtc = {
42172493146SRobert Jarzmik 	.name		= "pxa-rtc",
42272493146SRobert Jarzmik 	.id		= -1,
42372493146SRobert Jarzmik 	.num_resources  = ARRAY_SIZE(pxa_rtc_resources),
42472493146SRobert Jarzmik 	.resource       = pxa_rtc_resources,
42572493146SRobert Jarzmik };
42672493146SRobert Jarzmik 
4273888c090SHaojian Zhuang static struct resource sa1100_rtc_resources[] = {
4283888c090SHaojian Zhuang 	{
4293888c090SHaojian Zhuang 		.start  = IRQ_RTC1Hz,
4303888c090SHaojian Zhuang 		.end    = IRQ_RTC1Hz,
4313888c090SHaojian Zhuang 		.name	= "rtc 1Hz",
4323888c090SHaojian Zhuang 		.flags  = IORESOURCE_IRQ,
4333888c090SHaojian Zhuang 	}, {
4343888c090SHaojian Zhuang 		.start  = IRQ_RTCAlrm,
4353888c090SHaojian Zhuang 		.end    = IRQ_RTCAlrm,
4363888c090SHaojian Zhuang 		.name	= "rtc alarm",
4373888c090SHaojian Zhuang 		.flags  = IORESOURCE_IRQ,
4383888c090SHaojian Zhuang 	},
4393888c090SHaojian Zhuang };
4403888c090SHaojian Zhuang 
4413888c090SHaojian Zhuang struct platform_device sa1100_device_rtc = {
4423888c090SHaojian Zhuang 	.name		= "sa1100-rtc",
4433888c090SHaojian Zhuang 	.id		= -1,
4443888c090SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(sa1100_rtc_resources),
4453888c090SHaojian Zhuang 	.resource	= sa1100_rtc_resources,
4463888c090SHaojian Zhuang };
4473888c090SHaojian Zhuang 
4489f19d638SMark Brown static struct resource pxa_ac97_resources[] = {
4499f19d638SMark Brown 	[0] = {
4509f19d638SMark Brown 		.start  = 0x40500000,
4519f19d638SMark Brown 		.end	= 0x40500000 + 0xfff,
4529f19d638SMark Brown 		.flags  = IORESOURCE_MEM,
4539f19d638SMark Brown 	},
4549f19d638SMark Brown 	[1] = {
4559f19d638SMark Brown 		.start  = IRQ_AC97,
4569f19d638SMark Brown 		.end    = IRQ_AC97,
4579f19d638SMark Brown 		.flags  = IORESOURCE_IRQ,
4589f19d638SMark Brown 	},
4599f19d638SMark Brown };
4609f19d638SMark Brown 
4619f19d638SMark Brown static u64 pxa_ac97_dmamask = 0xffffffffUL;
4629f19d638SMark Brown 
4639f19d638SMark Brown struct platform_device pxa_device_ac97 = {
4649f19d638SMark Brown 	.name           = "pxa2xx-ac97",
4659f19d638SMark Brown 	.id             = -1,
4669f19d638SMark Brown 	.dev            = {
4679f19d638SMark Brown 		.dma_mask = &pxa_ac97_dmamask,
4689f19d638SMark Brown 		.coherent_dma_mask = 0xffffffff,
4699f19d638SMark Brown 	},
4709f19d638SMark Brown 	.num_resources  = ARRAY_SIZE(pxa_ac97_resources),
4719f19d638SMark Brown 	.resource       = pxa_ac97_resources,
4729f19d638SMark Brown };
4739f19d638SMark Brown 
4749f19d638SMark Brown void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
4759f19d638SMark Brown {
4769f19d638SMark Brown 	pxa_register_device(&pxa_device_ac97, ops);
4779f19d638SMark Brown }
4789f19d638SMark Brown 
4798f58de7cSeric miao #ifdef CONFIG_PXA25x
4808f58de7cSeric miao 
48175540c1aSeric miao static struct resource pxa25x_resource_pwm0[] = {
48275540c1aSeric miao 	[0] = {
48375540c1aSeric miao 		.start	= 0x40b00000,
48475540c1aSeric miao 		.end	= 0x40b0000f,
48575540c1aSeric miao 		.flags	= IORESOURCE_MEM,
48675540c1aSeric miao 	},
48775540c1aSeric miao };
48875540c1aSeric miao 
48975540c1aSeric miao struct platform_device pxa25x_device_pwm0 = {
49075540c1aSeric miao 	.name		= "pxa25x-pwm",
49175540c1aSeric miao 	.id		= 0,
49275540c1aSeric miao 	.resource	= pxa25x_resource_pwm0,
49375540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm0),
49475540c1aSeric miao };
49575540c1aSeric miao 
49675540c1aSeric miao static struct resource pxa25x_resource_pwm1[] = {
49775540c1aSeric miao 	[0] = {
49875540c1aSeric miao 		.start	= 0x40c00000,
49975540c1aSeric miao 		.end	= 0x40c0000f,
50075540c1aSeric miao 		.flags	= IORESOURCE_MEM,
50175540c1aSeric miao 	},
50275540c1aSeric miao };
50375540c1aSeric miao 
50475540c1aSeric miao struct platform_device pxa25x_device_pwm1 = {
50575540c1aSeric miao 	.name		= "pxa25x-pwm",
50675540c1aSeric miao 	.id		= 1,
50775540c1aSeric miao 	.resource	= pxa25x_resource_pwm1,
50875540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm1),
50975540c1aSeric miao };
51075540c1aSeric miao 
5118f58de7cSeric miao static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
5128f58de7cSeric miao 
5138f58de7cSeric miao static struct resource pxa25x_resource_ssp[] = {
5148f58de7cSeric miao 	[0] = {
5158f58de7cSeric miao 		.start	= 0x41000000,
5168f58de7cSeric miao 		.end	= 0x4100001f,
5178f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5188f58de7cSeric miao 	},
5198f58de7cSeric miao 	[1] = {
5208f58de7cSeric miao 		.start	= IRQ_SSP,
5218f58de7cSeric miao 		.end	= IRQ_SSP,
5228f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5238f58de7cSeric miao 	},
5248f58de7cSeric miao 	[2] = {
5258f58de7cSeric miao 		/* DRCMR for RX */
5268f58de7cSeric miao 		.start	= 13,
5278f58de7cSeric miao 		.end	= 13,
5288f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5298f58de7cSeric miao 	},
5308f58de7cSeric miao 	[3] = {
5318f58de7cSeric miao 		/* DRCMR for TX */
5328f58de7cSeric miao 		.start	= 14,
5338f58de7cSeric miao 		.end	= 14,
5348f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5358f58de7cSeric miao 	},
5368f58de7cSeric miao };
5378f58de7cSeric miao 
5388f58de7cSeric miao struct platform_device pxa25x_device_ssp = {
5398f58de7cSeric miao 	.name		= "pxa25x-ssp",
5408f58de7cSeric miao 	.id		= 0,
5418f58de7cSeric miao 	.dev		= {
5428f58de7cSeric miao 		.dma_mask = &pxa25x_ssp_dma_mask,
5438f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
5448f58de7cSeric miao 	},
5458f58de7cSeric miao 	.resource	= pxa25x_resource_ssp,
5468f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_ssp),
5478f58de7cSeric miao };
5488f58de7cSeric miao 
5498f58de7cSeric miao static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
5508f58de7cSeric miao 
5518f58de7cSeric miao static struct resource pxa25x_resource_nssp[] = {
5528f58de7cSeric miao 	[0] = {
5538f58de7cSeric miao 		.start	= 0x41400000,
5548f58de7cSeric miao 		.end	= 0x4140002f,
5558f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5568f58de7cSeric miao 	},
5578f58de7cSeric miao 	[1] = {
5588f58de7cSeric miao 		.start	= IRQ_NSSP,
5598f58de7cSeric miao 		.end	= IRQ_NSSP,
5608f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5618f58de7cSeric miao 	},
5628f58de7cSeric miao 	[2] = {
5638f58de7cSeric miao 		/* DRCMR for RX */
5648f58de7cSeric miao 		.start	= 15,
5658f58de7cSeric miao 		.end	= 15,
5668f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5678f58de7cSeric miao 	},
5688f58de7cSeric miao 	[3] = {
5698f58de7cSeric miao 		/* DRCMR for TX */
5708f58de7cSeric miao 		.start	= 16,
5718f58de7cSeric miao 		.end	= 16,
5728f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5738f58de7cSeric miao 	},
5748f58de7cSeric miao };
5758f58de7cSeric miao 
5768f58de7cSeric miao struct platform_device pxa25x_device_nssp = {
5778f58de7cSeric miao 	.name		= "pxa25x-nssp",
5788f58de7cSeric miao 	.id		= 1,
5798f58de7cSeric miao 	.dev		= {
5808f58de7cSeric miao 		.dma_mask = &pxa25x_nssp_dma_mask,
5818f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
5828f58de7cSeric miao 	},
5838f58de7cSeric miao 	.resource	= pxa25x_resource_nssp,
5848f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_nssp),
5858f58de7cSeric miao };
5868f58de7cSeric miao 
5878f58de7cSeric miao static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
5888f58de7cSeric miao 
5898f58de7cSeric miao static struct resource pxa25x_resource_assp[] = {
5908f58de7cSeric miao 	[0] = {
5918f58de7cSeric miao 		.start	= 0x41500000,
5928f58de7cSeric miao 		.end	= 0x4150002f,
5938f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5948f58de7cSeric miao 	},
5958f58de7cSeric miao 	[1] = {
5968f58de7cSeric miao 		.start	= IRQ_ASSP,
5978f58de7cSeric miao 		.end	= IRQ_ASSP,
5988f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5998f58de7cSeric miao 	},
6008f58de7cSeric miao 	[2] = {
6018f58de7cSeric miao 		/* DRCMR for RX */
6028f58de7cSeric miao 		.start	= 23,
6038f58de7cSeric miao 		.end	= 23,
6048f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6058f58de7cSeric miao 	},
6068f58de7cSeric miao 	[3] = {
6078f58de7cSeric miao 		/* DRCMR for TX */
6088f58de7cSeric miao 		.start	= 24,
6098f58de7cSeric miao 		.end	= 24,
6108f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6118f58de7cSeric miao 	},
6128f58de7cSeric miao };
6138f58de7cSeric miao 
6148f58de7cSeric miao struct platform_device pxa25x_device_assp = {
6158f58de7cSeric miao 	/* ASSP is basically equivalent to NSSP */
6168f58de7cSeric miao 	.name		= "pxa25x-nssp",
6178f58de7cSeric miao 	.id		= 2,
6188f58de7cSeric miao 	.dev		= {
6198f58de7cSeric miao 		.dma_mask = &pxa25x_assp_dma_mask,
6208f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
6218f58de7cSeric miao 	},
6228f58de7cSeric miao 	.resource	= pxa25x_resource_assp,
6238f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_assp),
6248f58de7cSeric miao };
6258f58de7cSeric miao #endif /* CONFIG_PXA25x */
6268f58de7cSeric miao 
6278f58de7cSeric miao #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
628a4553358SHaojian Zhuang static struct resource pxa27x_resource_camera[] = {
62937320980Seric miao 	[0] = {
630a4553358SHaojian Zhuang 		.start	= 0x50000000,
631a4553358SHaojian Zhuang 		.end	= 0x50000fff,
63237320980Seric miao 		.flags	= IORESOURCE_MEM,
63337320980Seric miao 	},
63437320980Seric miao 	[1] = {
635a4553358SHaojian Zhuang 		.start	= IRQ_CAMERA,
636a4553358SHaojian Zhuang 		.end	= IRQ_CAMERA,
63737320980Seric miao 		.flags	= IORESOURCE_IRQ,
63837320980Seric miao 	},
63937320980Seric miao };
64037320980Seric miao 
641a4553358SHaojian Zhuang static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
642a4553358SHaojian Zhuang 
643a4553358SHaojian Zhuang static struct platform_device pxa27x_device_camera = {
644a4553358SHaojian Zhuang 	.name		= "pxa27x-camera",
645a4553358SHaojian Zhuang 	.id		= 0, /* This is used to put cameras on this interface */
646a4553358SHaojian Zhuang 	.dev		= {
647a4553358SHaojian Zhuang 		.dma_mask      		= &pxa27x_dma_mask_camera,
648a4553358SHaojian Zhuang 		.coherent_dma_mask	= 0xffffffff,
649a4553358SHaojian Zhuang 	},
650a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa27x_resource_camera),
651a4553358SHaojian Zhuang 	.resource	= pxa27x_resource_camera,
65237320980Seric miao };
65337320980Seric miao 
654a4553358SHaojian Zhuang void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
65537320980Seric miao {
656a4553358SHaojian Zhuang 	pxa_register_device(&pxa27x_device_camera, info);
65737320980Seric miao }
65837320980Seric miao 
659ec68e45bSeric miao static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
660ec68e45bSeric miao 
661ec68e45bSeric miao static struct resource pxa27x_resource_ohci[] = {
662ec68e45bSeric miao 	[0] = {
663ec68e45bSeric miao 		.start  = 0x4C000000,
664ec68e45bSeric miao 		.end    = 0x4C00ff6f,
665ec68e45bSeric miao 		.flags  = IORESOURCE_MEM,
666ec68e45bSeric miao 	},
667ec68e45bSeric miao 	[1] = {
668ec68e45bSeric miao 		.start  = IRQ_USBH1,
669ec68e45bSeric miao 		.end    = IRQ_USBH1,
670ec68e45bSeric miao 		.flags  = IORESOURCE_IRQ,
671ec68e45bSeric miao 	},
672ec68e45bSeric miao };
673ec68e45bSeric miao 
674ec68e45bSeric miao struct platform_device pxa27x_device_ohci = {
675ec68e45bSeric miao 	.name		= "pxa27x-ohci",
676ec68e45bSeric miao 	.id		= -1,
677ec68e45bSeric miao 	.dev		= {
678ec68e45bSeric miao 		.dma_mask = &pxa27x_ohci_dma_mask,
679ec68e45bSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
680ec68e45bSeric miao 	},
681ec68e45bSeric miao 	.num_resources  = ARRAY_SIZE(pxa27x_resource_ohci),
682ec68e45bSeric miao 	.resource       = pxa27x_resource_ohci,
683ec68e45bSeric miao };
684ec68e45bSeric miao 
685ec68e45bSeric miao void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
686ec68e45bSeric miao {
687ec68e45bSeric miao 	pxa_register_device(&pxa27x_device_ohci, info);
688ec68e45bSeric miao }
689a4553358SHaojian Zhuang #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
690a4553358SHaojian Zhuang 
691a4553358SHaojian Zhuang #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
692a4553358SHaojian Zhuang static struct resource pxa27x_resource_keypad[] = {
693a4553358SHaojian Zhuang 	[0] = {
694a4553358SHaojian Zhuang 		.start	= 0x41500000,
695a4553358SHaojian Zhuang 		.end	= 0x4150004c,
696a4553358SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
697a4553358SHaojian Zhuang 	},
698a4553358SHaojian Zhuang 	[1] = {
699a4553358SHaojian Zhuang 		.start	= IRQ_KEYPAD,
700a4553358SHaojian Zhuang 		.end	= IRQ_KEYPAD,
701a4553358SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
702a4553358SHaojian Zhuang 	},
703a4553358SHaojian Zhuang };
704a4553358SHaojian Zhuang 
705a4553358SHaojian Zhuang struct platform_device pxa27x_device_keypad = {
706a4553358SHaojian Zhuang 	.name		= "pxa27x-keypad",
707a4553358SHaojian Zhuang 	.id		= -1,
708a4553358SHaojian Zhuang 	.resource	= pxa27x_resource_keypad,
709a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa27x_resource_keypad),
710a4553358SHaojian Zhuang };
711a4553358SHaojian Zhuang 
712a4553358SHaojian Zhuang void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
713a4553358SHaojian Zhuang {
714a4553358SHaojian Zhuang 	pxa_register_device(&pxa27x_device_keypad, info);
715a4553358SHaojian Zhuang }
716ec68e45bSeric miao 
7178f58de7cSeric miao static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
7188f58de7cSeric miao 
7198f58de7cSeric miao static struct resource pxa27x_resource_ssp1[] = {
7208f58de7cSeric miao 	[0] = {
7218f58de7cSeric miao 		.start	= 0x41000000,
7228f58de7cSeric miao 		.end	= 0x4100003f,
7238f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
7248f58de7cSeric miao 	},
7258f58de7cSeric miao 	[1] = {
7268f58de7cSeric miao 		.start	= IRQ_SSP,
7278f58de7cSeric miao 		.end	= IRQ_SSP,
7288f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
7298f58de7cSeric miao 	},
7308f58de7cSeric miao 	[2] = {
7318f58de7cSeric miao 		/* DRCMR for RX */
7328f58de7cSeric miao 		.start	= 13,
7338f58de7cSeric miao 		.end	= 13,
7348f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7358f58de7cSeric miao 	},
7368f58de7cSeric miao 	[3] = {
7378f58de7cSeric miao 		/* DRCMR for TX */
7388f58de7cSeric miao 		.start	= 14,
7398f58de7cSeric miao 		.end	= 14,
7408f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7418f58de7cSeric miao 	},
7428f58de7cSeric miao };
7438f58de7cSeric miao 
7448f58de7cSeric miao struct platform_device pxa27x_device_ssp1 = {
7458f58de7cSeric miao 	.name		= "pxa27x-ssp",
7468f58de7cSeric miao 	.id		= 0,
7478f58de7cSeric miao 	.dev		= {
7488f58de7cSeric miao 		.dma_mask = &pxa27x_ssp1_dma_mask,
7498f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
7508f58de7cSeric miao 	},
7518f58de7cSeric miao 	.resource	= pxa27x_resource_ssp1,
7528f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
7538f58de7cSeric miao };
7548f58de7cSeric miao 
7558f58de7cSeric miao static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
7568f58de7cSeric miao 
7578f58de7cSeric miao static struct resource pxa27x_resource_ssp2[] = {
7588f58de7cSeric miao 	[0] = {
7598f58de7cSeric miao 		.start	= 0x41700000,
7608f58de7cSeric miao 		.end	= 0x4170003f,
7618f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
7628f58de7cSeric miao 	},
7638f58de7cSeric miao 	[1] = {
7648f58de7cSeric miao 		.start	= IRQ_SSP2,
7658f58de7cSeric miao 		.end	= IRQ_SSP2,
7668f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
7678f58de7cSeric miao 	},
7688f58de7cSeric miao 	[2] = {
7698f58de7cSeric miao 		/* DRCMR for RX */
7708f58de7cSeric miao 		.start	= 15,
7718f58de7cSeric miao 		.end	= 15,
7728f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7738f58de7cSeric miao 	},
7748f58de7cSeric miao 	[3] = {
7758f58de7cSeric miao 		/* DRCMR for TX */
7768f58de7cSeric miao 		.start	= 16,
7778f58de7cSeric miao 		.end	= 16,
7788f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7798f58de7cSeric miao 	},
7808f58de7cSeric miao };
7818f58de7cSeric miao 
7828f58de7cSeric miao struct platform_device pxa27x_device_ssp2 = {
7838f58de7cSeric miao 	.name		= "pxa27x-ssp",
7848f58de7cSeric miao 	.id		= 1,
7858f58de7cSeric miao 	.dev		= {
7868f58de7cSeric miao 		.dma_mask = &pxa27x_ssp2_dma_mask,
7878f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
7888f58de7cSeric miao 	},
7898f58de7cSeric miao 	.resource	= pxa27x_resource_ssp2,
7908f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
7918f58de7cSeric miao };
7928f58de7cSeric miao 
7938f58de7cSeric miao static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
7948f58de7cSeric miao 
7958f58de7cSeric miao static struct resource pxa27x_resource_ssp3[] = {
7968f58de7cSeric miao 	[0] = {
7978f58de7cSeric miao 		.start	= 0x41900000,
7988f58de7cSeric miao 		.end	= 0x4190003f,
7998f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
8008f58de7cSeric miao 	},
8018f58de7cSeric miao 	[1] = {
8028f58de7cSeric miao 		.start	= IRQ_SSP3,
8038f58de7cSeric miao 		.end	= IRQ_SSP3,
8048f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
8058f58de7cSeric miao 	},
8068f58de7cSeric miao 	[2] = {
8078f58de7cSeric miao 		/* DRCMR for RX */
8088f58de7cSeric miao 		.start	= 66,
8098f58de7cSeric miao 		.end	= 66,
8108f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
8118f58de7cSeric miao 	},
8128f58de7cSeric miao 	[3] = {
8138f58de7cSeric miao 		/* DRCMR for TX */
8148f58de7cSeric miao 		.start	= 67,
8158f58de7cSeric miao 		.end	= 67,
8168f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
8178f58de7cSeric miao 	},
8188f58de7cSeric miao };
8198f58de7cSeric miao 
8208f58de7cSeric miao struct platform_device pxa27x_device_ssp3 = {
8218f58de7cSeric miao 	.name		= "pxa27x-ssp",
8228f58de7cSeric miao 	.id		= 2,
8238f58de7cSeric miao 	.dev		= {
8248f58de7cSeric miao 		.dma_mask = &pxa27x_ssp3_dma_mask,
8258f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
8268f58de7cSeric miao 	},
8278f58de7cSeric miao 	.resource	= pxa27x_resource_ssp3,
8288f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
8298f58de7cSeric miao };
8303f3acefbSGuennadi Liakhovetski 
83175540c1aSeric miao static struct resource pxa27x_resource_pwm0[] = {
83275540c1aSeric miao 	[0] = {
83375540c1aSeric miao 		.start	= 0x40b00000,
83475540c1aSeric miao 		.end	= 0x40b0001f,
83575540c1aSeric miao 		.flags	= IORESOURCE_MEM,
83675540c1aSeric miao 	},
83775540c1aSeric miao };
83875540c1aSeric miao 
83975540c1aSeric miao struct platform_device pxa27x_device_pwm0 = {
84075540c1aSeric miao 	.name		= "pxa27x-pwm",
84175540c1aSeric miao 	.id		= 0,
84275540c1aSeric miao 	.resource	= pxa27x_resource_pwm0,
84375540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm0),
84475540c1aSeric miao };
84575540c1aSeric miao 
84675540c1aSeric miao static struct resource pxa27x_resource_pwm1[] = {
84775540c1aSeric miao 	[0] = {
84875540c1aSeric miao 		.start	= 0x40c00000,
84975540c1aSeric miao 		.end	= 0x40c0001f,
85075540c1aSeric miao 		.flags	= IORESOURCE_MEM,
85175540c1aSeric miao 	},
85275540c1aSeric miao };
85375540c1aSeric miao 
85475540c1aSeric miao struct platform_device pxa27x_device_pwm1 = {
85575540c1aSeric miao 	.name		= "pxa27x-pwm",
85675540c1aSeric miao 	.id		= 1,
85775540c1aSeric miao 	.resource	= pxa27x_resource_pwm1,
85875540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm1),
85975540c1aSeric miao };
860a4553358SHaojian Zhuang #endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/
8618f58de7cSeric miao 
8628f58de7cSeric miao #ifdef CONFIG_PXA3xx
8638d33b055SBridge Wu static struct resource pxa3xx_resources_mci2[] = {
8648d33b055SBridge Wu 	[0] = {
8658d33b055SBridge Wu 		.start	= 0x42000000,
8668d33b055SBridge Wu 		.end	= 0x42000fff,
8678d33b055SBridge Wu 		.flags	= IORESOURCE_MEM,
8688d33b055SBridge Wu 	},
8698d33b055SBridge Wu 	[1] = {
8708d33b055SBridge Wu 		.start	= IRQ_MMC2,
8718d33b055SBridge Wu 		.end	= IRQ_MMC2,
8728d33b055SBridge Wu 		.flags	= IORESOURCE_IRQ,
8738d33b055SBridge Wu 	},
8748d33b055SBridge Wu 	[2] = {
8758d33b055SBridge Wu 		.start	= 93,
8768d33b055SBridge Wu 		.end	= 93,
8778d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
8788d33b055SBridge Wu 	},
8798d33b055SBridge Wu 	[3] = {
8808d33b055SBridge Wu 		.start	= 94,
8818d33b055SBridge Wu 		.end	= 94,
8828d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
8838d33b055SBridge Wu 	},
8848d33b055SBridge Wu };
8858d33b055SBridge Wu 
8868d33b055SBridge Wu struct platform_device pxa3xx_device_mci2 = {
8878d33b055SBridge Wu 	.name		= "pxa2xx-mci",
8888d33b055SBridge Wu 	.id		= 1,
8898d33b055SBridge Wu 	.dev		= {
8908d33b055SBridge Wu 		.dma_mask = &pxamci_dmamask,
8918d33b055SBridge Wu 		.coherent_dma_mask =	0xffffffff,
8928d33b055SBridge Wu 	},
8938d33b055SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci2),
8948d33b055SBridge Wu 	.resource	= pxa3xx_resources_mci2,
8958d33b055SBridge Wu };
8968d33b055SBridge Wu 
8978d33b055SBridge Wu void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
8988d33b055SBridge Wu {
8998d33b055SBridge Wu 	pxa_register_device(&pxa3xx_device_mci2, info);
9008d33b055SBridge Wu }
9018d33b055SBridge Wu 
9025a1f21b1SBridge Wu static struct resource pxa3xx_resources_mci3[] = {
9035a1f21b1SBridge Wu 	[0] = {
9045a1f21b1SBridge Wu 		.start	= 0x42500000,
9055a1f21b1SBridge Wu 		.end	= 0x42500fff,
9065a1f21b1SBridge Wu 		.flags	= IORESOURCE_MEM,
9075a1f21b1SBridge Wu 	},
9085a1f21b1SBridge Wu 	[1] = {
9095a1f21b1SBridge Wu 		.start	= IRQ_MMC3,
9105a1f21b1SBridge Wu 		.end	= IRQ_MMC3,
9115a1f21b1SBridge Wu 		.flags	= IORESOURCE_IRQ,
9125a1f21b1SBridge Wu 	},
9135a1f21b1SBridge Wu 	[2] = {
9145a1f21b1SBridge Wu 		.start	= 100,
9155a1f21b1SBridge Wu 		.end	= 100,
9165a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
9175a1f21b1SBridge Wu 	},
9185a1f21b1SBridge Wu 	[3] = {
9195a1f21b1SBridge Wu 		.start	= 101,
9205a1f21b1SBridge Wu 		.end	= 101,
9215a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
9225a1f21b1SBridge Wu 	},
9235a1f21b1SBridge Wu };
9245a1f21b1SBridge Wu 
9255a1f21b1SBridge Wu struct platform_device pxa3xx_device_mci3 = {
9265a1f21b1SBridge Wu 	.name		= "pxa2xx-mci",
9275a1f21b1SBridge Wu 	.id		= 2,
9285a1f21b1SBridge Wu 	.dev		= {
9295a1f21b1SBridge Wu 		.dma_mask = &pxamci_dmamask,
9305a1f21b1SBridge Wu 		.coherent_dma_mask = 0xffffffff,
9315a1f21b1SBridge Wu 	},
9325a1f21b1SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci3),
9335a1f21b1SBridge Wu 	.resource	= pxa3xx_resources_mci3,
9345a1f21b1SBridge Wu };
9355a1f21b1SBridge Wu 
9365a1f21b1SBridge Wu void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
9375a1f21b1SBridge Wu {
9385a1f21b1SBridge Wu 	pxa_register_device(&pxa3xx_device_mci3, info);
9395a1f21b1SBridge Wu }
9405a1f21b1SBridge Wu 
941a4553358SHaojian Zhuang static struct resource pxa3xx_resources_gcu[] = {
942a4553358SHaojian Zhuang 	{
943a4553358SHaojian Zhuang 		.start	= 0x54000000,
944a4553358SHaojian Zhuang 		.end	= 0x54000fff,
945a4553358SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
946a4553358SHaojian Zhuang 	},
947a4553358SHaojian Zhuang 	{
948a4553358SHaojian Zhuang 		.start	= IRQ_GCU,
949a4553358SHaojian Zhuang 		.end	= IRQ_GCU,
950a4553358SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
951a4553358SHaojian Zhuang 	},
952a4553358SHaojian Zhuang };
953a4553358SHaojian Zhuang 
954a4553358SHaojian Zhuang static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
955a4553358SHaojian Zhuang 
956a4553358SHaojian Zhuang struct platform_device pxa3xx_device_gcu = {
957a4553358SHaojian Zhuang 	.name		= "pxa3xx-gcu",
958a4553358SHaojian Zhuang 	.id		= -1,
959a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_gcu),
960a4553358SHaojian Zhuang 	.resource	= pxa3xx_resources_gcu,
961a4553358SHaojian Zhuang 	.dev		= {
962a4553358SHaojian Zhuang 		.dma_mask = &pxa3xx_gcu_dmamask,
963a4553358SHaojian Zhuang 		.coherent_dma_mask = 0xffffffff,
964a4553358SHaojian Zhuang 	},
965a4553358SHaojian Zhuang };
966a4553358SHaojian Zhuang 
967a4553358SHaojian Zhuang #endif /* CONFIG_PXA3xx */
968a4553358SHaojian Zhuang 
969a4553358SHaojian Zhuang #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
970a4553358SHaojian Zhuang static struct resource pxa3xx_resources_i2c_power[] = {
971a4553358SHaojian Zhuang 	{
972a4553358SHaojian Zhuang 		.start  = 0x40f500c0,
973a4553358SHaojian Zhuang 		.end    = 0x40f500d3,
974a4553358SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
975a4553358SHaojian Zhuang 	}, {
976a4553358SHaojian Zhuang 		.start	= IRQ_PWRI2C,
977a4553358SHaojian Zhuang 		.end	= IRQ_PWRI2C,
978a4553358SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
979a4553358SHaojian Zhuang 	},
980a4553358SHaojian Zhuang };
981a4553358SHaojian Zhuang 
982a4553358SHaojian Zhuang struct platform_device pxa3xx_device_i2c_power = {
983a4553358SHaojian Zhuang 	.name		= "pxa3xx-pwri2c",
984a4553358SHaojian Zhuang 	.id		= 1,
985a4553358SHaojian Zhuang 	.resource	= pxa3xx_resources_i2c_power,
986a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_i2c_power),
987a4553358SHaojian Zhuang };
988a4553358SHaojian Zhuang 
9899ae819a8SEric Miao static struct resource pxa3xx_resources_nand[] = {
9909ae819a8SEric Miao 	[0] = {
9919ae819a8SEric Miao 		.start	= 0x43100000,
9929ae819a8SEric Miao 		.end	= 0x43100053,
9939ae819a8SEric Miao 		.flags	= IORESOURCE_MEM,
9949ae819a8SEric Miao 	},
9959ae819a8SEric Miao 	[1] = {
9969ae819a8SEric Miao 		.start	= IRQ_NAND,
9979ae819a8SEric Miao 		.end	= IRQ_NAND,
9989ae819a8SEric Miao 		.flags	= IORESOURCE_IRQ,
9999ae819a8SEric Miao 	},
10009ae819a8SEric Miao 	[2] = {
10019ae819a8SEric Miao 		/* DRCMR for Data DMA */
10029ae819a8SEric Miao 		.start	= 97,
10039ae819a8SEric Miao 		.end	= 97,
10049ae819a8SEric Miao 		.flags	= IORESOURCE_DMA,
10059ae819a8SEric Miao 	},
10069ae819a8SEric Miao 	[3] = {
10079ae819a8SEric Miao 		/* DRCMR for Command DMA */
10089ae819a8SEric Miao 		.start	= 99,
10099ae819a8SEric Miao 		.end	= 99,
10109ae819a8SEric Miao 		.flags	= IORESOURCE_DMA,
10119ae819a8SEric Miao 	},
10129ae819a8SEric Miao };
10139ae819a8SEric Miao 
10149ae819a8SEric Miao static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
10159ae819a8SEric Miao 
10169ae819a8SEric Miao struct platform_device pxa3xx_device_nand = {
10179ae819a8SEric Miao 	.name		= "pxa3xx-nand",
10189ae819a8SEric Miao 	.id		= -1,
10199ae819a8SEric Miao 	.dev		= {
10209ae819a8SEric Miao 		.dma_mask = &pxa3xx_nand_dma_mask,
10219ae819a8SEric Miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
10229ae819a8SEric Miao 	},
10239ae819a8SEric Miao 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_nand),
10249ae819a8SEric Miao 	.resource	= pxa3xx_resources_nand,
10259ae819a8SEric Miao };
10269ae819a8SEric Miao 
10279ae819a8SEric Miao void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
10289ae819a8SEric Miao {
10299ae819a8SEric Miao 	pxa_register_device(&pxa3xx_device_nand, info);
10309ae819a8SEric Miao }
10311ff2c33eSDaniel Mack 
1032a4553358SHaojian Zhuang static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
1033a4553358SHaojian Zhuang 
1034a4553358SHaojian Zhuang static struct resource pxa3xx_resource_ssp4[] = {
1035a4553358SHaojian Zhuang 	[0] = {
1036a4553358SHaojian Zhuang 		.start	= 0x41a00000,
1037a4553358SHaojian Zhuang 		.end	= 0x41a0003f,
10381ff2c33eSDaniel Mack 		.flags	= IORESOURCE_MEM,
10391ff2c33eSDaniel Mack 	},
1040a4553358SHaojian Zhuang 	[1] = {
1041a4553358SHaojian Zhuang 		.start	= IRQ_SSP4,
1042a4553358SHaojian Zhuang 		.end	= IRQ_SSP4,
10431ff2c33eSDaniel Mack 		.flags	= IORESOURCE_IRQ,
10441ff2c33eSDaniel Mack 	},
1045a4553358SHaojian Zhuang 	[2] = {
1046a4553358SHaojian Zhuang 		/* DRCMR for RX */
1047a4553358SHaojian Zhuang 		.start	= 2,
1048a4553358SHaojian Zhuang 		.end	= 2,
1049a4553358SHaojian Zhuang 		.flags	= IORESOURCE_DMA,
1050a4553358SHaojian Zhuang 	},
1051a4553358SHaojian Zhuang 	[3] = {
1052a4553358SHaojian Zhuang 		/* DRCMR for TX */
1053a4553358SHaojian Zhuang 		.start	= 3,
1054a4553358SHaojian Zhuang 		.end	= 3,
1055a4553358SHaojian Zhuang 		.flags	= IORESOURCE_DMA,
10561ff2c33eSDaniel Mack 	},
10571ff2c33eSDaniel Mack };
10581ff2c33eSDaniel Mack 
1059a4553358SHaojian Zhuang struct platform_device pxa3xx_device_ssp4 = {
1060a4553358SHaojian Zhuang 	/* PXA3xx SSP is basically equivalent to PXA27x */
1061a4553358SHaojian Zhuang 	.name		= "pxa27x-ssp",
1062a4553358SHaojian Zhuang 	.id		= 3,
1063a4553358SHaojian Zhuang 	.dev		= {
1064a4553358SHaojian Zhuang 		.dma_mask = &pxa3xx_ssp4_dma_mask,
1065a4553358SHaojian Zhuang 		.coherent_dma_mask = DMA_BIT_MASK(32),
1066a4553358SHaojian Zhuang 	},
1067a4553358SHaojian Zhuang 	.resource	= pxa3xx_resource_ssp4,
1068a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa3xx_resource_ssp4),
1069a4553358SHaojian Zhuang };
1070a4553358SHaojian Zhuang #endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
1071e172274cSGuennadi Liakhovetski 
1072157d2644SHaojian Zhuang struct resource pxa_resource_gpio[] = {
1073157d2644SHaojian Zhuang 	{
1074157d2644SHaojian Zhuang 		.start	= 0x40e00000,
1075157d2644SHaojian Zhuang 		.end	= 0x40e0ffff,
1076157d2644SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
1077157d2644SHaojian Zhuang 	}, {
1078157d2644SHaojian Zhuang 		.start	= IRQ_GPIO0,
1079157d2644SHaojian Zhuang 		.end	= IRQ_GPIO0,
1080157d2644SHaojian Zhuang 		.name	= "gpio0",
1081157d2644SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1082157d2644SHaojian Zhuang 	}, {
1083157d2644SHaojian Zhuang 		.start	= IRQ_GPIO1,
1084157d2644SHaojian Zhuang 		.end	= IRQ_GPIO1,
1085157d2644SHaojian Zhuang 		.name	= "gpio1",
1086157d2644SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1087157d2644SHaojian Zhuang 	}, {
1088157d2644SHaojian Zhuang 		.start	= IRQ_GPIO_2_x,
1089157d2644SHaojian Zhuang 		.end	= IRQ_GPIO_2_x,
1090157d2644SHaojian Zhuang 		.name	= "gpio_mux",
1091157d2644SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1092157d2644SHaojian Zhuang 	},
1093157d2644SHaojian Zhuang };
1094157d2644SHaojian Zhuang 
1095157d2644SHaojian Zhuang struct platform_device pxa_device_gpio = {
1096157d2644SHaojian Zhuang 	.name		= "pxa-gpio",
1097157d2644SHaojian Zhuang 	.id		= -1,
1098157d2644SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa_resource_gpio),
1099157d2644SHaojian Zhuang 	.resource	= pxa_resource_gpio,
1100157d2644SHaojian Zhuang };
1101157d2644SHaojian Zhuang 
1102e172274cSGuennadi Liakhovetski /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
1103e172274cSGuennadi Liakhovetski  * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
1104e172274cSGuennadi Liakhovetski void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
1105e172274cSGuennadi Liakhovetski {
1106e172274cSGuennadi Liakhovetski 	struct platform_device *pd;
1107e172274cSGuennadi Liakhovetski 
1108e172274cSGuennadi Liakhovetski 	pd = platform_device_alloc("pxa2xx-spi", id);
1109e172274cSGuennadi Liakhovetski 	if (pd == NULL) {
1110e172274cSGuennadi Liakhovetski 		printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
1111e172274cSGuennadi Liakhovetski 		       id);
1112e172274cSGuennadi Liakhovetski 		return;
1113e172274cSGuennadi Liakhovetski 	}
1114e172274cSGuennadi Liakhovetski 
1115e172274cSGuennadi Liakhovetski 	pd->dev.platform_data = info;
1116e172274cSGuennadi Liakhovetski 	platform_device_add(pd);
1117e172274cSGuennadi Liakhovetski }
1118