xref: /linux/arch/arm/mach-pxa/devices.c (revision cc155c6f2cc705cb082ed676044368424e4b9121)
18f58de7cSeric miao #include <linux/module.h>
28f58de7cSeric miao #include <linux/kernel.h>
38f58de7cSeric miao #include <linux/init.h>
48f58de7cSeric miao #include <linux/platform_device.h>
58f58de7cSeric miao #include <linux/dma-mapping.h>
68f58de7cSeric miao 
7a09e64fbSRussell King #include <mach/udc.h>
8a09e64fbSRussell King #include <mach/pxafb.h>
9a09e64fbSRussell King #include <mach/mmc.h>
10a09e64fbSRussell King #include <mach/irda.h>
11a09e64fbSRussell King #include <mach/ohci.h>
12a09e64fbSRussell King #include <mach/pxa27x_keypad.h>
13a09e64fbSRussell King #include <mach/pxa2xx_spi.h>
14a09e64fbSRussell King #include <mach/camera.h>
15a09e64fbSRussell King #include <mach/audio.h>
1682b95ecbSHaojian Zhuang #include <plat/i2c.h>
1782b95ecbSHaojian Zhuang #include <plat/pxa3xx_nand.h>
188f58de7cSeric miao 
198f58de7cSeric miao #include "devices.h"
20bc3a5959SPhilipp Zabel #include "generic.h"
218f58de7cSeric miao 
228f58de7cSeric miao void __init pxa_register_device(struct platform_device *dev, void *data)
238f58de7cSeric miao {
248f58de7cSeric miao 	int ret;
258f58de7cSeric miao 
268f58de7cSeric miao 	dev->dev.platform_data = data;
278f58de7cSeric miao 
288f58de7cSeric miao 	ret = platform_device_register(dev);
298f58de7cSeric miao 	if (ret)
308f58de7cSeric miao 		dev_err(&dev->dev, "unable to register device: %d\n", ret);
318f58de7cSeric miao }
328f58de7cSeric miao 
338f58de7cSeric miao static struct resource pxamci_resources[] = {
348f58de7cSeric miao 	[0] = {
358f58de7cSeric miao 		.start	= 0x41100000,
368f58de7cSeric miao 		.end	= 0x41100fff,
378f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
388f58de7cSeric miao 	},
398f58de7cSeric miao 	[1] = {
408f58de7cSeric miao 		.start	= IRQ_MMC,
418f58de7cSeric miao 		.end	= IRQ_MMC,
428f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
438f58de7cSeric miao 	},
448f58de7cSeric miao 	[2] = {
458f58de7cSeric miao 		.start	= 21,
468f58de7cSeric miao 		.end	= 21,
478f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
488f58de7cSeric miao 	},
498f58de7cSeric miao 	[3] = {
508f58de7cSeric miao 		.start	= 22,
518f58de7cSeric miao 		.end	= 22,
528f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
538f58de7cSeric miao 	},
548f58de7cSeric miao };
558f58de7cSeric miao 
568f58de7cSeric miao static u64 pxamci_dmamask = 0xffffffffUL;
578f58de7cSeric miao 
588f58de7cSeric miao struct platform_device pxa_device_mci = {
598f58de7cSeric miao 	.name		= "pxa2xx-mci",
60fafc9d3fSBridge Wu 	.id		= 0,
618f58de7cSeric miao 	.dev		= {
628f58de7cSeric miao 		.dma_mask = &pxamci_dmamask,
638f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
648f58de7cSeric miao 	},
658f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxamci_resources),
668f58de7cSeric miao 	.resource	= pxamci_resources,
678f58de7cSeric miao };
688f58de7cSeric miao 
698f58de7cSeric miao void __init pxa_set_mci_info(struct pxamci_platform_data *info)
708f58de7cSeric miao {
718f58de7cSeric miao 	pxa_register_device(&pxa_device_mci, info);
728f58de7cSeric miao }
738f58de7cSeric miao 
748f58de7cSeric miao 
751257629bSPhilipp Zabel static struct pxa2xx_udc_mach_info pxa_udc_info = {
761257629bSPhilipp Zabel 	.gpio_pullup = -1,
771257629bSPhilipp Zabel 	.gpio_vbus   = -1,
781257629bSPhilipp Zabel };
798f58de7cSeric miao 
808f58de7cSeric miao void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
818f58de7cSeric miao {
828f58de7cSeric miao 	memcpy(&pxa_udc_info, info, sizeof *info);
838f58de7cSeric miao }
848f58de7cSeric miao 
858f58de7cSeric miao static struct resource pxa2xx_udc_resources[] = {
868f58de7cSeric miao 	[0] = {
878f58de7cSeric miao 		.start	= 0x40600000,
888f58de7cSeric miao 		.end	= 0x4060ffff,
898f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
908f58de7cSeric miao 	},
918f58de7cSeric miao 	[1] = {
928f58de7cSeric miao 		.start	= IRQ_USB,
938f58de7cSeric miao 		.end	= IRQ_USB,
948f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
958f58de7cSeric miao 	},
968f58de7cSeric miao };
978f58de7cSeric miao 
988f58de7cSeric miao static u64 udc_dma_mask = ~(u32)0;
998f58de7cSeric miao 
1007a857620SPhilipp Zabel struct platform_device pxa25x_device_udc = {
1017a857620SPhilipp Zabel 	.name		= "pxa25x-udc",
1027a857620SPhilipp Zabel 	.id		= -1,
1037a857620SPhilipp Zabel 	.resource	= pxa2xx_udc_resources,
1047a857620SPhilipp Zabel 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
1057a857620SPhilipp Zabel 	.dev		=  {
1067a857620SPhilipp Zabel 		.platform_data	= &pxa_udc_info,
1077a857620SPhilipp Zabel 		.dma_mask	= &udc_dma_mask,
1087a857620SPhilipp Zabel 	}
1097a857620SPhilipp Zabel };
1107a857620SPhilipp Zabel 
1117a857620SPhilipp Zabel struct platform_device pxa27x_device_udc = {
1127a857620SPhilipp Zabel 	.name		= "pxa27x-udc",
1138f58de7cSeric miao 	.id		= -1,
1148f58de7cSeric miao 	.resource	= pxa2xx_udc_resources,
1158f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
1168f58de7cSeric miao 	.dev		=  {
1178f58de7cSeric miao 		.platform_data	= &pxa_udc_info,
1188f58de7cSeric miao 		.dma_mask	= &udc_dma_mask,
1198f58de7cSeric miao 	}
1208f58de7cSeric miao };
1218f58de7cSeric miao 
1228f58de7cSeric miao static struct resource pxafb_resources[] = {
1238f58de7cSeric miao 	[0] = {
1248f58de7cSeric miao 		.start	= 0x44000000,
1258f58de7cSeric miao 		.end	= 0x4400ffff,
1268f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1278f58de7cSeric miao 	},
1288f58de7cSeric miao 	[1] = {
1298f58de7cSeric miao 		.start	= IRQ_LCD,
1308f58de7cSeric miao 		.end	= IRQ_LCD,
1318f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1328f58de7cSeric miao 	},
1338f58de7cSeric miao };
1348f58de7cSeric miao 
1358f58de7cSeric miao static u64 fb_dma_mask = ~(u64)0;
1368f58de7cSeric miao 
1378f58de7cSeric miao struct platform_device pxa_device_fb = {
1388f58de7cSeric miao 	.name		= "pxa2xx-fb",
1398f58de7cSeric miao 	.id		= -1,
1408f58de7cSeric miao 	.dev		= {
1418f58de7cSeric miao 		.dma_mask	= &fb_dma_mask,
1428f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
1438f58de7cSeric miao 	},
1448f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxafb_resources),
1458f58de7cSeric miao 	.resource	= pxafb_resources,
1468f58de7cSeric miao };
1478f58de7cSeric miao 
1488f58de7cSeric miao void __init set_pxa_fb_info(struct pxafb_mach_info *info)
1498f58de7cSeric miao {
1508f58de7cSeric miao 	pxa_register_device(&pxa_device_fb, info);
1518f58de7cSeric miao }
1528f58de7cSeric miao 
1538f58de7cSeric miao void __init set_pxa_fb_parent(struct device *parent_dev)
1548f58de7cSeric miao {
1558f58de7cSeric miao 	pxa_device_fb.dev.parent = parent_dev;
1568f58de7cSeric miao }
1578f58de7cSeric miao 
1588f58de7cSeric miao static struct resource pxa_resource_ffuart[] = {
1598f58de7cSeric miao 	{
16002f65262SEric Miao 		.start	= 0x40100000,
16102f65262SEric Miao 		.end	= 0x40100023,
1628f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1638f58de7cSeric miao 	}, {
1648f58de7cSeric miao 		.start	= IRQ_FFUART,
1658f58de7cSeric miao 		.end	= IRQ_FFUART,
1668f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1678f58de7cSeric miao 	}
1688f58de7cSeric miao };
1698f58de7cSeric miao 
1708f58de7cSeric miao struct platform_device pxa_device_ffuart = {
1718f58de7cSeric miao 	.name		= "pxa2xx-uart",
1728f58de7cSeric miao 	.id		= 0,
1738f58de7cSeric miao 	.resource	= pxa_resource_ffuart,
1748f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_ffuart),
1758f58de7cSeric miao };
1768f58de7cSeric miao 
177*cc155c6fSRussell King void __init pxa_set_ffuart_info(void *info)
178*cc155c6fSRussell King {
179*cc155c6fSRussell King 	pxa_register_device(&pxa_device_ffuart, info);
180*cc155c6fSRussell King }
181*cc155c6fSRussell King 
1828f58de7cSeric miao static struct resource pxa_resource_btuart[] = {
1838f58de7cSeric miao 	{
18402f65262SEric Miao 		.start	= 0x40200000,
18502f65262SEric Miao 		.end	= 0x40200023,
1868f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1878f58de7cSeric miao 	}, {
1888f58de7cSeric miao 		.start	= IRQ_BTUART,
1898f58de7cSeric miao 		.end	= IRQ_BTUART,
1908f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1918f58de7cSeric miao 	}
1928f58de7cSeric miao };
1938f58de7cSeric miao 
1948f58de7cSeric miao struct platform_device pxa_device_btuart = {
1958f58de7cSeric miao 	.name		= "pxa2xx-uart",
1968f58de7cSeric miao 	.id		= 1,
1978f58de7cSeric miao 	.resource	= pxa_resource_btuart,
1988f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_btuart),
1998f58de7cSeric miao };
2008f58de7cSeric miao 
201*cc155c6fSRussell King void __init pxa_set_btuart_info(void *info)
202*cc155c6fSRussell King {
203*cc155c6fSRussell King 	pxa_register_device(&pxa_device_btuart, info);
204*cc155c6fSRussell King }
205*cc155c6fSRussell King 
2068f58de7cSeric miao static struct resource pxa_resource_stuart[] = {
2078f58de7cSeric miao 	{
20802f65262SEric Miao 		.start	= 0x40700000,
20902f65262SEric Miao 		.end	= 0x40700023,
2108f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2118f58de7cSeric miao 	}, {
2128f58de7cSeric miao 		.start	= IRQ_STUART,
2138f58de7cSeric miao 		.end	= IRQ_STUART,
2148f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2158f58de7cSeric miao 	}
2168f58de7cSeric miao };
2178f58de7cSeric miao 
2188f58de7cSeric miao struct platform_device pxa_device_stuart = {
2198f58de7cSeric miao 	.name		= "pxa2xx-uart",
2208f58de7cSeric miao 	.id		= 2,
2218f58de7cSeric miao 	.resource	= pxa_resource_stuart,
2228f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_stuart),
2238f58de7cSeric miao };
2248f58de7cSeric miao 
225*cc155c6fSRussell King void __init pxa_set_stuart_info(void *info)
226*cc155c6fSRussell King {
227*cc155c6fSRussell King 	pxa_register_device(&pxa_device_stuart, info);
228*cc155c6fSRussell King }
229*cc155c6fSRussell King 
2308f58de7cSeric miao static struct resource pxa_resource_hwuart[] = {
2318f58de7cSeric miao 	{
23202f65262SEric Miao 		.start	= 0x41600000,
23302f65262SEric Miao 		.end	= 0x4160002F,
2348f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2358f58de7cSeric miao 	}, {
2368f58de7cSeric miao 		.start	= IRQ_HWUART,
2378f58de7cSeric miao 		.end	= IRQ_HWUART,
2388f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2398f58de7cSeric miao 	}
2408f58de7cSeric miao };
2418f58de7cSeric miao 
2428f58de7cSeric miao struct platform_device pxa_device_hwuart = {
2438f58de7cSeric miao 	.name		= "pxa2xx-uart",
2448f58de7cSeric miao 	.id		= 3,
2458f58de7cSeric miao 	.resource	= pxa_resource_hwuart,
2468f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
2478f58de7cSeric miao };
2488f58de7cSeric miao 
249*cc155c6fSRussell King void __init pxa_set_hwuart_info(void *info)
250*cc155c6fSRussell King {
251*cc155c6fSRussell King 	if (cpu_is_pxa255())
252*cc155c6fSRussell King 		pxa_register_device(&pxa_device_hwuart, info);
253*cc155c6fSRussell King 	else
254*cc155c6fSRussell King 		pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
255*cc155c6fSRussell King }
256*cc155c6fSRussell King 
2578f58de7cSeric miao static struct resource pxai2c_resources[] = {
2588f58de7cSeric miao 	{
2598f58de7cSeric miao 		.start	= 0x40301680,
2608f58de7cSeric miao 		.end	= 0x403016a3,
2618f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2628f58de7cSeric miao 	}, {
2638f58de7cSeric miao 		.start	= IRQ_I2C,
2648f58de7cSeric miao 		.end	= IRQ_I2C,
2658f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2668f58de7cSeric miao 	},
2678f58de7cSeric miao };
2688f58de7cSeric miao 
2698f58de7cSeric miao struct platform_device pxa_device_i2c = {
2708f58de7cSeric miao 	.name		= "pxa2xx-i2c",
2718f58de7cSeric miao 	.id		= 0,
2728f58de7cSeric miao 	.resource	= pxai2c_resources,
2738f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2c_resources),
2748f58de7cSeric miao };
2758f58de7cSeric miao 
2768f58de7cSeric miao void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
2778f58de7cSeric miao {
2788f58de7cSeric miao 	pxa_register_device(&pxa_device_i2c, info);
2798f58de7cSeric miao }
2808f58de7cSeric miao 
28199464293SEric Miao #ifdef CONFIG_PXA27x
28299464293SEric Miao static struct resource pxa27x_resources_i2c_power[] = {
28399464293SEric Miao 	{
28499464293SEric Miao 		.start	= 0x40f00180,
28599464293SEric Miao 		.end	= 0x40f001a3,
28699464293SEric Miao 		.flags	= IORESOURCE_MEM,
28799464293SEric Miao 	}, {
28899464293SEric Miao 		.start	= IRQ_PWRI2C,
28999464293SEric Miao 		.end	= IRQ_PWRI2C,
29099464293SEric Miao 		.flags	= IORESOURCE_IRQ,
29199464293SEric Miao 	},
29299464293SEric Miao };
29399464293SEric Miao 
29499464293SEric Miao struct platform_device pxa27x_device_i2c_power = {
29599464293SEric Miao 	.name		= "pxa2xx-i2c",
29699464293SEric Miao 	.id		= 1,
29799464293SEric Miao 	.resource	= pxa27x_resources_i2c_power,
29899464293SEric Miao 	.num_resources	= ARRAY_SIZE(pxa27x_resources_i2c_power),
29999464293SEric Miao };
30099464293SEric Miao #endif
30199464293SEric Miao 
30299464293SEric Miao #ifdef CONFIG_PXA3xx
30399464293SEric Miao static struct resource pxa3xx_resources_i2c_power[] = {
30499464293SEric Miao 	{
30599464293SEric Miao 		.start  = 0x40f500c0,
30699464293SEric Miao 		.end    = 0x40f500d3,
30799464293SEric Miao 		.flags	= IORESOURCE_MEM,
30899464293SEric Miao 	}, {
30999464293SEric Miao 		.start	= IRQ_PWRI2C,
31099464293SEric Miao 		.end	= IRQ_PWRI2C,
31199464293SEric Miao 		.flags	= IORESOURCE_IRQ,
31299464293SEric Miao 	},
31399464293SEric Miao };
31499464293SEric Miao 
31599464293SEric Miao struct platform_device pxa3xx_device_i2c_power = {
316f23d4911SEric Miao 	.name		= "pxa3xx-pwri2c",
31799464293SEric Miao 	.id		= 1,
31899464293SEric Miao 	.resource	= pxa3xx_resources_i2c_power,
31999464293SEric Miao 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_i2c_power),
32099464293SEric Miao };
32199464293SEric Miao #endif
32299464293SEric Miao 
3238f58de7cSeric miao static struct resource pxai2s_resources[] = {
3248f58de7cSeric miao 	{
3258f58de7cSeric miao 		.start	= 0x40400000,
3268f58de7cSeric miao 		.end	= 0x40400083,
3278f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3288f58de7cSeric miao 	}, {
3298f58de7cSeric miao 		.start	= IRQ_I2S,
3308f58de7cSeric miao 		.end	= IRQ_I2S,
3318f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3328f58de7cSeric miao 	},
3338f58de7cSeric miao };
3348f58de7cSeric miao 
3358f58de7cSeric miao struct platform_device pxa_device_i2s = {
3368f58de7cSeric miao 	.name		= "pxa2xx-i2s",
3378f58de7cSeric miao 	.id		= -1,
3388f58de7cSeric miao 	.resource	= pxai2s_resources,
3398f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2s_resources),
3408f58de7cSeric miao };
3418f58de7cSeric miao 
3428f58de7cSeric miao static u64 pxaficp_dmamask = ~(u32)0;
3438f58de7cSeric miao 
3448f58de7cSeric miao struct platform_device pxa_device_ficp = {
3458f58de7cSeric miao 	.name		= "pxa2xx-ir",
3468f58de7cSeric miao 	.id		= -1,
3478f58de7cSeric miao 	.dev		= {
3488f58de7cSeric miao 		.dma_mask = &pxaficp_dmamask,
3498f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
3508f58de7cSeric miao 	},
3518f58de7cSeric miao };
3528f58de7cSeric miao 
3538f58de7cSeric miao void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
3548f58de7cSeric miao {
3558f58de7cSeric miao 	pxa_register_device(&pxa_device_ficp, info);
3568f58de7cSeric miao }
3578f58de7cSeric miao 
35872493146SRobert Jarzmik static struct resource pxa_rtc_resources[] = {
35972493146SRobert Jarzmik 	[0] = {
36072493146SRobert Jarzmik 		.start  = 0x40900000,
36172493146SRobert Jarzmik 		.end	= 0x40900000 + 0x3b,
36272493146SRobert Jarzmik 		.flags  = IORESOURCE_MEM,
36372493146SRobert Jarzmik 	},
36472493146SRobert Jarzmik 	[1] = {
36572493146SRobert Jarzmik 		.start  = IRQ_RTC1Hz,
36672493146SRobert Jarzmik 		.end    = IRQ_RTC1Hz,
36772493146SRobert Jarzmik 		.flags  = IORESOURCE_IRQ,
36872493146SRobert Jarzmik 	},
36972493146SRobert Jarzmik 	[2] = {
37072493146SRobert Jarzmik 		.start  = IRQ_RTCAlrm,
37172493146SRobert Jarzmik 		.end    = IRQ_RTCAlrm,
37272493146SRobert Jarzmik 		.flags  = IORESOURCE_IRQ,
37372493146SRobert Jarzmik 	},
37472493146SRobert Jarzmik };
37572493146SRobert Jarzmik 
37672493146SRobert Jarzmik struct platform_device sa1100_device_rtc = {
3778f58de7cSeric miao 	.name		= "sa1100-rtc",
3788f58de7cSeric miao 	.id		= -1,
3798f58de7cSeric miao };
3808f58de7cSeric miao 
38172493146SRobert Jarzmik struct platform_device pxa_device_rtc = {
38272493146SRobert Jarzmik 	.name		= "pxa-rtc",
38372493146SRobert Jarzmik 	.id		= -1,
38472493146SRobert Jarzmik 	.num_resources  = ARRAY_SIZE(pxa_rtc_resources),
38572493146SRobert Jarzmik 	.resource       = pxa_rtc_resources,
38672493146SRobert Jarzmik };
38772493146SRobert Jarzmik 
3889f19d638SMark Brown static struct resource pxa_ac97_resources[] = {
3899f19d638SMark Brown 	[0] = {
3909f19d638SMark Brown 		.start  = 0x40500000,
3919f19d638SMark Brown 		.end	= 0x40500000 + 0xfff,
3929f19d638SMark Brown 		.flags  = IORESOURCE_MEM,
3939f19d638SMark Brown 	},
3949f19d638SMark Brown 	[1] = {
3959f19d638SMark Brown 		.start  = IRQ_AC97,
3969f19d638SMark Brown 		.end    = IRQ_AC97,
3979f19d638SMark Brown 		.flags  = IORESOURCE_IRQ,
3989f19d638SMark Brown 	},
3999f19d638SMark Brown };
4009f19d638SMark Brown 
4019f19d638SMark Brown static u64 pxa_ac97_dmamask = 0xffffffffUL;
4029f19d638SMark Brown 
4039f19d638SMark Brown struct platform_device pxa_device_ac97 = {
4049f19d638SMark Brown 	.name           = "pxa2xx-ac97",
4059f19d638SMark Brown 	.id             = -1,
4069f19d638SMark Brown 	.dev            = {
4079f19d638SMark Brown 		.dma_mask = &pxa_ac97_dmamask,
4089f19d638SMark Brown 		.coherent_dma_mask = 0xffffffff,
4099f19d638SMark Brown 	},
4109f19d638SMark Brown 	.num_resources  = ARRAY_SIZE(pxa_ac97_resources),
4119f19d638SMark Brown 	.resource       = pxa_ac97_resources,
4129f19d638SMark Brown };
4139f19d638SMark Brown 
4149f19d638SMark Brown void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
4159f19d638SMark Brown {
4169f19d638SMark Brown 	pxa_register_device(&pxa_device_ac97, ops);
4179f19d638SMark Brown }
4189f19d638SMark Brown 
4198f58de7cSeric miao #ifdef CONFIG_PXA25x
4208f58de7cSeric miao 
42175540c1aSeric miao static struct resource pxa25x_resource_pwm0[] = {
42275540c1aSeric miao 	[0] = {
42375540c1aSeric miao 		.start	= 0x40b00000,
42475540c1aSeric miao 		.end	= 0x40b0000f,
42575540c1aSeric miao 		.flags	= IORESOURCE_MEM,
42675540c1aSeric miao 	},
42775540c1aSeric miao };
42875540c1aSeric miao 
42975540c1aSeric miao struct platform_device pxa25x_device_pwm0 = {
43075540c1aSeric miao 	.name		= "pxa25x-pwm",
43175540c1aSeric miao 	.id		= 0,
43275540c1aSeric miao 	.resource	= pxa25x_resource_pwm0,
43375540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm0),
43475540c1aSeric miao };
43575540c1aSeric miao 
43675540c1aSeric miao static struct resource pxa25x_resource_pwm1[] = {
43775540c1aSeric miao 	[0] = {
43875540c1aSeric miao 		.start	= 0x40c00000,
43975540c1aSeric miao 		.end	= 0x40c0000f,
44075540c1aSeric miao 		.flags	= IORESOURCE_MEM,
44175540c1aSeric miao 	},
44275540c1aSeric miao };
44375540c1aSeric miao 
44475540c1aSeric miao struct platform_device pxa25x_device_pwm1 = {
44575540c1aSeric miao 	.name		= "pxa25x-pwm",
44675540c1aSeric miao 	.id		= 1,
44775540c1aSeric miao 	.resource	= pxa25x_resource_pwm1,
44875540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm1),
44975540c1aSeric miao };
45075540c1aSeric miao 
4518f58de7cSeric miao static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
4528f58de7cSeric miao 
4538f58de7cSeric miao static struct resource pxa25x_resource_ssp[] = {
4548f58de7cSeric miao 	[0] = {
4558f58de7cSeric miao 		.start	= 0x41000000,
4568f58de7cSeric miao 		.end	= 0x4100001f,
4578f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
4588f58de7cSeric miao 	},
4598f58de7cSeric miao 	[1] = {
4608f58de7cSeric miao 		.start	= IRQ_SSP,
4618f58de7cSeric miao 		.end	= IRQ_SSP,
4628f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
4638f58de7cSeric miao 	},
4648f58de7cSeric miao 	[2] = {
4658f58de7cSeric miao 		/* DRCMR for RX */
4668f58de7cSeric miao 		.start	= 13,
4678f58de7cSeric miao 		.end	= 13,
4688f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
4698f58de7cSeric miao 	},
4708f58de7cSeric miao 	[3] = {
4718f58de7cSeric miao 		/* DRCMR for TX */
4728f58de7cSeric miao 		.start	= 14,
4738f58de7cSeric miao 		.end	= 14,
4748f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
4758f58de7cSeric miao 	},
4768f58de7cSeric miao };
4778f58de7cSeric miao 
4788f58de7cSeric miao struct platform_device pxa25x_device_ssp = {
4798f58de7cSeric miao 	.name		= "pxa25x-ssp",
4808f58de7cSeric miao 	.id		= 0,
4818f58de7cSeric miao 	.dev		= {
4828f58de7cSeric miao 		.dma_mask = &pxa25x_ssp_dma_mask,
4838f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
4848f58de7cSeric miao 	},
4858f58de7cSeric miao 	.resource	= pxa25x_resource_ssp,
4868f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_ssp),
4878f58de7cSeric miao };
4888f58de7cSeric miao 
4898f58de7cSeric miao static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
4908f58de7cSeric miao 
4918f58de7cSeric miao static struct resource pxa25x_resource_nssp[] = {
4928f58de7cSeric miao 	[0] = {
4938f58de7cSeric miao 		.start	= 0x41400000,
4948f58de7cSeric miao 		.end	= 0x4140002f,
4958f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
4968f58de7cSeric miao 	},
4978f58de7cSeric miao 	[1] = {
4988f58de7cSeric miao 		.start	= IRQ_NSSP,
4998f58de7cSeric miao 		.end	= IRQ_NSSP,
5008f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5018f58de7cSeric miao 	},
5028f58de7cSeric miao 	[2] = {
5038f58de7cSeric miao 		/* DRCMR for RX */
5048f58de7cSeric miao 		.start	= 15,
5058f58de7cSeric miao 		.end	= 15,
5068f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5078f58de7cSeric miao 	},
5088f58de7cSeric miao 	[3] = {
5098f58de7cSeric miao 		/* DRCMR for TX */
5108f58de7cSeric miao 		.start	= 16,
5118f58de7cSeric miao 		.end	= 16,
5128f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5138f58de7cSeric miao 	},
5148f58de7cSeric miao };
5158f58de7cSeric miao 
5168f58de7cSeric miao struct platform_device pxa25x_device_nssp = {
5178f58de7cSeric miao 	.name		= "pxa25x-nssp",
5188f58de7cSeric miao 	.id		= 1,
5198f58de7cSeric miao 	.dev		= {
5208f58de7cSeric miao 		.dma_mask = &pxa25x_nssp_dma_mask,
5218f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
5228f58de7cSeric miao 	},
5238f58de7cSeric miao 	.resource	= pxa25x_resource_nssp,
5248f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_nssp),
5258f58de7cSeric miao };
5268f58de7cSeric miao 
5278f58de7cSeric miao static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
5288f58de7cSeric miao 
5298f58de7cSeric miao static struct resource pxa25x_resource_assp[] = {
5308f58de7cSeric miao 	[0] = {
5318f58de7cSeric miao 		.start	= 0x41500000,
5328f58de7cSeric miao 		.end	= 0x4150002f,
5338f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5348f58de7cSeric miao 	},
5358f58de7cSeric miao 	[1] = {
5368f58de7cSeric miao 		.start	= IRQ_ASSP,
5378f58de7cSeric miao 		.end	= IRQ_ASSP,
5388f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5398f58de7cSeric miao 	},
5408f58de7cSeric miao 	[2] = {
5418f58de7cSeric miao 		/* DRCMR for RX */
5428f58de7cSeric miao 		.start	= 23,
5438f58de7cSeric miao 		.end	= 23,
5448f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5458f58de7cSeric miao 	},
5468f58de7cSeric miao 	[3] = {
5478f58de7cSeric miao 		/* DRCMR for TX */
5488f58de7cSeric miao 		.start	= 24,
5498f58de7cSeric miao 		.end	= 24,
5508f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5518f58de7cSeric miao 	},
5528f58de7cSeric miao };
5538f58de7cSeric miao 
5548f58de7cSeric miao struct platform_device pxa25x_device_assp = {
5558f58de7cSeric miao 	/* ASSP is basically equivalent to NSSP */
5568f58de7cSeric miao 	.name		= "pxa25x-nssp",
5578f58de7cSeric miao 	.id		= 2,
5588f58de7cSeric miao 	.dev		= {
5598f58de7cSeric miao 		.dma_mask = &pxa25x_assp_dma_mask,
5608f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
5618f58de7cSeric miao 	},
5628f58de7cSeric miao 	.resource	= pxa25x_resource_assp,
5638f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_assp),
5648f58de7cSeric miao };
5658f58de7cSeric miao #endif /* CONFIG_PXA25x */
5668f58de7cSeric miao 
5678f58de7cSeric miao #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
5688f58de7cSeric miao 
56937320980Seric miao static struct resource pxa27x_resource_keypad[] = {
57037320980Seric miao 	[0] = {
57137320980Seric miao 		.start	= 0x41500000,
57237320980Seric miao 		.end	= 0x4150004c,
57337320980Seric miao 		.flags	= IORESOURCE_MEM,
57437320980Seric miao 	},
57537320980Seric miao 	[1] = {
57637320980Seric miao 		.start	= IRQ_KEYPAD,
57737320980Seric miao 		.end	= IRQ_KEYPAD,
57837320980Seric miao 		.flags	= IORESOURCE_IRQ,
57937320980Seric miao 	},
58037320980Seric miao };
58137320980Seric miao 
58237320980Seric miao struct platform_device pxa27x_device_keypad = {
58337320980Seric miao 	.name		= "pxa27x-keypad",
58437320980Seric miao 	.id		= -1,
58537320980Seric miao 	.resource	= pxa27x_resource_keypad,
58637320980Seric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_keypad),
58737320980Seric miao };
58837320980Seric miao 
58937320980Seric miao void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
59037320980Seric miao {
59137320980Seric miao 	pxa_register_device(&pxa27x_device_keypad, info);
59237320980Seric miao }
59337320980Seric miao 
594ec68e45bSeric miao static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
595ec68e45bSeric miao 
596ec68e45bSeric miao static struct resource pxa27x_resource_ohci[] = {
597ec68e45bSeric miao 	[0] = {
598ec68e45bSeric miao 		.start  = 0x4C000000,
599ec68e45bSeric miao 		.end    = 0x4C00ff6f,
600ec68e45bSeric miao 		.flags  = IORESOURCE_MEM,
601ec68e45bSeric miao 	},
602ec68e45bSeric miao 	[1] = {
603ec68e45bSeric miao 		.start  = IRQ_USBH1,
604ec68e45bSeric miao 		.end    = IRQ_USBH1,
605ec68e45bSeric miao 		.flags  = IORESOURCE_IRQ,
606ec68e45bSeric miao 	},
607ec68e45bSeric miao };
608ec68e45bSeric miao 
609ec68e45bSeric miao struct platform_device pxa27x_device_ohci = {
610ec68e45bSeric miao 	.name		= "pxa27x-ohci",
611ec68e45bSeric miao 	.id		= -1,
612ec68e45bSeric miao 	.dev		= {
613ec68e45bSeric miao 		.dma_mask = &pxa27x_ohci_dma_mask,
614ec68e45bSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
615ec68e45bSeric miao 	},
616ec68e45bSeric miao 	.num_resources  = ARRAY_SIZE(pxa27x_resource_ohci),
617ec68e45bSeric miao 	.resource       = pxa27x_resource_ohci,
618ec68e45bSeric miao };
619ec68e45bSeric miao 
620ec68e45bSeric miao void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
621ec68e45bSeric miao {
622ec68e45bSeric miao 	pxa_register_device(&pxa27x_device_ohci, info);
623ec68e45bSeric miao }
624ec68e45bSeric miao 
6258f58de7cSeric miao static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
6268f58de7cSeric miao 
6278f58de7cSeric miao static struct resource pxa27x_resource_ssp1[] = {
6288f58de7cSeric miao 	[0] = {
6298f58de7cSeric miao 		.start	= 0x41000000,
6308f58de7cSeric miao 		.end	= 0x4100003f,
6318f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
6328f58de7cSeric miao 	},
6338f58de7cSeric miao 	[1] = {
6348f58de7cSeric miao 		.start	= IRQ_SSP,
6358f58de7cSeric miao 		.end	= IRQ_SSP,
6368f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
6378f58de7cSeric miao 	},
6388f58de7cSeric miao 	[2] = {
6398f58de7cSeric miao 		/* DRCMR for RX */
6408f58de7cSeric miao 		.start	= 13,
6418f58de7cSeric miao 		.end	= 13,
6428f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6438f58de7cSeric miao 	},
6448f58de7cSeric miao 	[3] = {
6458f58de7cSeric miao 		/* DRCMR for TX */
6468f58de7cSeric miao 		.start	= 14,
6478f58de7cSeric miao 		.end	= 14,
6488f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6498f58de7cSeric miao 	},
6508f58de7cSeric miao };
6518f58de7cSeric miao 
6528f58de7cSeric miao struct platform_device pxa27x_device_ssp1 = {
6538f58de7cSeric miao 	.name		= "pxa27x-ssp",
6548f58de7cSeric miao 	.id		= 0,
6558f58de7cSeric miao 	.dev		= {
6568f58de7cSeric miao 		.dma_mask = &pxa27x_ssp1_dma_mask,
6578f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
6588f58de7cSeric miao 	},
6598f58de7cSeric miao 	.resource	= pxa27x_resource_ssp1,
6608f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
6618f58de7cSeric miao };
6628f58de7cSeric miao 
6638f58de7cSeric miao static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
6648f58de7cSeric miao 
6658f58de7cSeric miao static struct resource pxa27x_resource_ssp2[] = {
6668f58de7cSeric miao 	[0] = {
6678f58de7cSeric miao 		.start	= 0x41700000,
6688f58de7cSeric miao 		.end	= 0x4170003f,
6698f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
6708f58de7cSeric miao 	},
6718f58de7cSeric miao 	[1] = {
6728f58de7cSeric miao 		.start	= IRQ_SSP2,
6738f58de7cSeric miao 		.end	= IRQ_SSP2,
6748f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
6758f58de7cSeric miao 	},
6768f58de7cSeric miao 	[2] = {
6778f58de7cSeric miao 		/* DRCMR for RX */
6788f58de7cSeric miao 		.start	= 15,
6798f58de7cSeric miao 		.end	= 15,
6808f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6818f58de7cSeric miao 	},
6828f58de7cSeric miao 	[3] = {
6838f58de7cSeric miao 		/* DRCMR for TX */
6848f58de7cSeric miao 		.start	= 16,
6858f58de7cSeric miao 		.end	= 16,
6868f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6878f58de7cSeric miao 	},
6888f58de7cSeric miao };
6898f58de7cSeric miao 
6908f58de7cSeric miao struct platform_device pxa27x_device_ssp2 = {
6918f58de7cSeric miao 	.name		= "pxa27x-ssp",
6928f58de7cSeric miao 	.id		= 1,
6938f58de7cSeric miao 	.dev		= {
6948f58de7cSeric miao 		.dma_mask = &pxa27x_ssp2_dma_mask,
6958f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
6968f58de7cSeric miao 	},
6978f58de7cSeric miao 	.resource	= pxa27x_resource_ssp2,
6988f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
6998f58de7cSeric miao };
7008f58de7cSeric miao 
7018f58de7cSeric miao static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
7028f58de7cSeric miao 
7038f58de7cSeric miao static struct resource pxa27x_resource_ssp3[] = {
7048f58de7cSeric miao 	[0] = {
7058f58de7cSeric miao 		.start	= 0x41900000,
7068f58de7cSeric miao 		.end	= 0x4190003f,
7078f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
7088f58de7cSeric miao 	},
7098f58de7cSeric miao 	[1] = {
7108f58de7cSeric miao 		.start	= IRQ_SSP3,
7118f58de7cSeric miao 		.end	= IRQ_SSP3,
7128f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
7138f58de7cSeric miao 	},
7148f58de7cSeric miao 	[2] = {
7158f58de7cSeric miao 		/* DRCMR for RX */
7168f58de7cSeric miao 		.start	= 66,
7178f58de7cSeric miao 		.end	= 66,
7188f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7198f58de7cSeric miao 	},
7208f58de7cSeric miao 	[3] = {
7218f58de7cSeric miao 		/* DRCMR for TX */
7228f58de7cSeric miao 		.start	= 67,
7238f58de7cSeric miao 		.end	= 67,
7248f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7258f58de7cSeric miao 	},
7268f58de7cSeric miao };
7278f58de7cSeric miao 
7288f58de7cSeric miao struct platform_device pxa27x_device_ssp3 = {
7298f58de7cSeric miao 	.name		= "pxa27x-ssp",
7308f58de7cSeric miao 	.id		= 2,
7318f58de7cSeric miao 	.dev		= {
7328f58de7cSeric miao 		.dma_mask = &pxa27x_ssp3_dma_mask,
7338f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
7348f58de7cSeric miao 	},
7358f58de7cSeric miao 	.resource	= pxa27x_resource_ssp3,
7368f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
7378f58de7cSeric miao };
7383f3acefbSGuennadi Liakhovetski 
73975540c1aSeric miao static struct resource pxa27x_resource_pwm0[] = {
74075540c1aSeric miao 	[0] = {
74175540c1aSeric miao 		.start	= 0x40b00000,
74275540c1aSeric miao 		.end	= 0x40b0001f,
74375540c1aSeric miao 		.flags	= IORESOURCE_MEM,
74475540c1aSeric miao 	},
74575540c1aSeric miao };
74675540c1aSeric miao 
74775540c1aSeric miao struct platform_device pxa27x_device_pwm0 = {
74875540c1aSeric miao 	.name		= "pxa27x-pwm",
74975540c1aSeric miao 	.id		= 0,
75075540c1aSeric miao 	.resource	= pxa27x_resource_pwm0,
75175540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm0),
75275540c1aSeric miao };
75375540c1aSeric miao 
75475540c1aSeric miao static struct resource pxa27x_resource_pwm1[] = {
75575540c1aSeric miao 	[0] = {
75675540c1aSeric miao 		.start	= 0x40c00000,
75775540c1aSeric miao 		.end	= 0x40c0001f,
75875540c1aSeric miao 		.flags	= IORESOURCE_MEM,
75975540c1aSeric miao 	},
76075540c1aSeric miao };
76175540c1aSeric miao 
76275540c1aSeric miao struct platform_device pxa27x_device_pwm1 = {
76375540c1aSeric miao 	.name		= "pxa27x-pwm",
76475540c1aSeric miao 	.id		= 1,
76575540c1aSeric miao 	.resource	= pxa27x_resource_pwm1,
76675540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm1),
76775540c1aSeric miao };
76875540c1aSeric miao 
7693f3acefbSGuennadi Liakhovetski static struct resource pxa27x_resource_camera[] = {
7703f3acefbSGuennadi Liakhovetski 	[0] = {
7713f3acefbSGuennadi Liakhovetski 		.start	= 0x50000000,
7723f3acefbSGuennadi Liakhovetski 		.end	= 0x50000fff,
7733f3acefbSGuennadi Liakhovetski 		.flags	= IORESOURCE_MEM,
7743f3acefbSGuennadi Liakhovetski 	},
7753f3acefbSGuennadi Liakhovetski 	[1] = {
7763f3acefbSGuennadi Liakhovetski 		.start	= IRQ_CAMERA,
7773f3acefbSGuennadi Liakhovetski 		.end	= IRQ_CAMERA,
7783f3acefbSGuennadi Liakhovetski 		.flags	= IORESOURCE_IRQ,
7793f3acefbSGuennadi Liakhovetski 	},
7803f3acefbSGuennadi Liakhovetski };
7813f3acefbSGuennadi Liakhovetski 
7823f3acefbSGuennadi Liakhovetski static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
7833f3acefbSGuennadi Liakhovetski 
7843f3acefbSGuennadi Liakhovetski static struct platform_device pxa27x_device_camera = {
7853f3acefbSGuennadi Liakhovetski 	.name		= "pxa27x-camera",
7863f3acefbSGuennadi Liakhovetski 	.id		= 0, /* This is used to put cameras on this interface */
7873f3acefbSGuennadi Liakhovetski 	.dev		= {
7883f3acefbSGuennadi Liakhovetski 		.dma_mask      		= &pxa27x_dma_mask_camera,
7893f3acefbSGuennadi Liakhovetski 		.coherent_dma_mask	= 0xffffffff,
7903f3acefbSGuennadi Liakhovetski 	},
7913f3acefbSGuennadi Liakhovetski 	.num_resources	= ARRAY_SIZE(pxa27x_resource_camera),
7923f3acefbSGuennadi Liakhovetski 	.resource	= pxa27x_resource_camera,
7933f3acefbSGuennadi Liakhovetski };
7943f3acefbSGuennadi Liakhovetski 
7953f3acefbSGuennadi Liakhovetski void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
7963f3acefbSGuennadi Liakhovetski {
7973f3acefbSGuennadi Liakhovetski 	pxa_register_device(&pxa27x_device_camera, info);
7983f3acefbSGuennadi Liakhovetski }
7998f58de7cSeric miao #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
8008f58de7cSeric miao 
8018f58de7cSeric miao #ifdef CONFIG_PXA3xx
8028f58de7cSeric miao static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
8038f58de7cSeric miao 
8048f58de7cSeric miao static struct resource pxa3xx_resource_ssp4[] = {
8058f58de7cSeric miao 	[0] = {
8068f58de7cSeric miao 		.start	= 0x41a00000,
8078f58de7cSeric miao 		.end	= 0x41a0003f,
8088f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
8098f58de7cSeric miao 	},
8108f58de7cSeric miao 	[1] = {
8118f58de7cSeric miao 		.start	= IRQ_SSP4,
8128f58de7cSeric miao 		.end	= IRQ_SSP4,
8138f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
8148f58de7cSeric miao 	},
8158f58de7cSeric miao 	[2] = {
8168f58de7cSeric miao 		/* DRCMR for RX */
8178f58de7cSeric miao 		.start	= 2,
8188f58de7cSeric miao 		.end	= 2,
8198f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
8208f58de7cSeric miao 	},
8218f58de7cSeric miao 	[3] = {
8228f58de7cSeric miao 		/* DRCMR for TX */
8238f58de7cSeric miao 		.start	= 3,
8248f58de7cSeric miao 		.end	= 3,
8258f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
8268f58de7cSeric miao 	},
8278f58de7cSeric miao };
8288f58de7cSeric miao 
8298f58de7cSeric miao struct platform_device pxa3xx_device_ssp4 = {
8308f58de7cSeric miao 	/* PXA3xx SSP is basically equivalent to PXA27x */
8318f58de7cSeric miao 	.name		= "pxa27x-ssp",
8328f58de7cSeric miao 	.id		= 3,
8338f58de7cSeric miao 	.dev		= {
8348f58de7cSeric miao 		.dma_mask = &pxa3xx_ssp4_dma_mask,
8358f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
8368f58de7cSeric miao 	},
8378f58de7cSeric miao 	.resource	= pxa3xx_resource_ssp4,
8388f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa3xx_resource_ssp4),
8398f58de7cSeric miao };
8408d33b055SBridge Wu 
8418d33b055SBridge Wu static struct resource pxa3xx_resources_mci2[] = {
8428d33b055SBridge Wu 	[0] = {
8438d33b055SBridge Wu 		.start	= 0x42000000,
8448d33b055SBridge Wu 		.end	= 0x42000fff,
8458d33b055SBridge Wu 		.flags	= IORESOURCE_MEM,
8468d33b055SBridge Wu 	},
8478d33b055SBridge Wu 	[1] = {
8488d33b055SBridge Wu 		.start	= IRQ_MMC2,
8498d33b055SBridge Wu 		.end	= IRQ_MMC2,
8508d33b055SBridge Wu 		.flags	= IORESOURCE_IRQ,
8518d33b055SBridge Wu 	},
8528d33b055SBridge Wu 	[2] = {
8538d33b055SBridge Wu 		.start	= 93,
8548d33b055SBridge Wu 		.end	= 93,
8558d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
8568d33b055SBridge Wu 	},
8578d33b055SBridge Wu 	[3] = {
8588d33b055SBridge Wu 		.start	= 94,
8598d33b055SBridge Wu 		.end	= 94,
8608d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
8618d33b055SBridge Wu 	},
8628d33b055SBridge Wu };
8638d33b055SBridge Wu 
8648d33b055SBridge Wu struct platform_device pxa3xx_device_mci2 = {
8658d33b055SBridge Wu 	.name		= "pxa2xx-mci",
8668d33b055SBridge Wu 	.id		= 1,
8678d33b055SBridge Wu 	.dev		= {
8688d33b055SBridge Wu 		.dma_mask = &pxamci_dmamask,
8698d33b055SBridge Wu 		.coherent_dma_mask =	0xffffffff,
8708d33b055SBridge Wu 	},
8718d33b055SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci2),
8728d33b055SBridge Wu 	.resource	= pxa3xx_resources_mci2,
8738d33b055SBridge Wu };
8748d33b055SBridge Wu 
8758d33b055SBridge Wu void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
8768d33b055SBridge Wu {
8778d33b055SBridge Wu 	pxa_register_device(&pxa3xx_device_mci2, info);
8788d33b055SBridge Wu }
8798d33b055SBridge Wu 
8805a1f21b1SBridge Wu static struct resource pxa3xx_resources_mci3[] = {
8815a1f21b1SBridge Wu 	[0] = {
8825a1f21b1SBridge Wu 		.start	= 0x42500000,
8835a1f21b1SBridge Wu 		.end	= 0x42500fff,
8845a1f21b1SBridge Wu 		.flags	= IORESOURCE_MEM,
8855a1f21b1SBridge Wu 	},
8865a1f21b1SBridge Wu 	[1] = {
8875a1f21b1SBridge Wu 		.start	= IRQ_MMC3,
8885a1f21b1SBridge Wu 		.end	= IRQ_MMC3,
8895a1f21b1SBridge Wu 		.flags	= IORESOURCE_IRQ,
8905a1f21b1SBridge Wu 	},
8915a1f21b1SBridge Wu 	[2] = {
8925a1f21b1SBridge Wu 		.start	= 100,
8935a1f21b1SBridge Wu 		.end	= 100,
8945a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
8955a1f21b1SBridge Wu 	},
8965a1f21b1SBridge Wu 	[3] = {
8975a1f21b1SBridge Wu 		.start	= 101,
8985a1f21b1SBridge Wu 		.end	= 101,
8995a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
9005a1f21b1SBridge Wu 	},
9015a1f21b1SBridge Wu };
9025a1f21b1SBridge Wu 
9035a1f21b1SBridge Wu struct platform_device pxa3xx_device_mci3 = {
9045a1f21b1SBridge Wu 	.name		= "pxa2xx-mci",
9055a1f21b1SBridge Wu 	.id		= 2,
9065a1f21b1SBridge Wu 	.dev		= {
9075a1f21b1SBridge Wu 		.dma_mask = &pxamci_dmamask,
9085a1f21b1SBridge Wu 		.coherent_dma_mask = 0xffffffff,
9095a1f21b1SBridge Wu 	},
9105a1f21b1SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci3),
9115a1f21b1SBridge Wu 	.resource	= pxa3xx_resources_mci3,
9125a1f21b1SBridge Wu };
9135a1f21b1SBridge Wu 
9145a1f21b1SBridge Wu void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
9155a1f21b1SBridge Wu {
9165a1f21b1SBridge Wu 	pxa_register_device(&pxa3xx_device_mci3, info);
9175a1f21b1SBridge Wu }
9185a1f21b1SBridge Wu 
9199ae819a8SEric Miao static struct resource pxa3xx_resources_nand[] = {
9209ae819a8SEric Miao 	[0] = {
9219ae819a8SEric Miao 		.start	= 0x43100000,
9229ae819a8SEric Miao 		.end	= 0x43100053,
9239ae819a8SEric Miao 		.flags	= IORESOURCE_MEM,
9249ae819a8SEric Miao 	},
9259ae819a8SEric Miao 	[1] = {
9269ae819a8SEric Miao 		.start	= IRQ_NAND,
9279ae819a8SEric Miao 		.end	= IRQ_NAND,
9289ae819a8SEric Miao 		.flags	= IORESOURCE_IRQ,
9299ae819a8SEric Miao 	},
9309ae819a8SEric Miao 	[2] = {
9319ae819a8SEric Miao 		/* DRCMR for Data DMA */
9329ae819a8SEric Miao 		.start	= 97,
9339ae819a8SEric Miao 		.end	= 97,
9349ae819a8SEric Miao 		.flags	= IORESOURCE_DMA,
9359ae819a8SEric Miao 	},
9369ae819a8SEric Miao 	[3] = {
9379ae819a8SEric Miao 		/* DRCMR for Command DMA */
9389ae819a8SEric Miao 		.start	= 99,
9399ae819a8SEric Miao 		.end	= 99,
9409ae819a8SEric Miao 		.flags	= IORESOURCE_DMA,
9419ae819a8SEric Miao 	},
9429ae819a8SEric Miao };
9439ae819a8SEric Miao 
9449ae819a8SEric Miao static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
9459ae819a8SEric Miao 
9469ae819a8SEric Miao struct platform_device pxa3xx_device_nand = {
9479ae819a8SEric Miao 	.name		= "pxa3xx-nand",
9489ae819a8SEric Miao 	.id		= -1,
9499ae819a8SEric Miao 	.dev		= {
9509ae819a8SEric Miao 		.dma_mask = &pxa3xx_nand_dma_mask,
9519ae819a8SEric Miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
9529ae819a8SEric Miao 	},
9539ae819a8SEric Miao 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_nand),
9549ae819a8SEric Miao 	.resource	= pxa3xx_resources_nand,
9559ae819a8SEric Miao };
9569ae819a8SEric Miao 
9579ae819a8SEric Miao void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
9589ae819a8SEric Miao {
9599ae819a8SEric Miao 	pxa_register_device(&pxa3xx_device_nand, info);
9609ae819a8SEric Miao }
9611ff2c33eSDaniel Mack 
9621ff2c33eSDaniel Mack static struct resource pxa3xx_resources_gcu[] = {
9631ff2c33eSDaniel Mack 	{
9641ff2c33eSDaniel Mack 		.start	= 0x54000000,
9651ff2c33eSDaniel Mack 		.end	= 0x54000fff,
9661ff2c33eSDaniel Mack 		.flags	= IORESOURCE_MEM,
9671ff2c33eSDaniel Mack 	},
9681ff2c33eSDaniel Mack 	{
9691ff2c33eSDaniel Mack 		.start	= IRQ_GCU,
9701ff2c33eSDaniel Mack 		.end	= IRQ_GCU,
9711ff2c33eSDaniel Mack 		.flags	= IORESOURCE_IRQ,
9721ff2c33eSDaniel Mack 	},
9731ff2c33eSDaniel Mack };
9741ff2c33eSDaniel Mack 
9751ff2c33eSDaniel Mack static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
9761ff2c33eSDaniel Mack 
9771ff2c33eSDaniel Mack struct platform_device pxa3xx_device_gcu = {
9781ff2c33eSDaniel Mack 	.name		= "pxa3xx-gcu",
9791ff2c33eSDaniel Mack 	.id		= -1,
9801ff2c33eSDaniel Mack 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_gcu),
9811ff2c33eSDaniel Mack 	.resource	= pxa3xx_resources_gcu,
9821ff2c33eSDaniel Mack 	.dev		= {
9831ff2c33eSDaniel Mack 		.dma_mask = &pxa3xx_gcu_dmamask,
9841ff2c33eSDaniel Mack 		.coherent_dma_mask = 0xffffffff,
9851ff2c33eSDaniel Mack 	},
9861ff2c33eSDaniel Mack };
9871ff2c33eSDaniel Mack 
9888f58de7cSeric miao #endif /* CONFIG_PXA3xx */
989e172274cSGuennadi Liakhovetski 
990e172274cSGuennadi Liakhovetski /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
991e172274cSGuennadi Liakhovetski  * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
992e172274cSGuennadi Liakhovetski void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
993e172274cSGuennadi Liakhovetski {
994e172274cSGuennadi Liakhovetski 	struct platform_device *pd;
995e172274cSGuennadi Liakhovetski 
996e172274cSGuennadi Liakhovetski 	pd = platform_device_alloc("pxa2xx-spi", id);
997e172274cSGuennadi Liakhovetski 	if (pd == NULL) {
998e172274cSGuennadi Liakhovetski 		printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
999e172274cSGuennadi Liakhovetski 		       id);
1000e172274cSGuennadi Liakhovetski 		return;
1001e172274cSGuennadi Liakhovetski 	}
1002e172274cSGuennadi Liakhovetski 
1003e172274cSGuennadi Liakhovetski 	pd->dev.platform_data = info;
1004e172274cSGuennadi Liakhovetski 	platform_device_add(pd);
1005e172274cSGuennadi Liakhovetski }
1006