18f58de7cSeric miao #include <linux/module.h> 28f58de7cSeric miao #include <linux/kernel.h> 38f58de7cSeric miao #include <linux/init.h> 48f58de7cSeric miao #include <linux/platform_device.h> 58f58de7cSeric miao #include <linux/dma-mapping.h> 68f58de7cSeric miao 78f58de7cSeric miao #include <asm/arch/gpio.h> 88f58de7cSeric miao #include <asm/arch/udc.h> 98f58de7cSeric miao #include <asm/arch/pxafb.h> 108f58de7cSeric miao #include <asm/arch/mmc.h> 118f58de7cSeric miao #include <asm/arch/irda.h> 128f58de7cSeric miao #include <asm/arch/i2c.h> 13*bc3a5959SPhilipp Zabel #include <asm/arch/mfp-pxa27x.h> 14cd5604d5Seric miao #include <asm/arch/ohci.h> 1537320980Seric miao #include <asm/arch/pxa27x_keypad.h> 163f3acefbSGuennadi Liakhovetski #include <asm/arch/camera.h> 178f58de7cSeric miao 188f58de7cSeric miao #include "devices.h" 19*bc3a5959SPhilipp Zabel #include "generic.h" 208f58de7cSeric miao 218f58de7cSeric miao void __init pxa_register_device(struct platform_device *dev, void *data) 228f58de7cSeric miao { 238f58de7cSeric miao int ret; 248f58de7cSeric miao 258f58de7cSeric miao dev->dev.platform_data = data; 268f58de7cSeric miao 278f58de7cSeric miao ret = platform_device_register(dev); 288f58de7cSeric miao if (ret) 298f58de7cSeric miao dev_err(&dev->dev, "unable to register device: %d\n", ret); 308f58de7cSeric miao } 318f58de7cSeric miao 328f58de7cSeric miao static struct resource pxamci_resources[] = { 338f58de7cSeric miao [0] = { 348f58de7cSeric miao .start = 0x41100000, 358f58de7cSeric miao .end = 0x41100fff, 368f58de7cSeric miao .flags = IORESOURCE_MEM, 378f58de7cSeric miao }, 388f58de7cSeric miao [1] = { 398f58de7cSeric miao .start = IRQ_MMC, 408f58de7cSeric miao .end = IRQ_MMC, 418f58de7cSeric miao .flags = IORESOURCE_IRQ, 428f58de7cSeric miao }, 438f58de7cSeric miao [2] = { 448f58de7cSeric miao .start = 21, 458f58de7cSeric miao .end = 21, 468f58de7cSeric miao .flags = IORESOURCE_DMA, 478f58de7cSeric miao }, 488f58de7cSeric miao [3] = { 498f58de7cSeric miao .start = 22, 508f58de7cSeric miao .end = 22, 518f58de7cSeric miao .flags = IORESOURCE_DMA, 528f58de7cSeric miao }, 538f58de7cSeric miao }; 548f58de7cSeric miao 558f58de7cSeric miao static u64 pxamci_dmamask = 0xffffffffUL; 568f58de7cSeric miao 578f58de7cSeric miao struct platform_device pxa_device_mci = { 588f58de7cSeric miao .name = "pxa2xx-mci", 59fafc9d3fSBridge Wu .id = 0, 608f58de7cSeric miao .dev = { 618f58de7cSeric miao .dma_mask = &pxamci_dmamask, 628f58de7cSeric miao .coherent_dma_mask = 0xffffffff, 638f58de7cSeric miao }, 648f58de7cSeric miao .num_resources = ARRAY_SIZE(pxamci_resources), 658f58de7cSeric miao .resource = pxamci_resources, 668f58de7cSeric miao }; 678f58de7cSeric miao 688f58de7cSeric miao void __init pxa_set_mci_info(struct pxamci_platform_data *info) 698f58de7cSeric miao { 708f58de7cSeric miao pxa_register_device(&pxa_device_mci, info); 718f58de7cSeric miao } 728f58de7cSeric miao 738f58de7cSeric miao 748f58de7cSeric miao static struct pxa2xx_udc_mach_info pxa_udc_info; 758f58de7cSeric miao 768f58de7cSeric miao void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info) 778f58de7cSeric miao { 788f58de7cSeric miao memcpy(&pxa_udc_info, info, sizeof *info); 798f58de7cSeric miao } 808f58de7cSeric miao 818f58de7cSeric miao static struct resource pxa2xx_udc_resources[] = { 828f58de7cSeric miao [0] = { 838f58de7cSeric miao .start = 0x40600000, 848f58de7cSeric miao .end = 0x4060ffff, 858f58de7cSeric miao .flags = IORESOURCE_MEM, 868f58de7cSeric miao }, 878f58de7cSeric miao [1] = { 888f58de7cSeric miao .start = IRQ_USB, 898f58de7cSeric miao .end = IRQ_USB, 908f58de7cSeric miao .flags = IORESOURCE_IRQ, 918f58de7cSeric miao }, 928f58de7cSeric miao }; 938f58de7cSeric miao 948f58de7cSeric miao static u64 udc_dma_mask = ~(u32)0; 958f58de7cSeric miao 968f58de7cSeric miao struct platform_device pxa_device_udc = { 978f58de7cSeric miao .name = "pxa2xx-udc", 988f58de7cSeric miao .id = -1, 998f58de7cSeric miao .resource = pxa2xx_udc_resources, 1008f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa2xx_udc_resources), 1018f58de7cSeric miao .dev = { 1028f58de7cSeric miao .platform_data = &pxa_udc_info, 1038f58de7cSeric miao .dma_mask = &udc_dma_mask, 1048f58de7cSeric miao } 1058f58de7cSeric miao }; 1068f58de7cSeric miao 1078f58de7cSeric miao static struct resource pxafb_resources[] = { 1088f58de7cSeric miao [0] = { 1098f58de7cSeric miao .start = 0x44000000, 1108f58de7cSeric miao .end = 0x4400ffff, 1118f58de7cSeric miao .flags = IORESOURCE_MEM, 1128f58de7cSeric miao }, 1138f58de7cSeric miao [1] = { 1148f58de7cSeric miao .start = IRQ_LCD, 1158f58de7cSeric miao .end = IRQ_LCD, 1168f58de7cSeric miao .flags = IORESOURCE_IRQ, 1178f58de7cSeric miao }, 1188f58de7cSeric miao }; 1198f58de7cSeric miao 1208f58de7cSeric miao static u64 fb_dma_mask = ~(u64)0; 1218f58de7cSeric miao 1228f58de7cSeric miao struct platform_device pxa_device_fb = { 1238f58de7cSeric miao .name = "pxa2xx-fb", 1248f58de7cSeric miao .id = -1, 1258f58de7cSeric miao .dev = { 1268f58de7cSeric miao .dma_mask = &fb_dma_mask, 1278f58de7cSeric miao .coherent_dma_mask = 0xffffffff, 1288f58de7cSeric miao }, 1298f58de7cSeric miao .num_resources = ARRAY_SIZE(pxafb_resources), 1308f58de7cSeric miao .resource = pxafb_resources, 1318f58de7cSeric miao }; 1328f58de7cSeric miao 1338f58de7cSeric miao void __init set_pxa_fb_info(struct pxafb_mach_info *info) 1348f58de7cSeric miao { 1358f58de7cSeric miao pxa_register_device(&pxa_device_fb, info); 1368f58de7cSeric miao } 1378f58de7cSeric miao 1388f58de7cSeric miao void __init set_pxa_fb_parent(struct device *parent_dev) 1398f58de7cSeric miao { 1408f58de7cSeric miao pxa_device_fb.dev.parent = parent_dev; 1418f58de7cSeric miao } 1428f58de7cSeric miao 1438f58de7cSeric miao static struct resource pxa_resource_ffuart[] = { 1448f58de7cSeric miao { 1458f58de7cSeric miao .start = __PREG(FFUART), 1468f58de7cSeric miao .end = __PREG(FFUART) + 35, 1478f58de7cSeric miao .flags = IORESOURCE_MEM, 1488f58de7cSeric miao }, { 1498f58de7cSeric miao .start = IRQ_FFUART, 1508f58de7cSeric miao .end = IRQ_FFUART, 1518f58de7cSeric miao .flags = IORESOURCE_IRQ, 1528f58de7cSeric miao } 1538f58de7cSeric miao }; 1548f58de7cSeric miao 1558f58de7cSeric miao struct platform_device pxa_device_ffuart= { 1568f58de7cSeric miao .name = "pxa2xx-uart", 1578f58de7cSeric miao .id = 0, 1588f58de7cSeric miao .resource = pxa_resource_ffuart, 1598f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa_resource_ffuart), 1608f58de7cSeric miao }; 1618f58de7cSeric miao 1628f58de7cSeric miao static struct resource pxa_resource_btuart[] = { 1638f58de7cSeric miao { 1648f58de7cSeric miao .start = __PREG(BTUART), 1658f58de7cSeric miao .end = __PREG(BTUART) + 35, 1668f58de7cSeric miao .flags = IORESOURCE_MEM, 1678f58de7cSeric miao }, { 1688f58de7cSeric miao .start = IRQ_BTUART, 1698f58de7cSeric miao .end = IRQ_BTUART, 1708f58de7cSeric miao .flags = IORESOURCE_IRQ, 1718f58de7cSeric miao } 1728f58de7cSeric miao }; 1738f58de7cSeric miao 1748f58de7cSeric miao struct platform_device pxa_device_btuart = { 1758f58de7cSeric miao .name = "pxa2xx-uart", 1768f58de7cSeric miao .id = 1, 1778f58de7cSeric miao .resource = pxa_resource_btuart, 1788f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa_resource_btuart), 1798f58de7cSeric miao }; 1808f58de7cSeric miao 1818f58de7cSeric miao static struct resource pxa_resource_stuart[] = { 1828f58de7cSeric miao { 1838f58de7cSeric miao .start = __PREG(STUART), 1848f58de7cSeric miao .end = __PREG(STUART) + 35, 1858f58de7cSeric miao .flags = IORESOURCE_MEM, 1868f58de7cSeric miao }, { 1878f58de7cSeric miao .start = IRQ_STUART, 1888f58de7cSeric miao .end = IRQ_STUART, 1898f58de7cSeric miao .flags = IORESOURCE_IRQ, 1908f58de7cSeric miao } 1918f58de7cSeric miao }; 1928f58de7cSeric miao 1938f58de7cSeric miao struct platform_device pxa_device_stuart = { 1948f58de7cSeric miao .name = "pxa2xx-uart", 1958f58de7cSeric miao .id = 2, 1968f58de7cSeric miao .resource = pxa_resource_stuart, 1978f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa_resource_stuart), 1988f58de7cSeric miao }; 1998f58de7cSeric miao 2008f58de7cSeric miao static struct resource pxa_resource_hwuart[] = { 2018f58de7cSeric miao { 2028f58de7cSeric miao .start = __PREG(HWUART), 2038f58de7cSeric miao .end = __PREG(HWUART) + 47, 2048f58de7cSeric miao .flags = IORESOURCE_MEM, 2058f58de7cSeric miao }, { 2068f58de7cSeric miao .start = IRQ_HWUART, 2078f58de7cSeric miao .end = IRQ_HWUART, 2088f58de7cSeric miao .flags = IORESOURCE_IRQ, 2098f58de7cSeric miao } 2108f58de7cSeric miao }; 2118f58de7cSeric miao 2128f58de7cSeric miao struct platform_device pxa_device_hwuart = { 2138f58de7cSeric miao .name = "pxa2xx-uart", 2148f58de7cSeric miao .id = 3, 2158f58de7cSeric miao .resource = pxa_resource_hwuart, 2168f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa_resource_hwuart), 2178f58de7cSeric miao }; 2188f58de7cSeric miao 2198f58de7cSeric miao static struct resource pxai2c_resources[] = { 2208f58de7cSeric miao { 2218f58de7cSeric miao .start = 0x40301680, 2228f58de7cSeric miao .end = 0x403016a3, 2238f58de7cSeric miao .flags = IORESOURCE_MEM, 2248f58de7cSeric miao }, { 2258f58de7cSeric miao .start = IRQ_I2C, 2268f58de7cSeric miao .end = IRQ_I2C, 2278f58de7cSeric miao .flags = IORESOURCE_IRQ, 2288f58de7cSeric miao }, 2298f58de7cSeric miao }; 2308f58de7cSeric miao 2318f58de7cSeric miao struct platform_device pxa_device_i2c = { 2328f58de7cSeric miao .name = "pxa2xx-i2c", 2338f58de7cSeric miao .id = 0, 2348f58de7cSeric miao .resource = pxai2c_resources, 2358f58de7cSeric miao .num_resources = ARRAY_SIZE(pxai2c_resources), 2368f58de7cSeric miao }; 2378f58de7cSeric miao 238*bc3a5959SPhilipp Zabel static unsigned long pxa27x_i2c_mfp_cfg[] = { 239*bc3a5959SPhilipp Zabel GPIO117_I2C_SCL, 240*bc3a5959SPhilipp Zabel GPIO118_I2C_SDA, 241*bc3a5959SPhilipp Zabel }; 242*bc3a5959SPhilipp Zabel 2438f58de7cSeric miao void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) 2448f58de7cSeric miao { 245*bc3a5959SPhilipp Zabel if (cpu_is_pxa27x()) 246*bc3a5959SPhilipp Zabel pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg)); 2478f58de7cSeric miao pxa_register_device(&pxa_device_i2c, info); 2488f58de7cSeric miao } 2498f58de7cSeric miao 2508f58de7cSeric miao static struct resource pxai2s_resources[] = { 2518f58de7cSeric miao { 2528f58de7cSeric miao .start = 0x40400000, 2538f58de7cSeric miao .end = 0x40400083, 2548f58de7cSeric miao .flags = IORESOURCE_MEM, 2558f58de7cSeric miao }, { 2568f58de7cSeric miao .start = IRQ_I2S, 2578f58de7cSeric miao .end = IRQ_I2S, 2588f58de7cSeric miao .flags = IORESOURCE_IRQ, 2598f58de7cSeric miao }, 2608f58de7cSeric miao }; 2618f58de7cSeric miao 2628f58de7cSeric miao struct platform_device pxa_device_i2s = { 2638f58de7cSeric miao .name = "pxa2xx-i2s", 2648f58de7cSeric miao .id = -1, 2658f58de7cSeric miao .resource = pxai2s_resources, 2668f58de7cSeric miao .num_resources = ARRAY_SIZE(pxai2s_resources), 2678f58de7cSeric miao }; 2688f58de7cSeric miao 2698f58de7cSeric miao static u64 pxaficp_dmamask = ~(u32)0; 2708f58de7cSeric miao 2718f58de7cSeric miao struct platform_device pxa_device_ficp = { 2728f58de7cSeric miao .name = "pxa2xx-ir", 2738f58de7cSeric miao .id = -1, 2748f58de7cSeric miao .dev = { 2758f58de7cSeric miao .dma_mask = &pxaficp_dmamask, 2768f58de7cSeric miao .coherent_dma_mask = 0xffffffff, 2778f58de7cSeric miao }, 2788f58de7cSeric miao }; 2798f58de7cSeric miao 2808f58de7cSeric miao void __init pxa_set_ficp_info(struct pxaficp_platform_data *info) 2818f58de7cSeric miao { 2828f58de7cSeric miao pxa_register_device(&pxa_device_ficp, info); 2838f58de7cSeric miao } 2848f58de7cSeric miao 2858f58de7cSeric miao struct platform_device pxa_device_rtc = { 2868f58de7cSeric miao .name = "sa1100-rtc", 2878f58de7cSeric miao .id = -1, 2888f58de7cSeric miao }; 2898f58de7cSeric miao 2908f58de7cSeric miao #ifdef CONFIG_PXA25x 2918f58de7cSeric miao 2928f58de7cSeric miao static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32); 2938f58de7cSeric miao 2948f58de7cSeric miao static struct resource pxa25x_resource_ssp[] = { 2958f58de7cSeric miao [0] = { 2968f58de7cSeric miao .start = 0x41000000, 2978f58de7cSeric miao .end = 0x4100001f, 2988f58de7cSeric miao .flags = IORESOURCE_MEM, 2998f58de7cSeric miao }, 3008f58de7cSeric miao [1] = { 3018f58de7cSeric miao .start = IRQ_SSP, 3028f58de7cSeric miao .end = IRQ_SSP, 3038f58de7cSeric miao .flags = IORESOURCE_IRQ, 3048f58de7cSeric miao }, 3058f58de7cSeric miao [2] = { 3068f58de7cSeric miao /* DRCMR for RX */ 3078f58de7cSeric miao .start = 13, 3088f58de7cSeric miao .end = 13, 3098f58de7cSeric miao .flags = IORESOURCE_DMA, 3108f58de7cSeric miao }, 3118f58de7cSeric miao [3] = { 3128f58de7cSeric miao /* DRCMR for TX */ 3138f58de7cSeric miao .start = 14, 3148f58de7cSeric miao .end = 14, 3158f58de7cSeric miao .flags = IORESOURCE_DMA, 3168f58de7cSeric miao }, 3178f58de7cSeric miao }; 3188f58de7cSeric miao 3198f58de7cSeric miao struct platform_device pxa25x_device_ssp = { 3208f58de7cSeric miao .name = "pxa25x-ssp", 3218f58de7cSeric miao .id = 0, 3228f58de7cSeric miao .dev = { 3238f58de7cSeric miao .dma_mask = &pxa25x_ssp_dma_mask, 3248f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 3258f58de7cSeric miao }, 3268f58de7cSeric miao .resource = pxa25x_resource_ssp, 3278f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa25x_resource_ssp), 3288f58de7cSeric miao }; 3298f58de7cSeric miao 3308f58de7cSeric miao static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32); 3318f58de7cSeric miao 3328f58de7cSeric miao static struct resource pxa25x_resource_nssp[] = { 3338f58de7cSeric miao [0] = { 3348f58de7cSeric miao .start = 0x41400000, 3358f58de7cSeric miao .end = 0x4140002f, 3368f58de7cSeric miao .flags = IORESOURCE_MEM, 3378f58de7cSeric miao }, 3388f58de7cSeric miao [1] = { 3398f58de7cSeric miao .start = IRQ_NSSP, 3408f58de7cSeric miao .end = IRQ_NSSP, 3418f58de7cSeric miao .flags = IORESOURCE_IRQ, 3428f58de7cSeric miao }, 3438f58de7cSeric miao [2] = { 3448f58de7cSeric miao /* DRCMR for RX */ 3458f58de7cSeric miao .start = 15, 3468f58de7cSeric miao .end = 15, 3478f58de7cSeric miao .flags = IORESOURCE_DMA, 3488f58de7cSeric miao }, 3498f58de7cSeric miao [3] = { 3508f58de7cSeric miao /* DRCMR for TX */ 3518f58de7cSeric miao .start = 16, 3528f58de7cSeric miao .end = 16, 3538f58de7cSeric miao .flags = IORESOURCE_DMA, 3548f58de7cSeric miao }, 3558f58de7cSeric miao }; 3568f58de7cSeric miao 3578f58de7cSeric miao struct platform_device pxa25x_device_nssp = { 3588f58de7cSeric miao .name = "pxa25x-nssp", 3598f58de7cSeric miao .id = 1, 3608f58de7cSeric miao .dev = { 3618f58de7cSeric miao .dma_mask = &pxa25x_nssp_dma_mask, 3628f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 3638f58de7cSeric miao }, 3648f58de7cSeric miao .resource = pxa25x_resource_nssp, 3658f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa25x_resource_nssp), 3668f58de7cSeric miao }; 3678f58de7cSeric miao 3688f58de7cSeric miao static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32); 3698f58de7cSeric miao 3708f58de7cSeric miao static struct resource pxa25x_resource_assp[] = { 3718f58de7cSeric miao [0] = { 3728f58de7cSeric miao .start = 0x41500000, 3738f58de7cSeric miao .end = 0x4150002f, 3748f58de7cSeric miao .flags = IORESOURCE_MEM, 3758f58de7cSeric miao }, 3768f58de7cSeric miao [1] = { 3778f58de7cSeric miao .start = IRQ_ASSP, 3788f58de7cSeric miao .end = IRQ_ASSP, 3798f58de7cSeric miao .flags = IORESOURCE_IRQ, 3808f58de7cSeric miao }, 3818f58de7cSeric miao [2] = { 3828f58de7cSeric miao /* DRCMR for RX */ 3838f58de7cSeric miao .start = 23, 3848f58de7cSeric miao .end = 23, 3858f58de7cSeric miao .flags = IORESOURCE_DMA, 3868f58de7cSeric miao }, 3878f58de7cSeric miao [3] = { 3888f58de7cSeric miao /* DRCMR for TX */ 3898f58de7cSeric miao .start = 24, 3908f58de7cSeric miao .end = 24, 3918f58de7cSeric miao .flags = IORESOURCE_DMA, 3928f58de7cSeric miao }, 3938f58de7cSeric miao }; 3948f58de7cSeric miao 3958f58de7cSeric miao struct platform_device pxa25x_device_assp = { 3968f58de7cSeric miao /* ASSP is basically equivalent to NSSP */ 3978f58de7cSeric miao .name = "pxa25x-nssp", 3988f58de7cSeric miao .id = 2, 3998f58de7cSeric miao .dev = { 4008f58de7cSeric miao .dma_mask = &pxa25x_assp_dma_mask, 4018f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 4028f58de7cSeric miao }, 4038f58de7cSeric miao .resource = pxa25x_resource_assp, 4048f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa25x_resource_assp), 4058f58de7cSeric miao }; 4068f58de7cSeric miao #endif /* CONFIG_PXA25x */ 4078f58de7cSeric miao 4088f58de7cSeric miao #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 4098f58de7cSeric miao 41037320980Seric miao static struct resource pxa27x_resource_keypad[] = { 41137320980Seric miao [0] = { 41237320980Seric miao .start = 0x41500000, 41337320980Seric miao .end = 0x4150004c, 41437320980Seric miao .flags = IORESOURCE_MEM, 41537320980Seric miao }, 41637320980Seric miao [1] = { 41737320980Seric miao .start = IRQ_KEYPAD, 41837320980Seric miao .end = IRQ_KEYPAD, 41937320980Seric miao .flags = IORESOURCE_IRQ, 42037320980Seric miao }, 42137320980Seric miao }; 42237320980Seric miao 42337320980Seric miao struct platform_device pxa27x_device_keypad = { 42437320980Seric miao .name = "pxa27x-keypad", 42537320980Seric miao .id = -1, 42637320980Seric miao .resource = pxa27x_resource_keypad, 42737320980Seric miao .num_resources = ARRAY_SIZE(pxa27x_resource_keypad), 42837320980Seric miao }; 42937320980Seric miao 43037320980Seric miao void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info) 43137320980Seric miao { 43237320980Seric miao pxa_register_device(&pxa27x_device_keypad, info); 43337320980Seric miao } 43437320980Seric miao 435ec68e45bSeric miao static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32); 436ec68e45bSeric miao 437ec68e45bSeric miao static struct resource pxa27x_resource_ohci[] = { 438ec68e45bSeric miao [0] = { 439ec68e45bSeric miao .start = 0x4C000000, 440ec68e45bSeric miao .end = 0x4C00ff6f, 441ec68e45bSeric miao .flags = IORESOURCE_MEM, 442ec68e45bSeric miao }, 443ec68e45bSeric miao [1] = { 444ec68e45bSeric miao .start = IRQ_USBH1, 445ec68e45bSeric miao .end = IRQ_USBH1, 446ec68e45bSeric miao .flags = IORESOURCE_IRQ, 447ec68e45bSeric miao }, 448ec68e45bSeric miao }; 449ec68e45bSeric miao 450ec68e45bSeric miao struct platform_device pxa27x_device_ohci = { 451ec68e45bSeric miao .name = "pxa27x-ohci", 452ec68e45bSeric miao .id = -1, 453ec68e45bSeric miao .dev = { 454ec68e45bSeric miao .dma_mask = &pxa27x_ohci_dma_mask, 455ec68e45bSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 456ec68e45bSeric miao }, 457ec68e45bSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_ohci), 458ec68e45bSeric miao .resource = pxa27x_resource_ohci, 459ec68e45bSeric miao }; 460ec68e45bSeric miao 461ec68e45bSeric miao void __init pxa_set_ohci_info(struct pxaohci_platform_data *info) 462ec68e45bSeric miao { 463ec68e45bSeric miao pxa_register_device(&pxa27x_device_ohci, info); 464ec68e45bSeric miao } 465ec68e45bSeric miao 4668f58de7cSeric miao static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32); 4678f58de7cSeric miao 4688f58de7cSeric miao static struct resource pxa27x_resource_ssp1[] = { 4698f58de7cSeric miao [0] = { 4708f58de7cSeric miao .start = 0x41000000, 4718f58de7cSeric miao .end = 0x4100003f, 4728f58de7cSeric miao .flags = IORESOURCE_MEM, 4738f58de7cSeric miao }, 4748f58de7cSeric miao [1] = { 4758f58de7cSeric miao .start = IRQ_SSP, 4768f58de7cSeric miao .end = IRQ_SSP, 4778f58de7cSeric miao .flags = IORESOURCE_IRQ, 4788f58de7cSeric miao }, 4798f58de7cSeric miao [2] = { 4808f58de7cSeric miao /* DRCMR for RX */ 4818f58de7cSeric miao .start = 13, 4828f58de7cSeric miao .end = 13, 4838f58de7cSeric miao .flags = IORESOURCE_DMA, 4848f58de7cSeric miao }, 4858f58de7cSeric miao [3] = { 4868f58de7cSeric miao /* DRCMR for TX */ 4878f58de7cSeric miao .start = 14, 4888f58de7cSeric miao .end = 14, 4898f58de7cSeric miao .flags = IORESOURCE_DMA, 4908f58de7cSeric miao }, 4918f58de7cSeric miao }; 4928f58de7cSeric miao 4938f58de7cSeric miao struct platform_device pxa27x_device_ssp1 = { 4948f58de7cSeric miao .name = "pxa27x-ssp", 4958f58de7cSeric miao .id = 0, 4968f58de7cSeric miao .dev = { 4978f58de7cSeric miao .dma_mask = &pxa27x_ssp1_dma_mask, 4988f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 4998f58de7cSeric miao }, 5008f58de7cSeric miao .resource = pxa27x_resource_ssp1, 5018f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1), 5028f58de7cSeric miao }; 5038f58de7cSeric miao 5048f58de7cSeric miao static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32); 5058f58de7cSeric miao 5068f58de7cSeric miao static struct resource pxa27x_resource_ssp2[] = { 5078f58de7cSeric miao [0] = { 5088f58de7cSeric miao .start = 0x41700000, 5098f58de7cSeric miao .end = 0x4170003f, 5108f58de7cSeric miao .flags = IORESOURCE_MEM, 5118f58de7cSeric miao }, 5128f58de7cSeric miao [1] = { 5138f58de7cSeric miao .start = IRQ_SSP2, 5148f58de7cSeric miao .end = IRQ_SSP2, 5158f58de7cSeric miao .flags = IORESOURCE_IRQ, 5168f58de7cSeric miao }, 5178f58de7cSeric miao [2] = { 5188f58de7cSeric miao /* DRCMR for RX */ 5198f58de7cSeric miao .start = 15, 5208f58de7cSeric miao .end = 15, 5218f58de7cSeric miao .flags = IORESOURCE_DMA, 5228f58de7cSeric miao }, 5238f58de7cSeric miao [3] = { 5248f58de7cSeric miao /* DRCMR for TX */ 5258f58de7cSeric miao .start = 16, 5268f58de7cSeric miao .end = 16, 5278f58de7cSeric miao .flags = IORESOURCE_DMA, 5288f58de7cSeric miao }, 5298f58de7cSeric miao }; 5308f58de7cSeric miao 5318f58de7cSeric miao struct platform_device pxa27x_device_ssp2 = { 5328f58de7cSeric miao .name = "pxa27x-ssp", 5338f58de7cSeric miao .id = 1, 5348f58de7cSeric miao .dev = { 5358f58de7cSeric miao .dma_mask = &pxa27x_ssp2_dma_mask, 5368f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 5378f58de7cSeric miao }, 5388f58de7cSeric miao .resource = pxa27x_resource_ssp2, 5398f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2), 5408f58de7cSeric miao }; 5418f58de7cSeric miao 5428f58de7cSeric miao static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32); 5438f58de7cSeric miao 5448f58de7cSeric miao static struct resource pxa27x_resource_ssp3[] = { 5458f58de7cSeric miao [0] = { 5468f58de7cSeric miao .start = 0x41900000, 5478f58de7cSeric miao .end = 0x4190003f, 5488f58de7cSeric miao .flags = IORESOURCE_MEM, 5498f58de7cSeric miao }, 5508f58de7cSeric miao [1] = { 5518f58de7cSeric miao .start = IRQ_SSP3, 5528f58de7cSeric miao .end = IRQ_SSP3, 5538f58de7cSeric miao .flags = IORESOURCE_IRQ, 5548f58de7cSeric miao }, 5558f58de7cSeric miao [2] = { 5568f58de7cSeric miao /* DRCMR for RX */ 5578f58de7cSeric miao .start = 66, 5588f58de7cSeric miao .end = 66, 5598f58de7cSeric miao .flags = IORESOURCE_DMA, 5608f58de7cSeric miao }, 5618f58de7cSeric miao [3] = { 5628f58de7cSeric miao /* DRCMR for TX */ 5638f58de7cSeric miao .start = 67, 5648f58de7cSeric miao .end = 67, 5658f58de7cSeric miao .flags = IORESOURCE_DMA, 5668f58de7cSeric miao }, 5678f58de7cSeric miao }; 5688f58de7cSeric miao 5698f58de7cSeric miao struct platform_device pxa27x_device_ssp3 = { 5708f58de7cSeric miao .name = "pxa27x-ssp", 5718f58de7cSeric miao .id = 2, 5728f58de7cSeric miao .dev = { 5738f58de7cSeric miao .dma_mask = &pxa27x_ssp3_dma_mask, 5748f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 5758f58de7cSeric miao }, 5768f58de7cSeric miao .resource = pxa27x_resource_ssp3, 5778f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3), 5788f58de7cSeric miao }; 5793f3acefbSGuennadi Liakhovetski 5803f3acefbSGuennadi Liakhovetski static struct resource pxa27x_resource_camera[] = { 5813f3acefbSGuennadi Liakhovetski [0] = { 5823f3acefbSGuennadi Liakhovetski .start = 0x50000000, 5833f3acefbSGuennadi Liakhovetski .end = 0x50000fff, 5843f3acefbSGuennadi Liakhovetski .flags = IORESOURCE_MEM, 5853f3acefbSGuennadi Liakhovetski }, 5863f3acefbSGuennadi Liakhovetski [1] = { 5873f3acefbSGuennadi Liakhovetski .start = IRQ_CAMERA, 5883f3acefbSGuennadi Liakhovetski .end = IRQ_CAMERA, 5893f3acefbSGuennadi Liakhovetski .flags = IORESOURCE_IRQ, 5903f3acefbSGuennadi Liakhovetski }, 5913f3acefbSGuennadi Liakhovetski }; 5923f3acefbSGuennadi Liakhovetski 5933f3acefbSGuennadi Liakhovetski static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32); 5943f3acefbSGuennadi Liakhovetski 5953f3acefbSGuennadi Liakhovetski static struct platform_device pxa27x_device_camera = { 5963f3acefbSGuennadi Liakhovetski .name = "pxa27x-camera", 5973f3acefbSGuennadi Liakhovetski .id = 0, /* This is used to put cameras on this interface */ 5983f3acefbSGuennadi Liakhovetski .dev = { 5993f3acefbSGuennadi Liakhovetski .dma_mask = &pxa27x_dma_mask_camera, 6003f3acefbSGuennadi Liakhovetski .coherent_dma_mask = 0xffffffff, 6013f3acefbSGuennadi Liakhovetski }, 6023f3acefbSGuennadi Liakhovetski .num_resources = ARRAY_SIZE(pxa27x_resource_camera), 6033f3acefbSGuennadi Liakhovetski .resource = pxa27x_resource_camera, 6043f3acefbSGuennadi Liakhovetski }; 6053f3acefbSGuennadi Liakhovetski 6063f3acefbSGuennadi Liakhovetski void __init pxa_set_camera_info(struct pxacamera_platform_data *info) 6073f3acefbSGuennadi Liakhovetski { 6083f3acefbSGuennadi Liakhovetski pxa_register_device(&pxa27x_device_camera, info); 6093f3acefbSGuennadi Liakhovetski } 6108f58de7cSeric miao #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ 6118f58de7cSeric miao 6128f58de7cSeric miao #ifdef CONFIG_PXA3xx 6138f58de7cSeric miao static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32); 6148f58de7cSeric miao 6158f58de7cSeric miao static struct resource pxa3xx_resource_ssp4[] = { 6168f58de7cSeric miao [0] = { 6178f58de7cSeric miao .start = 0x41a00000, 6188f58de7cSeric miao .end = 0x41a0003f, 6198f58de7cSeric miao .flags = IORESOURCE_MEM, 6208f58de7cSeric miao }, 6218f58de7cSeric miao [1] = { 6228f58de7cSeric miao .start = IRQ_SSP4, 6238f58de7cSeric miao .end = IRQ_SSP4, 6248f58de7cSeric miao .flags = IORESOURCE_IRQ, 6258f58de7cSeric miao }, 6268f58de7cSeric miao [2] = { 6278f58de7cSeric miao /* DRCMR for RX */ 6288f58de7cSeric miao .start = 2, 6298f58de7cSeric miao .end = 2, 6308f58de7cSeric miao .flags = IORESOURCE_DMA, 6318f58de7cSeric miao }, 6328f58de7cSeric miao [3] = { 6338f58de7cSeric miao /* DRCMR for TX */ 6348f58de7cSeric miao .start = 3, 6358f58de7cSeric miao .end = 3, 6368f58de7cSeric miao .flags = IORESOURCE_DMA, 6378f58de7cSeric miao }, 6388f58de7cSeric miao }; 6398f58de7cSeric miao 6408f58de7cSeric miao struct platform_device pxa3xx_device_ssp4 = { 6418f58de7cSeric miao /* PXA3xx SSP is basically equivalent to PXA27x */ 6428f58de7cSeric miao .name = "pxa27x-ssp", 6438f58de7cSeric miao .id = 3, 6448f58de7cSeric miao .dev = { 6458f58de7cSeric miao .dma_mask = &pxa3xx_ssp4_dma_mask, 6468f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 6478f58de7cSeric miao }, 6488f58de7cSeric miao .resource = pxa3xx_resource_ssp4, 6498f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4), 6508f58de7cSeric miao }; 6518d33b055SBridge Wu 6528d33b055SBridge Wu static struct resource pxa3xx_resources_mci2[] = { 6538d33b055SBridge Wu [0] = { 6548d33b055SBridge Wu .start = 0x42000000, 6558d33b055SBridge Wu .end = 0x42000fff, 6568d33b055SBridge Wu .flags = IORESOURCE_MEM, 6578d33b055SBridge Wu }, 6588d33b055SBridge Wu [1] = { 6598d33b055SBridge Wu .start = IRQ_MMC2, 6608d33b055SBridge Wu .end = IRQ_MMC2, 6618d33b055SBridge Wu .flags = IORESOURCE_IRQ, 6628d33b055SBridge Wu }, 6638d33b055SBridge Wu [2] = { 6648d33b055SBridge Wu .start = 93, 6658d33b055SBridge Wu .end = 93, 6668d33b055SBridge Wu .flags = IORESOURCE_DMA, 6678d33b055SBridge Wu }, 6688d33b055SBridge Wu [3] = { 6698d33b055SBridge Wu .start = 94, 6708d33b055SBridge Wu .end = 94, 6718d33b055SBridge Wu .flags = IORESOURCE_DMA, 6728d33b055SBridge Wu }, 6738d33b055SBridge Wu }; 6748d33b055SBridge Wu 6758d33b055SBridge Wu struct platform_device pxa3xx_device_mci2 = { 6768d33b055SBridge Wu .name = "pxa2xx-mci", 6778d33b055SBridge Wu .id = 1, 6788d33b055SBridge Wu .dev = { 6798d33b055SBridge Wu .dma_mask = &pxamci_dmamask, 6808d33b055SBridge Wu .coherent_dma_mask = 0xffffffff, 6818d33b055SBridge Wu }, 6828d33b055SBridge Wu .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2), 6838d33b055SBridge Wu .resource = pxa3xx_resources_mci2, 6848d33b055SBridge Wu }; 6858d33b055SBridge Wu 6868d33b055SBridge Wu void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info) 6878d33b055SBridge Wu { 6888d33b055SBridge Wu pxa_register_device(&pxa3xx_device_mci2, info); 6898d33b055SBridge Wu } 6908d33b055SBridge Wu 6915a1f21b1SBridge Wu static struct resource pxa3xx_resources_mci3[] = { 6925a1f21b1SBridge Wu [0] = { 6935a1f21b1SBridge Wu .start = 0x42500000, 6945a1f21b1SBridge Wu .end = 0x42500fff, 6955a1f21b1SBridge Wu .flags = IORESOURCE_MEM, 6965a1f21b1SBridge Wu }, 6975a1f21b1SBridge Wu [1] = { 6985a1f21b1SBridge Wu .start = IRQ_MMC3, 6995a1f21b1SBridge Wu .end = IRQ_MMC3, 7005a1f21b1SBridge Wu .flags = IORESOURCE_IRQ, 7015a1f21b1SBridge Wu }, 7025a1f21b1SBridge Wu [2] = { 7035a1f21b1SBridge Wu .start = 100, 7045a1f21b1SBridge Wu .end = 100, 7055a1f21b1SBridge Wu .flags = IORESOURCE_DMA, 7065a1f21b1SBridge Wu }, 7075a1f21b1SBridge Wu [3] = { 7085a1f21b1SBridge Wu .start = 101, 7095a1f21b1SBridge Wu .end = 101, 7105a1f21b1SBridge Wu .flags = IORESOURCE_DMA, 7115a1f21b1SBridge Wu }, 7125a1f21b1SBridge Wu }; 7135a1f21b1SBridge Wu 7145a1f21b1SBridge Wu struct platform_device pxa3xx_device_mci3 = { 7155a1f21b1SBridge Wu .name = "pxa2xx-mci", 7165a1f21b1SBridge Wu .id = 2, 7175a1f21b1SBridge Wu .dev = { 7185a1f21b1SBridge Wu .dma_mask = &pxamci_dmamask, 7195a1f21b1SBridge Wu .coherent_dma_mask = 0xffffffff, 7205a1f21b1SBridge Wu }, 7215a1f21b1SBridge Wu .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3), 7225a1f21b1SBridge Wu .resource = pxa3xx_resources_mci3, 7235a1f21b1SBridge Wu }; 7245a1f21b1SBridge Wu 7255a1f21b1SBridge Wu void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info) 7265a1f21b1SBridge Wu { 7275a1f21b1SBridge Wu pxa_register_device(&pxa3xx_device_mci3, info); 7285a1f21b1SBridge Wu } 7295a1f21b1SBridge Wu 7308f58de7cSeric miao #endif /* CONFIG_PXA3xx */ 731