xref: /linux/arch/arm/mach-pxa/devices.c (revision b24413180f5600bcb3bb70fbed5cf186b60864bd)
1*b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
28f58de7cSeric miao #include <linux/module.h>
38f58de7cSeric miao #include <linux/kernel.h>
48f58de7cSeric miao #include <linux/init.h>
58f58de7cSeric miao #include <linux/platform_device.h>
68f58de7cSeric miao #include <linux/dma-mapping.h>
78348c259SSebastian Andrzej Siewior #include <linux/spi/pxa2xx_spi.h>
8b459396eSSebastian Andrzej Siewior #include <linux/i2c/pxa-i2c.h>
98f58de7cSeric miao 
104c25c5d2SArnd Bergmann #include "udc.h"
11293b2da1SArnd Bergmann #include <linux/platform_data/usb-pxa3xx-ulpi.h>
12293b2da1SArnd Bergmann #include <linux/platform_data/video-pxafb.h>
13293b2da1SArnd Bergmann #include <linux/platform_data/mmc-pxamci.h>
14293b2da1SArnd Bergmann #include <linux/platform_data/irda-pxaficp.h>
154e611091SRob Herring #include <mach/irqs.h>
16293b2da1SArnd Bergmann #include <linux/platform_data/usb-ohci-pxa27x.h>
17293b2da1SArnd Bergmann #include <linux/platform_data/keypad-pxa27x.h>
18a71daaa1SMauro Carvalho Chehab #include <linux/platform_data/media/camera-pxa.h>
19a09e64fbSRussell King #include <mach/audio.h>
2075e874c6SEric Miao #include <mach/hardware.h>
214be0856fSRobert Jarzmik #include <linux/platform_data/mmp_dma.h>
22293b2da1SArnd Bergmann #include <linux/platform_data/mtd-nand-pxa3xx.h>
238f58de7cSeric miao 
248f58de7cSeric miao #include "devices.h"
25bc3a5959SPhilipp Zabel #include "generic.h"
268f58de7cSeric miao 
278f58de7cSeric miao void __init pxa_register_device(struct platform_device *dev, void *data)
288f58de7cSeric miao {
298f58de7cSeric miao 	int ret;
308f58de7cSeric miao 
318f58de7cSeric miao 	dev->dev.platform_data = data;
328f58de7cSeric miao 
338f58de7cSeric miao 	ret = platform_device_register(dev);
348f58de7cSeric miao 	if (ret)
358f58de7cSeric miao 		dev_err(&dev->dev, "unable to register device: %d\n", ret);
368f58de7cSeric miao }
378f58de7cSeric miao 
3809a5358dSEric Miao static struct resource pxa_resource_pmu = {
3909a5358dSEric Miao 	.start	= IRQ_PMU,
4009a5358dSEric Miao 	.end	= IRQ_PMU,
4109a5358dSEric Miao 	.flags	= IORESOURCE_IRQ,
4209a5358dSEric Miao };
4309a5358dSEric Miao 
4409a5358dSEric Miao struct platform_device pxa_device_pmu = {
45f9eff219SMark Rutland 	.name		= "xscale-pmu",
46df3d17e0SSudeep KarkadaNagesha 	.id		= -1,
4709a5358dSEric Miao 	.resource	= &pxa_resource_pmu,
4809a5358dSEric Miao 	.num_resources	= 1,
4909a5358dSEric Miao };
5009a5358dSEric Miao 
518f58de7cSeric miao static struct resource pxamci_resources[] = {
528f58de7cSeric miao 	[0] = {
538f58de7cSeric miao 		.start	= 0x41100000,
548f58de7cSeric miao 		.end	= 0x41100fff,
558f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
568f58de7cSeric miao 	},
578f58de7cSeric miao 	[1] = {
588f58de7cSeric miao 		.start	= IRQ_MMC,
598f58de7cSeric miao 		.end	= IRQ_MMC,
608f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
618f58de7cSeric miao 	},
628f58de7cSeric miao 	[2] = {
638f58de7cSeric miao 		.start	= 21,
648f58de7cSeric miao 		.end	= 21,
658f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
668f58de7cSeric miao 	},
678f58de7cSeric miao 	[3] = {
688f58de7cSeric miao 		.start	= 22,
698f58de7cSeric miao 		.end	= 22,
708f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
718f58de7cSeric miao 	},
728f58de7cSeric miao };
738f58de7cSeric miao 
748f58de7cSeric miao static u64 pxamci_dmamask = 0xffffffffUL;
758f58de7cSeric miao 
768f58de7cSeric miao struct platform_device pxa_device_mci = {
778f58de7cSeric miao 	.name		= "pxa2xx-mci",
78fafc9d3fSBridge Wu 	.id		= 0,
798f58de7cSeric miao 	.dev		= {
808f58de7cSeric miao 		.dma_mask = &pxamci_dmamask,
818f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
828f58de7cSeric miao 	},
838f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxamci_resources),
848f58de7cSeric miao 	.resource	= pxamci_resources,
858f58de7cSeric miao };
868f58de7cSeric miao 
878f58de7cSeric miao void __init pxa_set_mci_info(struct pxamci_platform_data *info)
888f58de7cSeric miao {
898f58de7cSeric miao 	pxa_register_device(&pxa_device_mci, info);
908f58de7cSeric miao }
918f58de7cSeric miao 
928f58de7cSeric miao 
931257629bSPhilipp Zabel static struct pxa2xx_udc_mach_info pxa_udc_info = {
941257629bSPhilipp Zabel 	.gpio_pullup = -1,
951257629bSPhilipp Zabel };
968f58de7cSeric miao 
978f58de7cSeric miao void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
988f58de7cSeric miao {
998f58de7cSeric miao 	memcpy(&pxa_udc_info, info, sizeof *info);
1008f58de7cSeric miao }
1018f58de7cSeric miao 
1028f58de7cSeric miao static struct resource pxa2xx_udc_resources[] = {
1038f58de7cSeric miao 	[0] = {
1048f58de7cSeric miao 		.start	= 0x40600000,
1058f58de7cSeric miao 		.end	= 0x4060ffff,
1068f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1078f58de7cSeric miao 	},
1088f58de7cSeric miao 	[1] = {
1098f58de7cSeric miao 		.start	= IRQ_USB,
1108f58de7cSeric miao 		.end	= IRQ_USB,
1118f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1128f58de7cSeric miao 	},
1138f58de7cSeric miao };
1148f58de7cSeric miao 
1158f58de7cSeric miao static u64 udc_dma_mask = ~(u32)0;
1168f58de7cSeric miao 
1177a857620SPhilipp Zabel struct platform_device pxa25x_device_udc = {
1187a857620SPhilipp Zabel 	.name		= "pxa25x-udc",
1197a857620SPhilipp Zabel 	.id		= -1,
1207a857620SPhilipp Zabel 	.resource	= pxa2xx_udc_resources,
1217a857620SPhilipp Zabel 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
1227a857620SPhilipp Zabel 	.dev		=  {
1237a857620SPhilipp Zabel 		.platform_data	= &pxa_udc_info,
1247a857620SPhilipp Zabel 		.dma_mask	= &udc_dma_mask,
1257a857620SPhilipp Zabel 	}
1267a857620SPhilipp Zabel };
1277a857620SPhilipp Zabel 
1287a857620SPhilipp Zabel struct platform_device pxa27x_device_udc = {
1297a857620SPhilipp Zabel 	.name		= "pxa27x-udc",
1308f58de7cSeric miao 	.id		= -1,
1318f58de7cSeric miao 	.resource	= pxa2xx_udc_resources,
1328f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
1338f58de7cSeric miao 	.dev		=  {
1348f58de7cSeric miao 		.platform_data	= &pxa_udc_info,
1358f58de7cSeric miao 		.dma_mask	= &udc_dma_mask,
1368f58de7cSeric miao 	}
1378f58de7cSeric miao };
1388f58de7cSeric miao 
13969f22be7SIgor Grinberg #ifdef CONFIG_PXA3xx
14069f22be7SIgor Grinberg static struct resource pxa3xx_u2d_resources[] = {
14169f22be7SIgor Grinberg 	[0] = {
14269f22be7SIgor Grinberg 		.start	= 0x54100000,
14369f22be7SIgor Grinberg 		.end	= 0x54100fff,
14469f22be7SIgor Grinberg 		.flags	= IORESOURCE_MEM,
14569f22be7SIgor Grinberg 	},
14669f22be7SIgor Grinberg 	[1] = {
14769f22be7SIgor Grinberg 		.start	= IRQ_USB2,
14869f22be7SIgor Grinberg 		.end	= IRQ_USB2,
14969f22be7SIgor Grinberg 		.flags	= IORESOURCE_IRQ,
15069f22be7SIgor Grinberg 	},
15169f22be7SIgor Grinberg };
15269f22be7SIgor Grinberg 
15369f22be7SIgor Grinberg struct platform_device pxa3xx_device_u2d = {
15469f22be7SIgor Grinberg 	.name		= "pxa3xx-u2d",
15569f22be7SIgor Grinberg 	.id		= -1,
15669f22be7SIgor Grinberg 	.resource	= pxa3xx_u2d_resources,
15769f22be7SIgor Grinberg 	.num_resources	= ARRAY_SIZE(pxa3xx_u2d_resources),
15869f22be7SIgor Grinberg };
15969f22be7SIgor Grinberg 
16069f22be7SIgor Grinberg void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
16169f22be7SIgor Grinberg {
16269f22be7SIgor Grinberg 	pxa_register_device(&pxa3xx_device_u2d, info);
16369f22be7SIgor Grinberg }
16469f22be7SIgor Grinberg #endif /* CONFIG_PXA3xx */
16569f22be7SIgor Grinberg 
1668f58de7cSeric miao static struct resource pxafb_resources[] = {
1678f58de7cSeric miao 	[0] = {
1688f58de7cSeric miao 		.start	= 0x44000000,
1698f58de7cSeric miao 		.end	= 0x4400ffff,
1708f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1718f58de7cSeric miao 	},
1728f58de7cSeric miao 	[1] = {
1738f58de7cSeric miao 		.start	= IRQ_LCD,
1748f58de7cSeric miao 		.end	= IRQ_LCD,
1758f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1768f58de7cSeric miao 	},
1778f58de7cSeric miao };
1788f58de7cSeric miao 
1798f58de7cSeric miao static u64 fb_dma_mask = ~(u64)0;
1808f58de7cSeric miao 
1818f58de7cSeric miao struct platform_device pxa_device_fb = {
1828f58de7cSeric miao 	.name		= "pxa2xx-fb",
1838f58de7cSeric miao 	.id		= -1,
1848f58de7cSeric miao 	.dev		= {
1858f58de7cSeric miao 		.dma_mask	= &fb_dma_mask,
1868f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
1878f58de7cSeric miao 	},
1888f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxafb_resources),
1898f58de7cSeric miao 	.resource	= pxafb_resources,
1908f58de7cSeric miao };
1918f58de7cSeric miao 
1924321e1a1SRussell King - ARM Linux void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
1938f58de7cSeric miao {
1944321e1a1SRussell King - ARM Linux 	pxa_device_fb.dev.parent = parent;
1958f58de7cSeric miao 	pxa_register_device(&pxa_device_fb, info);
1968f58de7cSeric miao }
1978f58de7cSeric miao 
1988f58de7cSeric miao static struct resource pxa_resource_ffuart[] = {
1998f58de7cSeric miao 	{
20002f65262SEric Miao 		.start	= 0x40100000,
20102f65262SEric Miao 		.end	= 0x40100023,
2028f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2038f58de7cSeric miao 	}, {
2048f58de7cSeric miao 		.start	= IRQ_FFUART,
2058f58de7cSeric miao 		.end	= IRQ_FFUART,
2068f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2078f58de7cSeric miao 	}
2088f58de7cSeric miao };
2098f58de7cSeric miao 
2108f58de7cSeric miao struct platform_device pxa_device_ffuart = {
2118f58de7cSeric miao 	.name		= "pxa2xx-uart",
2128f58de7cSeric miao 	.id		= 0,
2138f58de7cSeric miao 	.resource	= pxa_resource_ffuart,
2148f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_ffuart),
2158f58de7cSeric miao };
2168f58de7cSeric miao 
217cc155c6fSRussell King void __init pxa_set_ffuart_info(void *info)
218cc155c6fSRussell King {
219cc155c6fSRussell King 	pxa_register_device(&pxa_device_ffuart, info);
220cc155c6fSRussell King }
221cc155c6fSRussell King 
2228f58de7cSeric miao static struct resource pxa_resource_btuart[] = {
2238f58de7cSeric miao 	{
22402f65262SEric Miao 		.start	= 0x40200000,
22502f65262SEric Miao 		.end	= 0x40200023,
2268f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2278f58de7cSeric miao 	}, {
2288f58de7cSeric miao 		.start	= IRQ_BTUART,
2298f58de7cSeric miao 		.end	= IRQ_BTUART,
2308f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2318f58de7cSeric miao 	}
2328f58de7cSeric miao };
2338f58de7cSeric miao 
2348f58de7cSeric miao struct platform_device pxa_device_btuart = {
2358f58de7cSeric miao 	.name		= "pxa2xx-uart",
2368f58de7cSeric miao 	.id		= 1,
2378f58de7cSeric miao 	.resource	= pxa_resource_btuart,
2388f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_btuart),
2398f58de7cSeric miao };
2408f58de7cSeric miao 
241cc155c6fSRussell King void __init pxa_set_btuart_info(void *info)
242cc155c6fSRussell King {
243cc155c6fSRussell King 	pxa_register_device(&pxa_device_btuart, info);
244cc155c6fSRussell King }
245cc155c6fSRussell King 
2468f58de7cSeric miao static struct resource pxa_resource_stuart[] = {
2478f58de7cSeric miao 	{
24802f65262SEric Miao 		.start	= 0x40700000,
24902f65262SEric Miao 		.end	= 0x40700023,
2508f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2518f58de7cSeric miao 	}, {
2528f58de7cSeric miao 		.start	= IRQ_STUART,
2538f58de7cSeric miao 		.end	= IRQ_STUART,
2548f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2558f58de7cSeric miao 	}
2568f58de7cSeric miao };
2578f58de7cSeric miao 
2588f58de7cSeric miao struct platform_device pxa_device_stuart = {
2598f58de7cSeric miao 	.name		= "pxa2xx-uart",
2608f58de7cSeric miao 	.id		= 2,
2618f58de7cSeric miao 	.resource	= pxa_resource_stuart,
2628f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_stuart),
2638f58de7cSeric miao };
2648f58de7cSeric miao 
265cc155c6fSRussell King void __init pxa_set_stuart_info(void *info)
266cc155c6fSRussell King {
267cc155c6fSRussell King 	pxa_register_device(&pxa_device_stuart, info);
268cc155c6fSRussell King }
269cc155c6fSRussell King 
2708f58de7cSeric miao static struct resource pxa_resource_hwuart[] = {
2718f58de7cSeric miao 	{
27202f65262SEric Miao 		.start	= 0x41600000,
27302f65262SEric Miao 		.end	= 0x4160002F,
2748f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2758f58de7cSeric miao 	}, {
2768f58de7cSeric miao 		.start	= IRQ_HWUART,
2778f58de7cSeric miao 		.end	= IRQ_HWUART,
2788f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2798f58de7cSeric miao 	}
2808f58de7cSeric miao };
2818f58de7cSeric miao 
2828f58de7cSeric miao struct platform_device pxa_device_hwuart = {
2838f58de7cSeric miao 	.name		= "pxa2xx-uart",
2848f58de7cSeric miao 	.id		= 3,
2858f58de7cSeric miao 	.resource	= pxa_resource_hwuart,
2868f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
2878f58de7cSeric miao };
2888f58de7cSeric miao 
289cc155c6fSRussell King void __init pxa_set_hwuart_info(void *info)
290cc155c6fSRussell King {
291cc155c6fSRussell King 	if (cpu_is_pxa255())
292cc155c6fSRussell King 		pxa_register_device(&pxa_device_hwuart, info);
293cc155c6fSRussell King 	else
294cc155c6fSRussell King 		pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
295cc155c6fSRussell King }
296cc155c6fSRussell King 
2978f58de7cSeric miao static struct resource pxai2c_resources[] = {
2988f58de7cSeric miao 	{
2998f58de7cSeric miao 		.start	= 0x40301680,
3008f58de7cSeric miao 		.end	= 0x403016a3,
3018f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3028f58de7cSeric miao 	}, {
3038f58de7cSeric miao 		.start	= IRQ_I2C,
3048f58de7cSeric miao 		.end	= IRQ_I2C,
3058f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3068f58de7cSeric miao 	},
3078f58de7cSeric miao };
3088f58de7cSeric miao 
3098f58de7cSeric miao struct platform_device pxa_device_i2c = {
3108f58de7cSeric miao 	.name		= "pxa2xx-i2c",
3118f58de7cSeric miao 	.id		= 0,
3128f58de7cSeric miao 	.resource	= pxai2c_resources,
3138f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2c_resources),
3148f58de7cSeric miao };
3158f58de7cSeric miao 
3168f58de7cSeric miao void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
3178f58de7cSeric miao {
3188f58de7cSeric miao 	pxa_register_device(&pxa_device_i2c, info);
3198f58de7cSeric miao }
3208f58de7cSeric miao 
32199464293SEric Miao #ifdef CONFIG_PXA27x
32299464293SEric Miao static struct resource pxa27x_resources_i2c_power[] = {
32399464293SEric Miao 	{
32499464293SEric Miao 		.start	= 0x40f00180,
32599464293SEric Miao 		.end	= 0x40f001a3,
32699464293SEric Miao 		.flags	= IORESOURCE_MEM,
32799464293SEric Miao 	}, {
32899464293SEric Miao 		.start	= IRQ_PWRI2C,
32999464293SEric Miao 		.end	= IRQ_PWRI2C,
33099464293SEric Miao 		.flags	= IORESOURCE_IRQ,
33199464293SEric Miao 	},
33299464293SEric Miao };
33399464293SEric Miao 
33499464293SEric Miao struct platform_device pxa27x_device_i2c_power = {
33599464293SEric Miao 	.name		= "pxa2xx-i2c",
33699464293SEric Miao 	.id		= 1,
33799464293SEric Miao 	.resource	= pxa27x_resources_i2c_power,
33899464293SEric Miao 	.num_resources	= ARRAY_SIZE(pxa27x_resources_i2c_power),
33999464293SEric Miao };
34099464293SEric Miao #endif
34199464293SEric Miao 
3428f58de7cSeric miao static struct resource pxai2s_resources[] = {
3438f58de7cSeric miao 	{
3448f58de7cSeric miao 		.start	= 0x40400000,
3458f58de7cSeric miao 		.end	= 0x40400083,
3468f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3478f58de7cSeric miao 	}, {
3488f58de7cSeric miao 		.start	= IRQ_I2S,
3498f58de7cSeric miao 		.end	= IRQ_I2S,
3508f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3518f58de7cSeric miao 	},
3528f58de7cSeric miao };
3538f58de7cSeric miao 
3548f58de7cSeric miao struct platform_device pxa_device_i2s = {
3558f58de7cSeric miao 	.name		= "pxa2xx-i2s",
3568f58de7cSeric miao 	.id		= -1,
3578f58de7cSeric miao 	.resource	= pxai2s_resources,
3588f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2s_resources),
3598f58de7cSeric miao };
3608f58de7cSeric miao 
361f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp1 = {
362f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
363f0fba2adSLiam Girdwood 	.id		= 0,
364f0fba2adSLiam Girdwood };
365f0fba2adSLiam Girdwood 
366f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp2= {
367f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
368f0fba2adSLiam Girdwood 	.id		= 1,
369f0fba2adSLiam Girdwood };
370f0fba2adSLiam Girdwood 
371f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp3 = {
372f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
373f0fba2adSLiam Girdwood 	.id		= 2,
374f0fba2adSLiam Girdwood };
375f0fba2adSLiam Girdwood 
376f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp4 = {
377f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
378f0fba2adSLiam Girdwood 	.id		= 3,
379f0fba2adSLiam Girdwood };
380f0fba2adSLiam Girdwood 
381f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_platform = {
382f0fba2adSLiam Girdwood 	.name		= "pxa-pcm-audio",
383f0fba2adSLiam Girdwood 	.id		= -1,
384f0fba2adSLiam Girdwood };
385f0fba2adSLiam Girdwood 
3868f58de7cSeric miao static u64 pxaficp_dmamask = ~(u32)0;
3878f58de7cSeric miao 
388121f3f9bSRob Herring static struct resource pxa_ir_resources[] = {
389121f3f9bSRob Herring 	[0] = {
390121f3f9bSRob Herring 		.start  = IRQ_STUART,
391121f3f9bSRob Herring 		.end    = IRQ_STUART,
392121f3f9bSRob Herring 		.flags  = IORESOURCE_IRQ,
393121f3f9bSRob Herring 	},
394121f3f9bSRob Herring 	[1] = {
395121f3f9bSRob Herring 		.start  = IRQ_ICP,
396121f3f9bSRob Herring 		.end    = IRQ_ICP,
397121f3f9bSRob Herring 		.flags  = IORESOURCE_IRQ,
398121f3f9bSRob Herring 	},
39948a629daSRobert Jarzmik 	[3] = {
40048a629daSRobert Jarzmik 		.start  = 0x40800000,
40148a629daSRobert Jarzmik 		.end	= 0x4080001b,
40248a629daSRobert Jarzmik 		.flags  = IORESOURCE_MEM,
40348a629daSRobert Jarzmik 	},
40448a629daSRobert Jarzmik 	[4] = {
40548a629daSRobert Jarzmik 		.start  = 0x40700000,
40648a629daSRobert Jarzmik 		.end	= 0x40700023,
40748a629daSRobert Jarzmik 		.flags  = IORESOURCE_MEM,
40848a629daSRobert Jarzmik 	},
40948a629daSRobert Jarzmik 	[5] = {
41048a629daSRobert Jarzmik 		.start  = 17,
41148a629daSRobert Jarzmik 		.end	= 17,
41248a629daSRobert Jarzmik 		.flags  = IORESOURCE_DMA,
41348a629daSRobert Jarzmik 	},
41448a629daSRobert Jarzmik 	[6] = {
41548a629daSRobert Jarzmik 		.start  = 18,
41648a629daSRobert Jarzmik 		.end	= 18,
41748a629daSRobert Jarzmik 		.flags  = IORESOURCE_DMA,
41848a629daSRobert Jarzmik 	},
419121f3f9bSRob Herring };
420121f3f9bSRob Herring 
4218f58de7cSeric miao struct platform_device pxa_device_ficp = {
4228f58de7cSeric miao 	.name		= "pxa2xx-ir",
4238f58de7cSeric miao 	.id		= -1,
424121f3f9bSRob Herring 	.num_resources	= ARRAY_SIZE(pxa_ir_resources),
425121f3f9bSRob Herring 	.resource	= pxa_ir_resources,
4268f58de7cSeric miao 	.dev		= {
4278f58de7cSeric miao 		.dma_mask = &pxaficp_dmamask,
4288f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
4298f58de7cSeric miao 	},
4308f58de7cSeric miao };
4318f58de7cSeric miao 
4328f58de7cSeric miao void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
4338f58de7cSeric miao {
4348f58de7cSeric miao 	pxa_register_device(&pxa_device_ficp, info);
4358f58de7cSeric miao }
4368f58de7cSeric miao 
43772493146SRobert Jarzmik static struct resource pxa_rtc_resources[] = {
43872493146SRobert Jarzmik 	[0] = {
43972493146SRobert Jarzmik 		.start  = 0x40900000,
44072493146SRobert Jarzmik 		.end	= 0x40900000 + 0x3b,
44172493146SRobert Jarzmik 		.flags  = IORESOURCE_MEM,
44272493146SRobert Jarzmik 	},
44372493146SRobert Jarzmik 	[1] = {
44472493146SRobert Jarzmik 		.start  = IRQ_RTC1Hz,
44572493146SRobert Jarzmik 		.end    = IRQ_RTC1Hz,
4463888c090SHaojian Zhuang 		.name	= "rtc 1Hz",
44772493146SRobert Jarzmik 		.flags  = IORESOURCE_IRQ,
44872493146SRobert Jarzmik 	},
44972493146SRobert Jarzmik 	[2] = {
45072493146SRobert Jarzmik 		.start  = IRQ_RTCAlrm,
45172493146SRobert Jarzmik 		.end    = IRQ_RTCAlrm,
4523888c090SHaojian Zhuang 		.name	= "rtc alarm",
45372493146SRobert Jarzmik 		.flags  = IORESOURCE_IRQ,
45472493146SRobert Jarzmik 	},
45572493146SRobert Jarzmik };
45672493146SRobert Jarzmik 
45772493146SRobert Jarzmik struct platform_device pxa_device_rtc = {
45872493146SRobert Jarzmik 	.name		= "pxa-rtc",
45972493146SRobert Jarzmik 	.id		= -1,
46072493146SRobert Jarzmik 	.num_resources  = ARRAY_SIZE(pxa_rtc_resources),
46172493146SRobert Jarzmik 	.resource       = pxa_rtc_resources,
46272493146SRobert Jarzmik };
46372493146SRobert Jarzmik 
4643888c090SHaojian Zhuang struct platform_device sa1100_device_rtc = {
4653888c090SHaojian Zhuang 	.name		= "sa1100-rtc",
4663888c090SHaojian Zhuang 	.id		= -1,
4672c4fabecSRob Herring 	.num_resources  = ARRAY_SIZE(pxa_rtc_resources),
4682c4fabecSRob Herring 	.resource       = pxa_rtc_resources,
4693888c090SHaojian Zhuang };
4703888c090SHaojian Zhuang 
4719f19d638SMark Brown static struct resource pxa_ac97_resources[] = {
4729f19d638SMark Brown 	[0] = {
4739f19d638SMark Brown 		.start  = 0x40500000,
4749f19d638SMark Brown 		.end	= 0x40500000 + 0xfff,
4759f19d638SMark Brown 		.flags  = IORESOURCE_MEM,
4769f19d638SMark Brown 	},
4779f19d638SMark Brown 	[1] = {
4789f19d638SMark Brown 		.start  = IRQ_AC97,
4799f19d638SMark Brown 		.end    = IRQ_AC97,
4809f19d638SMark Brown 		.flags  = IORESOURCE_IRQ,
4819f19d638SMark Brown 	},
4829f19d638SMark Brown };
4839f19d638SMark Brown 
4849f19d638SMark Brown static u64 pxa_ac97_dmamask = 0xffffffffUL;
4859f19d638SMark Brown 
4869f19d638SMark Brown struct platform_device pxa_device_ac97 = {
4879f19d638SMark Brown 	.name           = "pxa2xx-ac97",
4889f19d638SMark Brown 	.id             = -1,
4899f19d638SMark Brown 	.dev            = {
4909f19d638SMark Brown 		.dma_mask = &pxa_ac97_dmamask,
4919f19d638SMark Brown 		.coherent_dma_mask = 0xffffffff,
4929f19d638SMark Brown 	},
4939f19d638SMark Brown 	.num_resources  = ARRAY_SIZE(pxa_ac97_resources),
4949f19d638SMark Brown 	.resource       = pxa_ac97_resources,
4959f19d638SMark Brown };
4969f19d638SMark Brown 
4979f19d638SMark Brown void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
4989f19d638SMark Brown {
4999f19d638SMark Brown 	pxa_register_device(&pxa_device_ac97, ops);
5009f19d638SMark Brown }
5019f19d638SMark Brown 
5028f58de7cSeric miao #ifdef CONFIG_PXA25x
5038f58de7cSeric miao 
50475540c1aSeric miao static struct resource pxa25x_resource_pwm0[] = {
50575540c1aSeric miao 	[0] = {
50675540c1aSeric miao 		.start	= 0x40b00000,
50775540c1aSeric miao 		.end	= 0x40b0000f,
50875540c1aSeric miao 		.flags	= IORESOURCE_MEM,
50975540c1aSeric miao 	},
51075540c1aSeric miao };
51175540c1aSeric miao 
51275540c1aSeric miao struct platform_device pxa25x_device_pwm0 = {
51375540c1aSeric miao 	.name		= "pxa25x-pwm",
51475540c1aSeric miao 	.id		= 0,
51575540c1aSeric miao 	.resource	= pxa25x_resource_pwm0,
51675540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm0),
51775540c1aSeric miao };
51875540c1aSeric miao 
51975540c1aSeric miao static struct resource pxa25x_resource_pwm1[] = {
52075540c1aSeric miao 	[0] = {
52175540c1aSeric miao 		.start	= 0x40c00000,
52275540c1aSeric miao 		.end	= 0x40c0000f,
52375540c1aSeric miao 		.flags	= IORESOURCE_MEM,
52475540c1aSeric miao 	},
52575540c1aSeric miao };
52675540c1aSeric miao 
52775540c1aSeric miao struct platform_device pxa25x_device_pwm1 = {
52875540c1aSeric miao 	.name		= "pxa25x-pwm",
52975540c1aSeric miao 	.id		= 1,
53075540c1aSeric miao 	.resource	= pxa25x_resource_pwm1,
53175540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm1),
53275540c1aSeric miao };
53375540c1aSeric miao 
5348f58de7cSeric miao static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
5358f58de7cSeric miao 
5368f58de7cSeric miao static struct resource pxa25x_resource_ssp[] = {
5378f58de7cSeric miao 	[0] = {
5388f58de7cSeric miao 		.start	= 0x41000000,
5398f58de7cSeric miao 		.end	= 0x4100001f,
5408f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5418f58de7cSeric miao 	},
5428f58de7cSeric miao 	[1] = {
5438f58de7cSeric miao 		.start	= IRQ_SSP,
5448f58de7cSeric miao 		.end	= IRQ_SSP,
5458f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5468f58de7cSeric miao 	},
5478f58de7cSeric miao 	[2] = {
5488f58de7cSeric miao 		/* DRCMR for RX */
5498f58de7cSeric miao 		.start	= 13,
5508f58de7cSeric miao 		.end	= 13,
5518f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5528f58de7cSeric miao 	},
5538f58de7cSeric miao 	[3] = {
5548f58de7cSeric miao 		/* DRCMR for TX */
5558f58de7cSeric miao 		.start	= 14,
5568f58de7cSeric miao 		.end	= 14,
5578f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5588f58de7cSeric miao 	},
5598f58de7cSeric miao };
5608f58de7cSeric miao 
5618f58de7cSeric miao struct platform_device pxa25x_device_ssp = {
5628f58de7cSeric miao 	.name		= "pxa25x-ssp",
5638f58de7cSeric miao 	.id		= 0,
5648f58de7cSeric miao 	.dev		= {
5658f58de7cSeric miao 		.dma_mask = &pxa25x_ssp_dma_mask,
5668f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
5678f58de7cSeric miao 	},
5688f58de7cSeric miao 	.resource	= pxa25x_resource_ssp,
5698f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_ssp),
5708f58de7cSeric miao };
5718f58de7cSeric miao 
5728f58de7cSeric miao static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
5738f58de7cSeric miao 
5748f58de7cSeric miao static struct resource pxa25x_resource_nssp[] = {
5758f58de7cSeric miao 	[0] = {
5768f58de7cSeric miao 		.start	= 0x41400000,
5778f58de7cSeric miao 		.end	= 0x4140002f,
5788f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5798f58de7cSeric miao 	},
5808f58de7cSeric miao 	[1] = {
5818f58de7cSeric miao 		.start	= IRQ_NSSP,
5828f58de7cSeric miao 		.end	= IRQ_NSSP,
5838f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5848f58de7cSeric miao 	},
5858f58de7cSeric miao 	[2] = {
5868f58de7cSeric miao 		/* DRCMR for RX */
5878f58de7cSeric miao 		.start	= 15,
5888f58de7cSeric miao 		.end	= 15,
5898f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5908f58de7cSeric miao 	},
5918f58de7cSeric miao 	[3] = {
5928f58de7cSeric miao 		/* DRCMR for TX */
5938f58de7cSeric miao 		.start	= 16,
5948f58de7cSeric miao 		.end	= 16,
5958f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5968f58de7cSeric miao 	},
5978f58de7cSeric miao };
5988f58de7cSeric miao 
5998f58de7cSeric miao struct platform_device pxa25x_device_nssp = {
6008f58de7cSeric miao 	.name		= "pxa25x-nssp",
6018f58de7cSeric miao 	.id		= 1,
6028f58de7cSeric miao 	.dev		= {
6038f58de7cSeric miao 		.dma_mask = &pxa25x_nssp_dma_mask,
6048f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
6058f58de7cSeric miao 	},
6068f58de7cSeric miao 	.resource	= pxa25x_resource_nssp,
6078f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_nssp),
6088f58de7cSeric miao };
6098f58de7cSeric miao 
6108f58de7cSeric miao static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
6118f58de7cSeric miao 
6128f58de7cSeric miao static struct resource pxa25x_resource_assp[] = {
6138f58de7cSeric miao 	[0] = {
6148f58de7cSeric miao 		.start	= 0x41500000,
6158f58de7cSeric miao 		.end	= 0x4150002f,
6168f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
6178f58de7cSeric miao 	},
6188f58de7cSeric miao 	[1] = {
6198f58de7cSeric miao 		.start	= IRQ_ASSP,
6208f58de7cSeric miao 		.end	= IRQ_ASSP,
6218f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
6228f58de7cSeric miao 	},
6238f58de7cSeric miao 	[2] = {
6248f58de7cSeric miao 		/* DRCMR for RX */
6258f58de7cSeric miao 		.start	= 23,
6268f58de7cSeric miao 		.end	= 23,
6278f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6288f58de7cSeric miao 	},
6298f58de7cSeric miao 	[3] = {
6308f58de7cSeric miao 		/* DRCMR for TX */
6318f58de7cSeric miao 		.start	= 24,
6328f58de7cSeric miao 		.end	= 24,
6338f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6348f58de7cSeric miao 	},
6358f58de7cSeric miao };
6368f58de7cSeric miao 
6378f58de7cSeric miao struct platform_device pxa25x_device_assp = {
6388f58de7cSeric miao 	/* ASSP is basically equivalent to NSSP */
6398f58de7cSeric miao 	.name		= "pxa25x-nssp",
6408f58de7cSeric miao 	.id		= 2,
6418f58de7cSeric miao 	.dev		= {
6428f58de7cSeric miao 		.dma_mask = &pxa25x_assp_dma_mask,
6438f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
6448f58de7cSeric miao 	},
6458f58de7cSeric miao 	.resource	= pxa25x_resource_assp,
6468f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_assp),
6478f58de7cSeric miao };
6488f58de7cSeric miao #endif /* CONFIG_PXA25x */
6498f58de7cSeric miao 
6508f58de7cSeric miao #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
651a4553358SHaojian Zhuang static struct resource pxa27x_resource_camera[] = {
65237320980Seric miao 	[0] = {
653a4553358SHaojian Zhuang 		.start	= 0x50000000,
654a4553358SHaojian Zhuang 		.end	= 0x50000fff,
65537320980Seric miao 		.flags	= IORESOURCE_MEM,
65637320980Seric miao 	},
65737320980Seric miao 	[1] = {
658a4553358SHaojian Zhuang 		.start	= IRQ_CAMERA,
659a4553358SHaojian Zhuang 		.end	= IRQ_CAMERA,
66037320980Seric miao 		.flags	= IORESOURCE_IRQ,
66137320980Seric miao 	},
66237320980Seric miao };
66337320980Seric miao 
664a4553358SHaojian Zhuang static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
665a4553358SHaojian Zhuang 
666a4553358SHaojian Zhuang static struct platform_device pxa27x_device_camera = {
667a4553358SHaojian Zhuang 	.name		= "pxa27x-camera",
668a4553358SHaojian Zhuang 	.id		= 0, /* This is used to put cameras on this interface */
669a4553358SHaojian Zhuang 	.dev		= {
670a4553358SHaojian Zhuang 		.dma_mask      		= &pxa27x_dma_mask_camera,
671a4553358SHaojian Zhuang 		.coherent_dma_mask	= 0xffffffff,
672a4553358SHaojian Zhuang 	},
673a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa27x_resource_camera),
674a4553358SHaojian Zhuang 	.resource	= pxa27x_resource_camera,
67537320980Seric miao };
67637320980Seric miao 
677a4553358SHaojian Zhuang void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
67837320980Seric miao {
679a4553358SHaojian Zhuang 	pxa_register_device(&pxa27x_device_camera, info);
68037320980Seric miao }
68137320980Seric miao 
682ec68e45bSeric miao static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
683ec68e45bSeric miao 
684ec68e45bSeric miao static struct resource pxa27x_resource_ohci[] = {
685ec68e45bSeric miao 	[0] = {
686ec68e45bSeric miao 		.start  = 0x4C000000,
687ec68e45bSeric miao 		.end    = 0x4C00ff6f,
688ec68e45bSeric miao 		.flags  = IORESOURCE_MEM,
689ec68e45bSeric miao 	},
690ec68e45bSeric miao 	[1] = {
691ec68e45bSeric miao 		.start  = IRQ_USBH1,
692ec68e45bSeric miao 		.end    = IRQ_USBH1,
693ec68e45bSeric miao 		.flags  = IORESOURCE_IRQ,
694ec68e45bSeric miao 	},
695ec68e45bSeric miao };
696ec68e45bSeric miao 
697ec68e45bSeric miao struct platform_device pxa27x_device_ohci = {
698ec68e45bSeric miao 	.name		= "pxa27x-ohci",
699ec68e45bSeric miao 	.id		= -1,
700ec68e45bSeric miao 	.dev		= {
701ec68e45bSeric miao 		.dma_mask = &pxa27x_ohci_dma_mask,
702ec68e45bSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
703ec68e45bSeric miao 	},
704ec68e45bSeric miao 	.num_resources  = ARRAY_SIZE(pxa27x_resource_ohci),
705ec68e45bSeric miao 	.resource       = pxa27x_resource_ohci,
706ec68e45bSeric miao };
707ec68e45bSeric miao 
708ec68e45bSeric miao void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
709ec68e45bSeric miao {
710ec68e45bSeric miao 	pxa_register_device(&pxa27x_device_ohci, info);
711ec68e45bSeric miao }
712a4553358SHaojian Zhuang #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
713a4553358SHaojian Zhuang 
71449ea7fc0SHaojian Zhuang #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
715a4553358SHaojian Zhuang static struct resource pxa27x_resource_keypad[] = {
716a4553358SHaojian Zhuang 	[0] = {
717a4553358SHaojian Zhuang 		.start	= 0x41500000,
718a4553358SHaojian Zhuang 		.end	= 0x4150004c,
719a4553358SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
720a4553358SHaojian Zhuang 	},
721a4553358SHaojian Zhuang 	[1] = {
722a4553358SHaojian Zhuang 		.start	= IRQ_KEYPAD,
723a4553358SHaojian Zhuang 		.end	= IRQ_KEYPAD,
724a4553358SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
725a4553358SHaojian Zhuang 	},
726a4553358SHaojian Zhuang };
727a4553358SHaojian Zhuang 
728a4553358SHaojian Zhuang struct platform_device pxa27x_device_keypad = {
729a4553358SHaojian Zhuang 	.name		= "pxa27x-keypad",
730a4553358SHaojian Zhuang 	.id		= -1,
731a4553358SHaojian Zhuang 	.resource	= pxa27x_resource_keypad,
732a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa27x_resource_keypad),
733a4553358SHaojian Zhuang };
734a4553358SHaojian Zhuang 
735a4553358SHaojian Zhuang void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
736a4553358SHaojian Zhuang {
737a4553358SHaojian Zhuang 	pxa_register_device(&pxa27x_device_keypad, info);
738a4553358SHaojian Zhuang }
739ec68e45bSeric miao 
7408f58de7cSeric miao static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
7418f58de7cSeric miao 
7428f58de7cSeric miao static struct resource pxa27x_resource_ssp1[] = {
7438f58de7cSeric miao 	[0] = {
7448f58de7cSeric miao 		.start	= 0x41000000,
7458f58de7cSeric miao 		.end	= 0x4100003f,
7468f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
7478f58de7cSeric miao 	},
7488f58de7cSeric miao 	[1] = {
7498f58de7cSeric miao 		.start	= IRQ_SSP,
7508f58de7cSeric miao 		.end	= IRQ_SSP,
7518f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
7528f58de7cSeric miao 	},
7538f58de7cSeric miao 	[2] = {
7548f58de7cSeric miao 		/* DRCMR for RX */
7558f58de7cSeric miao 		.start	= 13,
7568f58de7cSeric miao 		.end	= 13,
7578f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7588f58de7cSeric miao 	},
7598f58de7cSeric miao 	[3] = {
7608f58de7cSeric miao 		/* DRCMR for TX */
7618f58de7cSeric miao 		.start	= 14,
7628f58de7cSeric miao 		.end	= 14,
7638f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7648f58de7cSeric miao 	},
7658f58de7cSeric miao };
7668f58de7cSeric miao 
7678f58de7cSeric miao struct platform_device pxa27x_device_ssp1 = {
7688f58de7cSeric miao 	.name		= "pxa27x-ssp",
7698f58de7cSeric miao 	.id		= 0,
7708f58de7cSeric miao 	.dev		= {
7718f58de7cSeric miao 		.dma_mask = &pxa27x_ssp1_dma_mask,
7728f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
7738f58de7cSeric miao 	},
7748f58de7cSeric miao 	.resource	= pxa27x_resource_ssp1,
7758f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
7768f58de7cSeric miao };
7778f58de7cSeric miao 
7788f58de7cSeric miao static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
7798f58de7cSeric miao 
7808f58de7cSeric miao static struct resource pxa27x_resource_ssp2[] = {
7818f58de7cSeric miao 	[0] = {
7828f58de7cSeric miao 		.start	= 0x41700000,
7838f58de7cSeric miao 		.end	= 0x4170003f,
7848f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
7858f58de7cSeric miao 	},
7868f58de7cSeric miao 	[1] = {
7878f58de7cSeric miao 		.start	= IRQ_SSP2,
7888f58de7cSeric miao 		.end	= IRQ_SSP2,
7898f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
7908f58de7cSeric miao 	},
7918f58de7cSeric miao 	[2] = {
7928f58de7cSeric miao 		/* DRCMR for RX */
7938f58de7cSeric miao 		.start	= 15,
7948f58de7cSeric miao 		.end	= 15,
7958f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7968f58de7cSeric miao 	},
7978f58de7cSeric miao 	[3] = {
7988f58de7cSeric miao 		/* DRCMR for TX */
7998f58de7cSeric miao 		.start	= 16,
8008f58de7cSeric miao 		.end	= 16,
8018f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
8028f58de7cSeric miao 	},
8038f58de7cSeric miao };
8048f58de7cSeric miao 
8058f58de7cSeric miao struct platform_device pxa27x_device_ssp2 = {
8068f58de7cSeric miao 	.name		= "pxa27x-ssp",
8078f58de7cSeric miao 	.id		= 1,
8088f58de7cSeric miao 	.dev		= {
8098f58de7cSeric miao 		.dma_mask = &pxa27x_ssp2_dma_mask,
8108f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
8118f58de7cSeric miao 	},
8128f58de7cSeric miao 	.resource	= pxa27x_resource_ssp2,
8138f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
8148f58de7cSeric miao };
8158f58de7cSeric miao 
8168f58de7cSeric miao static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
8178f58de7cSeric miao 
8188f58de7cSeric miao static struct resource pxa27x_resource_ssp3[] = {
8198f58de7cSeric miao 	[0] = {
8208f58de7cSeric miao 		.start	= 0x41900000,
8218f58de7cSeric miao 		.end	= 0x4190003f,
8228f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
8238f58de7cSeric miao 	},
8248f58de7cSeric miao 	[1] = {
8258f58de7cSeric miao 		.start	= IRQ_SSP3,
8268f58de7cSeric miao 		.end	= IRQ_SSP3,
8278f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
8288f58de7cSeric miao 	},
8298f58de7cSeric miao 	[2] = {
8308f58de7cSeric miao 		/* DRCMR for RX */
8318f58de7cSeric miao 		.start	= 66,
8328f58de7cSeric miao 		.end	= 66,
8338f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
8348f58de7cSeric miao 	},
8358f58de7cSeric miao 	[3] = {
8368f58de7cSeric miao 		/* DRCMR for TX */
8378f58de7cSeric miao 		.start	= 67,
8388f58de7cSeric miao 		.end	= 67,
8398f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
8408f58de7cSeric miao 	},
8418f58de7cSeric miao };
8428f58de7cSeric miao 
8438f58de7cSeric miao struct platform_device pxa27x_device_ssp3 = {
8448f58de7cSeric miao 	.name		= "pxa27x-ssp",
8458f58de7cSeric miao 	.id		= 2,
8468f58de7cSeric miao 	.dev		= {
8478f58de7cSeric miao 		.dma_mask = &pxa27x_ssp3_dma_mask,
8488f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
8498f58de7cSeric miao 	},
8508f58de7cSeric miao 	.resource	= pxa27x_resource_ssp3,
8518f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
8528f58de7cSeric miao };
8533f3acefbSGuennadi Liakhovetski 
85475540c1aSeric miao static struct resource pxa27x_resource_pwm0[] = {
85575540c1aSeric miao 	[0] = {
85675540c1aSeric miao 		.start	= 0x40b00000,
85775540c1aSeric miao 		.end	= 0x40b0001f,
85875540c1aSeric miao 		.flags	= IORESOURCE_MEM,
85975540c1aSeric miao 	},
86075540c1aSeric miao };
86175540c1aSeric miao 
86275540c1aSeric miao struct platform_device pxa27x_device_pwm0 = {
86375540c1aSeric miao 	.name		= "pxa27x-pwm",
86475540c1aSeric miao 	.id		= 0,
86575540c1aSeric miao 	.resource	= pxa27x_resource_pwm0,
86675540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm0),
86775540c1aSeric miao };
86875540c1aSeric miao 
86975540c1aSeric miao static struct resource pxa27x_resource_pwm1[] = {
87075540c1aSeric miao 	[0] = {
87175540c1aSeric miao 		.start	= 0x40c00000,
87275540c1aSeric miao 		.end	= 0x40c0001f,
87375540c1aSeric miao 		.flags	= IORESOURCE_MEM,
87475540c1aSeric miao 	},
87575540c1aSeric miao };
87675540c1aSeric miao 
87775540c1aSeric miao struct platform_device pxa27x_device_pwm1 = {
87875540c1aSeric miao 	.name		= "pxa27x-pwm",
87975540c1aSeric miao 	.id		= 1,
88075540c1aSeric miao 	.resource	= pxa27x_resource_pwm1,
88175540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm1),
88275540c1aSeric miao };
88349ea7fc0SHaojian Zhuang #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
8848f58de7cSeric miao 
8858f58de7cSeric miao #ifdef CONFIG_PXA3xx
8868d33b055SBridge Wu static struct resource pxa3xx_resources_mci2[] = {
8878d33b055SBridge Wu 	[0] = {
8888d33b055SBridge Wu 		.start	= 0x42000000,
8898d33b055SBridge Wu 		.end	= 0x42000fff,
8908d33b055SBridge Wu 		.flags	= IORESOURCE_MEM,
8918d33b055SBridge Wu 	},
8928d33b055SBridge Wu 	[1] = {
8938d33b055SBridge Wu 		.start	= IRQ_MMC2,
8948d33b055SBridge Wu 		.end	= IRQ_MMC2,
8958d33b055SBridge Wu 		.flags	= IORESOURCE_IRQ,
8968d33b055SBridge Wu 	},
8978d33b055SBridge Wu 	[2] = {
8988d33b055SBridge Wu 		.start	= 93,
8998d33b055SBridge Wu 		.end	= 93,
9008d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
9018d33b055SBridge Wu 	},
9028d33b055SBridge Wu 	[3] = {
9038d33b055SBridge Wu 		.start	= 94,
9048d33b055SBridge Wu 		.end	= 94,
9058d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
9068d33b055SBridge Wu 	},
9078d33b055SBridge Wu };
9088d33b055SBridge Wu 
9098d33b055SBridge Wu struct platform_device pxa3xx_device_mci2 = {
9108d33b055SBridge Wu 	.name		= "pxa2xx-mci",
9118d33b055SBridge Wu 	.id		= 1,
9128d33b055SBridge Wu 	.dev		= {
9138d33b055SBridge Wu 		.dma_mask = &pxamci_dmamask,
9148d33b055SBridge Wu 		.coherent_dma_mask =	0xffffffff,
9158d33b055SBridge Wu 	},
9168d33b055SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci2),
9178d33b055SBridge Wu 	.resource	= pxa3xx_resources_mci2,
9188d33b055SBridge Wu };
9198d33b055SBridge Wu 
9208d33b055SBridge Wu void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
9218d33b055SBridge Wu {
9228d33b055SBridge Wu 	pxa_register_device(&pxa3xx_device_mci2, info);
9238d33b055SBridge Wu }
9248d33b055SBridge Wu 
9255a1f21b1SBridge Wu static struct resource pxa3xx_resources_mci3[] = {
9265a1f21b1SBridge Wu 	[0] = {
9275a1f21b1SBridge Wu 		.start	= 0x42500000,
9285a1f21b1SBridge Wu 		.end	= 0x42500fff,
9295a1f21b1SBridge Wu 		.flags	= IORESOURCE_MEM,
9305a1f21b1SBridge Wu 	},
9315a1f21b1SBridge Wu 	[1] = {
9325a1f21b1SBridge Wu 		.start	= IRQ_MMC3,
9335a1f21b1SBridge Wu 		.end	= IRQ_MMC3,
9345a1f21b1SBridge Wu 		.flags	= IORESOURCE_IRQ,
9355a1f21b1SBridge Wu 	},
9365a1f21b1SBridge Wu 	[2] = {
9375a1f21b1SBridge Wu 		.start	= 100,
9385a1f21b1SBridge Wu 		.end	= 100,
9395a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
9405a1f21b1SBridge Wu 	},
9415a1f21b1SBridge Wu 	[3] = {
9425a1f21b1SBridge Wu 		.start	= 101,
9435a1f21b1SBridge Wu 		.end	= 101,
9445a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
9455a1f21b1SBridge Wu 	},
9465a1f21b1SBridge Wu };
9475a1f21b1SBridge Wu 
9485a1f21b1SBridge Wu struct platform_device pxa3xx_device_mci3 = {
9495a1f21b1SBridge Wu 	.name		= "pxa2xx-mci",
9505a1f21b1SBridge Wu 	.id		= 2,
9515a1f21b1SBridge Wu 	.dev		= {
9525a1f21b1SBridge Wu 		.dma_mask = &pxamci_dmamask,
9535a1f21b1SBridge Wu 		.coherent_dma_mask = 0xffffffff,
9545a1f21b1SBridge Wu 	},
9555a1f21b1SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci3),
9565a1f21b1SBridge Wu 	.resource	= pxa3xx_resources_mci3,
9575a1f21b1SBridge Wu };
9585a1f21b1SBridge Wu 
9595a1f21b1SBridge Wu void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
9605a1f21b1SBridge Wu {
9615a1f21b1SBridge Wu 	pxa_register_device(&pxa3xx_device_mci3, info);
9625a1f21b1SBridge Wu }
9635a1f21b1SBridge Wu 
964a4553358SHaojian Zhuang static struct resource pxa3xx_resources_gcu[] = {
965a4553358SHaojian Zhuang 	{
966a4553358SHaojian Zhuang 		.start	= 0x54000000,
967a4553358SHaojian Zhuang 		.end	= 0x54000fff,
968a4553358SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
969a4553358SHaojian Zhuang 	},
970a4553358SHaojian Zhuang 	{
971a4553358SHaojian Zhuang 		.start	= IRQ_GCU,
972a4553358SHaojian Zhuang 		.end	= IRQ_GCU,
973a4553358SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
974a4553358SHaojian Zhuang 	},
975a4553358SHaojian Zhuang };
976a4553358SHaojian Zhuang 
977a4553358SHaojian Zhuang static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
978a4553358SHaojian Zhuang 
979a4553358SHaojian Zhuang struct platform_device pxa3xx_device_gcu = {
980a4553358SHaojian Zhuang 	.name		= "pxa3xx-gcu",
981a4553358SHaojian Zhuang 	.id		= -1,
982a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_gcu),
983a4553358SHaojian Zhuang 	.resource	= pxa3xx_resources_gcu,
984a4553358SHaojian Zhuang 	.dev		= {
985a4553358SHaojian Zhuang 		.dma_mask = &pxa3xx_gcu_dmamask,
986a4553358SHaojian Zhuang 		.coherent_dma_mask = 0xffffffff,
987a4553358SHaojian Zhuang 	},
988a4553358SHaojian Zhuang };
989a4553358SHaojian Zhuang 
990a4553358SHaojian Zhuang #endif /* CONFIG_PXA3xx */
991a4553358SHaojian Zhuang 
99249ea7fc0SHaojian Zhuang #if defined(CONFIG_PXA3xx)
993a4553358SHaojian Zhuang static struct resource pxa3xx_resources_i2c_power[] = {
994a4553358SHaojian Zhuang 	{
995a4553358SHaojian Zhuang 		.start  = 0x40f500c0,
996a4553358SHaojian Zhuang 		.end    = 0x40f500d3,
997a4553358SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
998a4553358SHaojian Zhuang 	}, {
999a4553358SHaojian Zhuang 		.start	= IRQ_PWRI2C,
1000a4553358SHaojian Zhuang 		.end	= IRQ_PWRI2C,
1001a4553358SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1002a4553358SHaojian Zhuang 	},
1003a4553358SHaojian Zhuang };
1004a4553358SHaojian Zhuang 
1005a4553358SHaojian Zhuang struct platform_device pxa3xx_device_i2c_power = {
1006a4553358SHaojian Zhuang 	.name		= "pxa3xx-pwri2c",
1007a4553358SHaojian Zhuang 	.id		= 1,
1008a4553358SHaojian Zhuang 	.resource	= pxa3xx_resources_i2c_power,
1009a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_i2c_power),
1010a4553358SHaojian Zhuang };
1011a4553358SHaojian Zhuang 
10129ae819a8SEric Miao static struct resource pxa3xx_resources_nand[] = {
10139ae819a8SEric Miao 	[0] = {
10149ae819a8SEric Miao 		.start	= 0x43100000,
10159ae819a8SEric Miao 		.end	= 0x43100053,
10169ae819a8SEric Miao 		.flags	= IORESOURCE_MEM,
10179ae819a8SEric Miao 	},
10189ae819a8SEric Miao 	[1] = {
10199ae819a8SEric Miao 		.start	= IRQ_NAND,
10209ae819a8SEric Miao 		.end	= IRQ_NAND,
10219ae819a8SEric Miao 		.flags	= IORESOURCE_IRQ,
10229ae819a8SEric Miao 	},
10239ae819a8SEric Miao 	[2] = {
10249ae819a8SEric Miao 		/* DRCMR for Data DMA */
10259ae819a8SEric Miao 		.start	= 97,
10269ae819a8SEric Miao 		.end	= 97,
10279ae819a8SEric Miao 		.flags	= IORESOURCE_DMA,
10289ae819a8SEric Miao 	},
10299ae819a8SEric Miao 	[3] = {
10309ae819a8SEric Miao 		/* DRCMR for Command DMA */
10319ae819a8SEric Miao 		.start	= 99,
10329ae819a8SEric Miao 		.end	= 99,
10339ae819a8SEric Miao 		.flags	= IORESOURCE_DMA,
10349ae819a8SEric Miao 	},
10359ae819a8SEric Miao };
10369ae819a8SEric Miao 
10379ae819a8SEric Miao static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
10389ae819a8SEric Miao 
10399ae819a8SEric Miao struct platform_device pxa3xx_device_nand = {
10409ae819a8SEric Miao 	.name		= "pxa3xx-nand",
10419ae819a8SEric Miao 	.id		= -1,
10429ae819a8SEric Miao 	.dev		= {
10439ae819a8SEric Miao 		.dma_mask = &pxa3xx_nand_dma_mask,
10449ae819a8SEric Miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
10459ae819a8SEric Miao 	},
10469ae819a8SEric Miao 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_nand),
10479ae819a8SEric Miao 	.resource	= pxa3xx_resources_nand,
10489ae819a8SEric Miao };
10499ae819a8SEric Miao 
10509ae819a8SEric Miao void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
10519ae819a8SEric Miao {
10529ae819a8SEric Miao 	pxa_register_device(&pxa3xx_device_nand, info);
10539ae819a8SEric Miao }
10541ff2c33eSDaniel Mack 
1055a4553358SHaojian Zhuang static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
1056a4553358SHaojian Zhuang 
1057a4553358SHaojian Zhuang static struct resource pxa3xx_resource_ssp4[] = {
1058a4553358SHaojian Zhuang 	[0] = {
1059a4553358SHaojian Zhuang 		.start	= 0x41a00000,
1060a4553358SHaojian Zhuang 		.end	= 0x41a0003f,
10611ff2c33eSDaniel Mack 		.flags	= IORESOURCE_MEM,
10621ff2c33eSDaniel Mack 	},
1063a4553358SHaojian Zhuang 	[1] = {
1064a4553358SHaojian Zhuang 		.start	= IRQ_SSP4,
1065a4553358SHaojian Zhuang 		.end	= IRQ_SSP4,
10661ff2c33eSDaniel Mack 		.flags	= IORESOURCE_IRQ,
10671ff2c33eSDaniel Mack 	},
1068a4553358SHaojian Zhuang 	[2] = {
1069a4553358SHaojian Zhuang 		/* DRCMR for RX */
1070a4553358SHaojian Zhuang 		.start	= 2,
1071a4553358SHaojian Zhuang 		.end	= 2,
1072a4553358SHaojian Zhuang 		.flags	= IORESOURCE_DMA,
1073a4553358SHaojian Zhuang 	},
1074a4553358SHaojian Zhuang 	[3] = {
1075a4553358SHaojian Zhuang 		/* DRCMR for TX */
1076a4553358SHaojian Zhuang 		.start	= 3,
1077a4553358SHaojian Zhuang 		.end	= 3,
1078a4553358SHaojian Zhuang 		.flags	= IORESOURCE_DMA,
10791ff2c33eSDaniel Mack 	},
10801ff2c33eSDaniel Mack };
10811ff2c33eSDaniel Mack 
10820da0e227SDaniel Mack /*
10830da0e227SDaniel Mack  * PXA3xx SSP is basically equivalent to PXA27x.
10840da0e227SDaniel Mack  * However, we need to register the device by the correct name in order to
10850da0e227SDaniel Mack  * make the driver set the correct internal type, hence we provide specific
10860da0e227SDaniel Mack  * platform_devices for each of them.
10870da0e227SDaniel Mack  */
10880da0e227SDaniel Mack struct platform_device pxa3xx_device_ssp1 = {
10890da0e227SDaniel Mack 	.name		= "pxa3xx-ssp",
10900da0e227SDaniel Mack 	.id		= 0,
10910da0e227SDaniel Mack 	.dev		= {
10920da0e227SDaniel Mack 		.dma_mask = &pxa27x_ssp1_dma_mask,
10930da0e227SDaniel Mack 		.coherent_dma_mask = DMA_BIT_MASK(32),
10940da0e227SDaniel Mack 	},
10950da0e227SDaniel Mack 	.resource	= pxa27x_resource_ssp1,
10960da0e227SDaniel Mack 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
10970da0e227SDaniel Mack };
10980da0e227SDaniel Mack 
10990da0e227SDaniel Mack struct platform_device pxa3xx_device_ssp2 = {
11000da0e227SDaniel Mack 	.name		= "pxa3xx-ssp",
11010da0e227SDaniel Mack 	.id		= 1,
11020da0e227SDaniel Mack 	.dev		= {
11030da0e227SDaniel Mack 		.dma_mask = &pxa27x_ssp2_dma_mask,
11040da0e227SDaniel Mack 		.coherent_dma_mask = DMA_BIT_MASK(32),
11050da0e227SDaniel Mack 	},
11060da0e227SDaniel Mack 	.resource	= pxa27x_resource_ssp2,
11070da0e227SDaniel Mack 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
11080da0e227SDaniel Mack };
11090da0e227SDaniel Mack 
11100da0e227SDaniel Mack struct platform_device pxa3xx_device_ssp3 = {
11110da0e227SDaniel Mack 	.name		= "pxa3xx-ssp",
11120da0e227SDaniel Mack 	.id		= 2,
11130da0e227SDaniel Mack 	.dev		= {
11140da0e227SDaniel Mack 		.dma_mask = &pxa27x_ssp3_dma_mask,
11150da0e227SDaniel Mack 		.coherent_dma_mask = DMA_BIT_MASK(32),
11160da0e227SDaniel Mack 	},
11170da0e227SDaniel Mack 	.resource	= pxa27x_resource_ssp3,
11180da0e227SDaniel Mack 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
11190da0e227SDaniel Mack };
11200da0e227SDaniel Mack 
1121a4553358SHaojian Zhuang struct platform_device pxa3xx_device_ssp4 = {
11220da0e227SDaniel Mack 	.name		= "pxa3xx-ssp",
1123a4553358SHaojian Zhuang 	.id		= 3,
1124a4553358SHaojian Zhuang 	.dev		= {
1125a4553358SHaojian Zhuang 		.dma_mask = &pxa3xx_ssp4_dma_mask,
1126a4553358SHaojian Zhuang 		.coherent_dma_mask = DMA_BIT_MASK(32),
1127a4553358SHaojian Zhuang 	},
1128a4553358SHaojian Zhuang 	.resource	= pxa3xx_resource_ssp4,
1129a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa3xx_resource_ssp4),
1130a4553358SHaojian Zhuang };
113149ea7fc0SHaojian Zhuang #endif /* CONFIG_PXA3xx */
1132e172274cSGuennadi Liakhovetski 
1133157d2644SHaojian Zhuang struct resource pxa_resource_gpio[] = {
1134157d2644SHaojian Zhuang 	{
1135157d2644SHaojian Zhuang 		.start	= 0x40e00000,
1136157d2644SHaojian Zhuang 		.end	= 0x40e0ffff,
1137157d2644SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
1138157d2644SHaojian Zhuang 	}, {
1139157d2644SHaojian Zhuang 		.start	= IRQ_GPIO0,
1140157d2644SHaojian Zhuang 		.end	= IRQ_GPIO0,
1141157d2644SHaojian Zhuang 		.name	= "gpio0",
1142157d2644SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1143157d2644SHaojian Zhuang 	}, {
1144157d2644SHaojian Zhuang 		.start	= IRQ_GPIO1,
1145157d2644SHaojian Zhuang 		.end	= IRQ_GPIO1,
1146157d2644SHaojian Zhuang 		.name	= "gpio1",
1147157d2644SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1148157d2644SHaojian Zhuang 	}, {
1149157d2644SHaojian Zhuang 		.start	= IRQ_GPIO_2_x,
1150157d2644SHaojian Zhuang 		.end	= IRQ_GPIO_2_x,
1151157d2644SHaojian Zhuang 		.name	= "gpio_mux",
1152157d2644SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1153157d2644SHaojian Zhuang 	},
1154157d2644SHaojian Zhuang };
1155157d2644SHaojian Zhuang 
11562cab0292SHaojian Zhuang struct platform_device pxa25x_device_gpio = {
11572cab0292SHaojian Zhuang #ifdef CONFIG_CPU_PXA26x
11582cab0292SHaojian Zhuang 	.name		= "pxa26x-gpio",
11592cab0292SHaojian Zhuang #else
11602cab0292SHaojian Zhuang 	.name		= "pxa25x-gpio",
11612cab0292SHaojian Zhuang #endif
11622cab0292SHaojian Zhuang 	.id		= -1,
11632cab0292SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa_resource_gpio),
11642cab0292SHaojian Zhuang 	.resource	= pxa_resource_gpio,
11652cab0292SHaojian Zhuang };
11662cab0292SHaojian Zhuang 
11672cab0292SHaojian Zhuang struct platform_device pxa27x_device_gpio = {
11682cab0292SHaojian Zhuang 	.name		= "pxa27x-gpio",
11692cab0292SHaojian Zhuang 	.id		= -1,
11702cab0292SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa_resource_gpio),
11712cab0292SHaojian Zhuang 	.resource	= pxa_resource_gpio,
11722cab0292SHaojian Zhuang };
11732cab0292SHaojian Zhuang 
11742cab0292SHaojian Zhuang struct platform_device pxa3xx_device_gpio = {
11752cab0292SHaojian Zhuang 	.name		= "pxa3xx-gpio",
11762cab0292SHaojian Zhuang 	.id		= -1,
11772cab0292SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa_resource_gpio),
11782cab0292SHaojian Zhuang 	.resource	= pxa_resource_gpio,
11792cab0292SHaojian Zhuang };
11802cab0292SHaojian Zhuang 
11812cab0292SHaojian Zhuang struct platform_device pxa93x_device_gpio = {
11822cab0292SHaojian Zhuang 	.name		= "pxa93x-gpio",
1183157d2644SHaojian Zhuang 	.id		= -1,
1184157d2644SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa_resource_gpio),
1185157d2644SHaojian Zhuang 	.resource	= pxa_resource_gpio,
1186157d2644SHaojian Zhuang };
1187157d2644SHaojian Zhuang 
1188e172274cSGuennadi Liakhovetski /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
1189e172274cSGuennadi Liakhovetski  * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
1190e172274cSGuennadi Liakhovetski void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
1191e172274cSGuennadi Liakhovetski {
1192e172274cSGuennadi Liakhovetski 	struct platform_device *pd;
1193e172274cSGuennadi Liakhovetski 
1194e172274cSGuennadi Liakhovetski 	pd = platform_device_alloc("pxa2xx-spi", id);
1195e172274cSGuennadi Liakhovetski 	if (pd == NULL) {
1196e172274cSGuennadi Liakhovetski 		printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
1197e172274cSGuennadi Liakhovetski 		       id);
1198e172274cSGuennadi Liakhovetski 		return;
1199e172274cSGuennadi Liakhovetski 	}
1200e172274cSGuennadi Liakhovetski 
1201e172274cSGuennadi Liakhovetski 	pd->dev.platform_data = info;
1202e172274cSGuennadi Liakhovetski 	platform_device_add(pd);
1203e172274cSGuennadi Liakhovetski }
12044be0856fSRobert Jarzmik 
12054be0856fSRobert Jarzmik static struct mmp_dma_platdata pxa_dma_pdata = {
12064be0856fSRobert Jarzmik 	.dma_channels	= 0,
120772b195cbSRobert Jarzmik 	.nb_requestors	= 0,
12084be0856fSRobert Jarzmik };
12094be0856fSRobert Jarzmik 
12104be0856fSRobert Jarzmik static struct resource pxa_dma_resource[] = {
12114be0856fSRobert Jarzmik 	[0] = {
12124be0856fSRobert Jarzmik 		.start	= 0x40000000,
12134be0856fSRobert Jarzmik 		.end	= 0x4000ffff,
12144be0856fSRobert Jarzmik 		.flags	= IORESOURCE_MEM,
12154be0856fSRobert Jarzmik 	},
12164be0856fSRobert Jarzmik 	[1] = {
12174be0856fSRobert Jarzmik 		.start	= IRQ_DMA,
12184be0856fSRobert Jarzmik 		.end	= IRQ_DMA,
12194be0856fSRobert Jarzmik 		.flags	= IORESOURCE_IRQ,
12204be0856fSRobert Jarzmik 	},
12214be0856fSRobert Jarzmik };
12224be0856fSRobert Jarzmik 
12234be0856fSRobert Jarzmik static u64 pxadma_dmamask = 0xffffffffUL;
12244be0856fSRobert Jarzmik 
12254be0856fSRobert Jarzmik static struct platform_device pxa2xx_pxa_dma = {
12264be0856fSRobert Jarzmik 	.name		= "pxa-dma",
12274be0856fSRobert Jarzmik 	.id		= 0,
12284be0856fSRobert Jarzmik 	.dev		= {
12294be0856fSRobert Jarzmik 		.dma_mask = &pxadma_dmamask,
12304be0856fSRobert Jarzmik 		.coherent_dma_mask = 0xffffffff,
12314be0856fSRobert Jarzmik 	},
12324be0856fSRobert Jarzmik 	.num_resources	= ARRAY_SIZE(pxa_dma_resource),
12334be0856fSRobert Jarzmik 	.resource	= pxa_dma_resource,
12344be0856fSRobert Jarzmik };
12354be0856fSRobert Jarzmik 
123672b195cbSRobert Jarzmik void __init pxa2xx_set_dmac_info(int nb_channels, int nb_requestors)
12374be0856fSRobert Jarzmik {
12384be0856fSRobert Jarzmik 	pxa_dma_pdata.dma_channels = nb_channels;
12394c35430aSRobert Jarzmik 	pxa_dma_pdata.nb_requestors = nb_requestors;
12404be0856fSRobert Jarzmik 	pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata);
12414be0856fSRobert Jarzmik }
1242