xref: /linux/arch/arm/mach-pxa/devices.c (revision 9ae819a819b4dfc60ac13dd1f1e1a7eaa3d4a6cb)
18f58de7cSeric miao #include <linux/module.h>
28f58de7cSeric miao #include <linux/kernel.h>
38f58de7cSeric miao #include <linux/init.h>
48f58de7cSeric miao #include <linux/platform_device.h>
58f58de7cSeric miao #include <linux/dma-mapping.h>
68f58de7cSeric miao 
78f58de7cSeric miao #include <asm/arch/gpio.h>
88f58de7cSeric miao #include <asm/arch/udc.h>
98f58de7cSeric miao #include <asm/arch/pxafb.h>
108f58de7cSeric miao #include <asm/arch/mmc.h>
118f58de7cSeric miao #include <asm/arch/irda.h>
128f58de7cSeric miao #include <asm/arch/i2c.h>
13bc3a5959SPhilipp Zabel #include <asm/arch/mfp-pxa27x.h>
14cd5604d5Seric miao #include <asm/arch/ohci.h>
1537320980Seric miao #include <asm/arch/pxa27x_keypad.h>
16e172274cSGuennadi Liakhovetski #include <asm/arch/pxa2xx_spi.h>
173f3acefbSGuennadi Liakhovetski #include <asm/arch/camera.h>
189f19d638SMark Brown #include <asm/arch/audio.h>
19*9ae819a8SEric Miao #include <asm/arch/pxa3xx_nand.h>
208f58de7cSeric miao 
218f58de7cSeric miao #include "devices.h"
22bc3a5959SPhilipp Zabel #include "generic.h"
238f58de7cSeric miao 
248f58de7cSeric miao void __init pxa_register_device(struct platform_device *dev, void *data)
258f58de7cSeric miao {
268f58de7cSeric miao 	int ret;
278f58de7cSeric miao 
288f58de7cSeric miao 	dev->dev.platform_data = data;
298f58de7cSeric miao 
308f58de7cSeric miao 	ret = platform_device_register(dev);
318f58de7cSeric miao 	if (ret)
328f58de7cSeric miao 		dev_err(&dev->dev, "unable to register device: %d\n", ret);
338f58de7cSeric miao }
348f58de7cSeric miao 
358f58de7cSeric miao static struct resource pxamci_resources[] = {
368f58de7cSeric miao 	[0] = {
378f58de7cSeric miao 		.start	= 0x41100000,
388f58de7cSeric miao 		.end	= 0x41100fff,
398f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
408f58de7cSeric miao 	},
418f58de7cSeric miao 	[1] = {
428f58de7cSeric miao 		.start	= IRQ_MMC,
438f58de7cSeric miao 		.end	= IRQ_MMC,
448f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
458f58de7cSeric miao 	},
468f58de7cSeric miao 	[2] = {
478f58de7cSeric miao 		.start	= 21,
488f58de7cSeric miao 		.end	= 21,
498f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
508f58de7cSeric miao 	},
518f58de7cSeric miao 	[3] = {
528f58de7cSeric miao 		.start	= 22,
538f58de7cSeric miao 		.end	= 22,
548f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
558f58de7cSeric miao 	},
568f58de7cSeric miao };
578f58de7cSeric miao 
588f58de7cSeric miao static u64 pxamci_dmamask = 0xffffffffUL;
598f58de7cSeric miao 
608f58de7cSeric miao struct platform_device pxa_device_mci = {
618f58de7cSeric miao 	.name		= "pxa2xx-mci",
62fafc9d3fSBridge Wu 	.id		= 0,
638f58de7cSeric miao 	.dev		= {
648f58de7cSeric miao 		.dma_mask = &pxamci_dmamask,
658f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
668f58de7cSeric miao 	},
678f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxamci_resources),
688f58de7cSeric miao 	.resource	= pxamci_resources,
698f58de7cSeric miao };
708f58de7cSeric miao 
718f58de7cSeric miao void __init pxa_set_mci_info(struct pxamci_platform_data *info)
728f58de7cSeric miao {
738f58de7cSeric miao 	pxa_register_device(&pxa_device_mci, info);
748f58de7cSeric miao }
758f58de7cSeric miao 
768f58de7cSeric miao 
778f58de7cSeric miao static struct pxa2xx_udc_mach_info pxa_udc_info;
788f58de7cSeric miao 
798f58de7cSeric miao void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
808f58de7cSeric miao {
818f58de7cSeric miao 	memcpy(&pxa_udc_info, info, sizeof *info);
828f58de7cSeric miao }
838f58de7cSeric miao 
848f58de7cSeric miao static struct resource pxa2xx_udc_resources[] = {
858f58de7cSeric miao 	[0] = {
868f58de7cSeric miao 		.start	= 0x40600000,
878f58de7cSeric miao 		.end	= 0x4060ffff,
888f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
898f58de7cSeric miao 	},
908f58de7cSeric miao 	[1] = {
918f58de7cSeric miao 		.start	= IRQ_USB,
928f58de7cSeric miao 		.end	= IRQ_USB,
938f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
948f58de7cSeric miao 	},
958f58de7cSeric miao };
968f58de7cSeric miao 
978f58de7cSeric miao static u64 udc_dma_mask = ~(u32)0;
988f58de7cSeric miao 
997a857620SPhilipp Zabel struct platform_device pxa25x_device_udc = {
1007a857620SPhilipp Zabel 	.name		= "pxa25x-udc",
1017a857620SPhilipp Zabel 	.id		= -1,
1027a857620SPhilipp Zabel 	.resource	= pxa2xx_udc_resources,
1037a857620SPhilipp Zabel 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
1047a857620SPhilipp Zabel 	.dev		=  {
1057a857620SPhilipp Zabel 		.platform_data	= &pxa_udc_info,
1067a857620SPhilipp Zabel 		.dma_mask	= &udc_dma_mask,
1077a857620SPhilipp Zabel 	}
1087a857620SPhilipp Zabel };
1097a857620SPhilipp Zabel 
1107a857620SPhilipp Zabel struct platform_device pxa27x_device_udc = {
1117a857620SPhilipp Zabel 	.name		= "pxa27x-udc",
1128f58de7cSeric miao 	.id		= -1,
1138f58de7cSeric miao 	.resource	= pxa2xx_udc_resources,
1148f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
1158f58de7cSeric miao 	.dev		=  {
1168f58de7cSeric miao 		.platform_data	= &pxa_udc_info,
1178f58de7cSeric miao 		.dma_mask	= &udc_dma_mask,
1188f58de7cSeric miao 	}
1198f58de7cSeric miao };
1208f58de7cSeric miao 
1218f58de7cSeric miao static struct resource pxafb_resources[] = {
1228f58de7cSeric miao 	[0] = {
1238f58de7cSeric miao 		.start	= 0x44000000,
1248f58de7cSeric miao 		.end	= 0x4400ffff,
1258f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1268f58de7cSeric miao 	},
1278f58de7cSeric miao 	[1] = {
1288f58de7cSeric miao 		.start	= IRQ_LCD,
1298f58de7cSeric miao 		.end	= IRQ_LCD,
1308f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1318f58de7cSeric miao 	},
1328f58de7cSeric miao };
1338f58de7cSeric miao 
1348f58de7cSeric miao static u64 fb_dma_mask = ~(u64)0;
1358f58de7cSeric miao 
1368f58de7cSeric miao struct platform_device pxa_device_fb = {
1378f58de7cSeric miao 	.name		= "pxa2xx-fb",
1388f58de7cSeric miao 	.id		= -1,
1398f58de7cSeric miao 	.dev		= {
1408f58de7cSeric miao 		.dma_mask	= &fb_dma_mask,
1418f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
1428f58de7cSeric miao 	},
1438f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxafb_resources),
1448f58de7cSeric miao 	.resource	= pxafb_resources,
1458f58de7cSeric miao };
1468f58de7cSeric miao 
1478f58de7cSeric miao void __init set_pxa_fb_info(struct pxafb_mach_info *info)
1488f58de7cSeric miao {
1498f58de7cSeric miao 	pxa_register_device(&pxa_device_fb, info);
1508f58de7cSeric miao }
1518f58de7cSeric miao 
1528f58de7cSeric miao void __init set_pxa_fb_parent(struct device *parent_dev)
1538f58de7cSeric miao {
1548f58de7cSeric miao 	pxa_device_fb.dev.parent = parent_dev;
1558f58de7cSeric miao }
1568f58de7cSeric miao 
1578f58de7cSeric miao static struct resource pxa_resource_ffuart[] = {
1588f58de7cSeric miao 	{
1598f58de7cSeric miao 		.start	= __PREG(FFUART),
1608f58de7cSeric miao 		.end	= __PREG(FFUART) + 35,
1618f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1628f58de7cSeric miao 	}, {
1638f58de7cSeric miao 		.start	= IRQ_FFUART,
1648f58de7cSeric miao 		.end	= IRQ_FFUART,
1658f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1668f58de7cSeric miao 	}
1678f58de7cSeric miao };
1688f58de7cSeric miao 
1698f58de7cSeric miao struct platform_device pxa_device_ffuart= {
1708f58de7cSeric miao 	.name		= "pxa2xx-uart",
1718f58de7cSeric miao 	.id		= 0,
1728f58de7cSeric miao 	.resource	= pxa_resource_ffuart,
1738f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_ffuart),
1748f58de7cSeric miao };
1758f58de7cSeric miao 
1768f58de7cSeric miao static struct resource pxa_resource_btuart[] = {
1778f58de7cSeric miao 	{
1788f58de7cSeric miao 		.start	= __PREG(BTUART),
1798f58de7cSeric miao 		.end	= __PREG(BTUART) + 35,
1808f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1818f58de7cSeric miao 	}, {
1828f58de7cSeric miao 		.start	= IRQ_BTUART,
1838f58de7cSeric miao 		.end	= IRQ_BTUART,
1848f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1858f58de7cSeric miao 	}
1868f58de7cSeric miao };
1878f58de7cSeric miao 
1888f58de7cSeric miao struct platform_device pxa_device_btuart = {
1898f58de7cSeric miao 	.name		= "pxa2xx-uart",
1908f58de7cSeric miao 	.id		= 1,
1918f58de7cSeric miao 	.resource	= pxa_resource_btuart,
1928f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_btuart),
1938f58de7cSeric miao };
1948f58de7cSeric miao 
1958f58de7cSeric miao static struct resource pxa_resource_stuart[] = {
1968f58de7cSeric miao 	{
1978f58de7cSeric miao 		.start	= __PREG(STUART),
1988f58de7cSeric miao 		.end	= __PREG(STUART) + 35,
1998f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2008f58de7cSeric miao 	}, {
2018f58de7cSeric miao 		.start	= IRQ_STUART,
2028f58de7cSeric miao 		.end	= IRQ_STUART,
2038f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2048f58de7cSeric miao 	}
2058f58de7cSeric miao };
2068f58de7cSeric miao 
2078f58de7cSeric miao struct platform_device pxa_device_stuart = {
2088f58de7cSeric miao 	.name		= "pxa2xx-uart",
2098f58de7cSeric miao 	.id		= 2,
2108f58de7cSeric miao 	.resource	= pxa_resource_stuart,
2118f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_stuart),
2128f58de7cSeric miao };
2138f58de7cSeric miao 
2148f58de7cSeric miao static struct resource pxa_resource_hwuart[] = {
2158f58de7cSeric miao 	{
2168f58de7cSeric miao 		.start	= __PREG(HWUART),
2178f58de7cSeric miao 		.end	= __PREG(HWUART) + 47,
2188f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2198f58de7cSeric miao 	}, {
2208f58de7cSeric miao 		.start	= IRQ_HWUART,
2218f58de7cSeric miao 		.end	= IRQ_HWUART,
2228f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2238f58de7cSeric miao 	}
2248f58de7cSeric miao };
2258f58de7cSeric miao 
2268f58de7cSeric miao struct platform_device pxa_device_hwuart = {
2278f58de7cSeric miao 	.name		= "pxa2xx-uart",
2288f58de7cSeric miao 	.id		= 3,
2298f58de7cSeric miao 	.resource	= pxa_resource_hwuart,
2308f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
2318f58de7cSeric miao };
2328f58de7cSeric miao 
2338f58de7cSeric miao static struct resource pxai2c_resources[] = {
2348f58de7cSeric miao 	{
2358f58de7cSeric miao 		.start	= 0x40301680,
2368f58de7cSeric miao 		.end	= 0x403016a3,
2378f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2388f58de7cSeric miao 	}, {
2398f58de7cSeric miao 		.start	= IRQ_I2C,
2408f58de7cSeric miao 		.end	= IRQ_I2C,
2418f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2428f58de7cSeric miao 	},
2438f58de7cSeric miao };
2448f58de7cSeric miao 
2458f58de7cSeric miao struct platform_device pxa_device_i2c = {
2468f58de7cSeric miao 	.name		= "pxa2xx-i2c",
2478f58de7cSeric miao 	.id		= 0,
2488f58de7cSeric miao 	.resource	= pxai2c_resources,
2498f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2c_resources),
2508f58de7cSeric miao };
2518f58de7cSeric miao 
252bc3a5959SPhilipp Zabel static unsigned long pxa27x_i2c_mfp_cfg[] = {
253bc3a5959SPhilipp Zabel 	GPIO117_I2C_SCL,
254bc3a5959SPhilipp Zabel 	GPIO118_I2C_SDA,
255bc3a5959SPhilipp Zabel };
256bc3a5959SPhilipp Zabel 
2578f58de7cSeric miao void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
2588f58de7cSeric miao {
259bc3a5959SPhilipp Zabel 	if (cpu_is_pxa27x())
260bc3a5959SPhilipp Zabel 		pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg));
2618f58de7cSeric miao 	pxa_register_device(&pxa_device_i2c, info);
2628f58de7cSeric miao }
2638f58de7cSeric miao 
2648f58de7cSeric miao static struct resource pxai2s_resources[] = {
2658f58de7cSeric miao 	{
2668f58de7cSeric miao 		.start	= 0x40400000,
2678f58de7cSeric miao 		.end	= 0x40400083,
2688f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2698f58de7cSeric miao 	}, {
2708f58de7cSeric miao 		.start	= IRQ_I2S,
2718f58de7cSeric miao 		.end	= IRQ_I2S,
2728f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2738f58de7cSeric miao 	},
2748f58de7cSeric miao };
2758f58de7cSeric miao 
2768f58de7cSeric miao struct platform_device pxa_device_i2s = {
2778f58de7cSeric miao 	.name		= "pxa2xx-i2s",
2788f58de7cSeric miao 	.id		= -1,
2798f58de7cSeric miao 	.resource	= pxai2s_resources,
2808f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2s_resources),
2818f58de7cSeric miao };
2828f58de7cSeric miao 
2838f58de7cSeric miao static u64 pxaficp_dmamask = ~(u32)0;
2848f58de7cSeric miao 
2858f58de7cSeric miao struct platform_device pxa_device_ficp = {
2868f58de7cSeric miao 	.name		= "pxa2xx-ir",
2878f58de7cSeric miao 	.id		= -1,
2888f58de7cSeric miao 	.dev		= {
2898f58de7cSeric miao 		.dma_mask = &pxaficp_dmamask,
2908f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
2918f58de7cSeric miao 	},
2928f58de7cSeric miao };
2938f58de7cSeric miao 
2948f58de7cSeric miao void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
2958f58de7cSeric miao {
2968f58de7cSeric miao 	pxa_register_device(&pxa_device_ficp, info);
2978f58de7cSeric miao }
2988f58de7cSeric miao 
2998f58de7cSeric miao struct platform_device pxa_device_rtc = {
3008f58de7cSeric miao 	.name		= "sa1100-rtc",
3018f58de7cSeric miao 	.id		= -1,
3028f58de7cSeric miao };
3038f58de7cSeric miao 
3049f19d638SMark Brown static struct resource pxa_ac97_resources[] = {
3059f19d638SMark Brown 	[0] = {
3069f19d638SMark Brown 		.start  = 0x40500000,
3079f19d638SMark Brown 		.end	= 0x40500000 + 0xfff,
3089f19d638SMark Brown 		.flags  = IORESOURCE_MEM,
3099f19d638SMark Brown 	},
3109f19d638SMark Brown 	[1] = {
3119f19d638SMark Brown 		.start  = IRQ_AC97,
3129f19d638SMark Brown 		.end    = IRQ_AC97,
3139f19d638SMark Brown 		.flags  = IORESOURCE_IRQ,
3149f19d638SMark Brown 	},
3159f19d638SMark Brown };
3169f19d638SMark Brown 
3179f19d638SMark Brown static u64 pxa_ac97_dmamask = 0xffffffffUL;
3189f19d638SMark Brown 
3199f19d638SMark Brown struct platform_device pxa_device_ac97 = {
3209f19d638SMark Brown 	.name           = "pxa2xx-ac97",
3219f19d638SMark Brown 	.id             = -1,
3229f19d638SMark Brown 	.dev            = {
3239f19d638SMark Brown 		.dma_mask = &pxa_ac97_dmamask,
3249f19d638SMark Brown 		.coherent_dma_mask = 0xffffffff,
3259f19d638SMark Brown 	},
3269f19d638SMark Brown 	.num_resources  = ARRAY_SIZE(pxa_ac97_resources),
3279f19d638SMark Brown 	.resource       = pxa_ac97_resources,
3289f19d638SMark Brown };
3299f19d638SMark Brown 
3309f19d638SMark Brown void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
3319f19d638SMark Brown {
3329f19d638SMark Brown 	pxa_register_device(&pxa_device_ac97, ops);
3339f19d638SMark Brown }
3349f19d638SMark Brown 
3358f58de7cSeric miao #ifdef CONFIG_PXA25x
3368f58de7cSeric miao 
33775540c1aSeric miao static struct resource pxa25x_resource_pwm0[] = {
33875540c1aSeric miao 	[0] = {
33975540c1aSeric miao 		.start	= 0x40b00000,
34075540c1aSeric miao 		.end	= 0x40b0000f,
34175540c1aSeric miao 		.flags	= IORESOURCE_MEM,
34275540c1aSeric miao 	},
34375540c1aSeric miao };
34475540c1aSeric miao 
34575540c1aSeric miao struct platform_device pxa25x_device_pwm0 = {
34675540c1aSeric miao 	.name		= "pxa25x-pwm",
34775540c1aSeric miao 	.id		= 0,
34875540c1aSeric miao 	.resource	= pxa25x_resource_pwm0,
34975540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm0),
35075540c1aSeric miao };
35175540c1aSeric miao 
35275540c1aSeric miao static struct resource pxa25x_resource_pwm1[] = {
35375540c1aSeric miao 	[0] = {
35475540c1aSeric miao 		.start	= 0x40c00000,
35575540c1aSeric miao 		.end	= 0x40c0000f,
35675540c1aSeric miao 		.flags	= IORESOURCE_MEM,
35775540c1aSeric miao 	},
35875540c1aSeric miao };
35975540c1aSeric miao 
36075540c1aSeric miao struct platform_device pxa25x_device_pwm1 = {
36175540c1aSeric miao 	.name		= "pxa25x-pwm",
36275540c1aSeric miao 	.id		= 1,
36375540c1aSeric miao 	.resource	= pxa25x_resource_pwm1,
36475540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm1),
36575540c1aSeric miao };
36675540c1aSeric miao 
3678f58de7cSeric miao static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
3688f58de7cSeric miao 
3698f58de7cSeric miao static struct resource pxa25x_resource_ssp[] = {
3708f58de7cSeric miao 	[0] = {
3718f58de7cSeric miao 		.start	= 0x41000000,
3728f58de7cSeric miao 		.end	= 0x4100001f,
3738f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3748f58de7cSeric miao 	},
3758f58de7cSeric miao 	[1] = {
3768f58de7cSeric miao 		.start	= IRQ_SSP,
3778f58de7cSeric miao 		.end	= IRQ_SSP,
3788f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3798f58de7cSeric miao 	},
3808f58de7cSeric miao 	[2] = {
3818f58de7cSeric miao 		/* DRCMR for RX */
3828f58de7cSeric miao 		.start	= 13,
3838f58de7cSeric miao 		.end	= 13,
3848f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
3858f58de7cSeric miao 	},
3868f58de7cSeric miao 	[3] = {
3878f58de7cSeric miao 		/* DRCMR for TX */
3888f58de7cSeric miao 		.start	= 14,
3898f58de7cSeric miao 		.end	= 14,
3908f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
3918f58de7cSeric miao 	},
3928f58de7cSeric miao };
3938f58de7cSeric miao 
3948f58de7cSeric miao struct platform_device pxa25x_device_ssp = {
3958f58de7cSeric miao 	.name		= "pxa25x-ssp",
3968f58de7cSeric miao 	.id		= 0,
3978f58de7cSeric miao 	.dev		= {
3988f58de7cSeric miao 		.dma_mask = &pxa25x_ssp_dma_mask,
3998f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
4008f58de7cSeric miao 	},
4018f58de7cSeric miao 	.resource	= pxa25x_resource_ssp,
4028f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_ssp),
4038f58de7cSeric miao };
4048f58de7cSeric miao 
4058f58de7cSeric miao static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
4068f58de7cSeric miao 
4078f58de7cSeric miao static struct resource pxa25x_resource_nssp[] = {
4088f58de7cSeric miao 	[0] = {
4098f58de7cSeric miao 		.start	= 0x41400000,
4108f58de7cSeric miao 		.end	= 0x4140002f,
4118f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
4128f58de7cSeric miao 	},
4138f58de7cSeric miao 	[1] = {
4148f58de7cSeric miao 		.start	= IRQ_NSSP,
4158f58de7cSeric miao 		.end	= IRQ_NSSP,
4168f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
4178f58de7cSeric miao 	},
4188f58de7cSeric miao 	[2] = {
4198f58de7cSeric miao 		/* DRCMR for RX */
4208f58de7cSeric miao 		.start	= 15,
4218f58de7cSeric miao 		.end	= 15,
4228f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
4238f58de7cSeric miao 	},
4248f58de7cSeric miao 	[3] = {
4258f58de7cSeric miao 		/* DRCMR for TX */
4268f58de7cSeric miao 		.start	= 16,
4278f58de7cSeric miao 		.end	= 16,
4288f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
4298f58de7cSeric miao 	},
4308f58de7cSeric miao };
4318f58de7cSeric miao 
4328f58de7cSeric miao struct platform_device pxa25x_device_nssp = {
4338f58de7cSeric miao 	.name		= "pxa25x-nssp",
4348f58de7cSeric miao 	.id		= 1,
4358f58de7cSeric miao 	.dev		= {
4368f58de7cSeric miao 		.dma_mask = &pxa25x_nssp_dma_mask,
4378f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
4388f58de7cSeric miao 	},
4398f58de7cSeric miao 	.resource	= pxa25x_resource_nssp,
4408f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_nssp),
4418f58de7cSeric miao };
4428f58de7cSeric miao 
4438f58de7cSeric miao static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
4448f58de7cSeric miao 
4458f58de7cSeric miao static struct resource pxa25x_resource_assp[] = {
4468f58de7cSeric miao 	[0] = {
4478f58de7cSeric miao 		.start	= 0x41500000,
4488f58de7cSeric miao 		.end	= 0x4150002f,
4498f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
4508f58de7cSeric miao 	},
4518f58de7cSeric miao 	[1] = {
4528f58de7cSeric miao 		.start	= IRQ_ASSP,
4538f58de7cSeric miao 		.end	= IRQ_ASSP,
4548f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
4558f58de7cSeric miao 	},
4568f58de7cSeric miao 	[2] = {
4578f58de7cSeric miao 		/* DRCMR for RX */
4588f58de7cSeric miao 		.start	= 23,
4598f58de7cSeric miao 		.end	= 23,
4608f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
4618f58de7cSeric miao 	},
4628f58de7cSeric miao 	[3] = {
4638f58de7cSeric miao 		/* DRCMR for TX */
4648f58de7cSeric miao 		.start	= 24,
4658f58de7cSeric miao 		.end	= 24,
4668f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
4678f58de7cSeric miao 	},
4688f58de7cSeric miao };
4698f58de7cSeric miao 
4708f58de7cSeric miao struct platform_device pxa25x_device_assp = {
4718f58de7cSeric miao 	/* ASSP is basically equivalent to NSSP */
4728f58de7cSeric miao 	.name		= "pxa25x-nssp",
4738f58de7cSeric miao 	.id		= 2,
4748f58de7cSeric miao 	.dev		= {
4758f58de7cSeric miao 		.dma_mask = &pxa25x_assp_dma_mask,
4768f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
4778f58de7cSeric miao 	},
4788f58de7cSeric miao 	.resource	= pxa25x_resource_assp,
4798f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_assp),
4808f58de7cSeric miao };
4818f58de7cSeric miao #endif /* CONFIG_PXA25x */
4828f58de7cSeric miao 
4838f58de7cSeric miao #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
4848f58de7cSeric miao 
48537320980Seric miao static struct resource pxa27x_resource_keypad[] = {
48637320980Seric miao 	[0] = {
48737320980Seric miao 		.start	= 0x41500000,
48837320980Seric miao 		.end	= 0x4150004c,
48937320980Seric miao 		.flags	= IORESOURCE_MEM,
49037320980Seric miao 	},
49137320980Seric miao 	[1] = {
49237320980Seric miao 		.start	= IRQ_KEYPAD,
49337320980Seric miao 		.end	= IRQ_KEYPAD,
49437320980Seric miao 		.flags	= IORESOURCE_IRQ,
49537320980Seric miao 	},
49637320980Seric miao };
49737320980Seric miao 
49837320980Seric miao struct platform_device pxa27x_device_keypad = {
49937320980Seric miao 	.name		= "pxa27x-keypad",
50037320980Seric miao 	.id		= -1,
50137320980Seric miao 	.resource	= pxa27x_resource_keypad,
50237320980Seric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_keypad),
50337320980Seric miao };
50437320980Seric miao 
50537320980Seric miao void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
50637320980Seric miao {
50737320980Seric miao 	pxa_register_device(&pxa27x_device_keypad, info);
50837320980Seric miao }
50937320980Seric miao 
510ec68e45bSeric miao static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
511ec68e45bSeric miao 
512ec68e45bSeric miao static struct resource pxa27x_resource_ohci[] = {
513ec68e45bSeric miao 	[0] = {
514ec68e45bSeric miao 		.start  = 0x4C000000,
515ec68e45bSeric miao 		.end    = 0x4C00ff6f,
516ec68e45bSeric miao 		.flags  = IORESOURCE_MEM,
517ec68e45bSeric miao 	},
518ec68e45bSeric miao 	[1] = {
519ec68e45bSeric miao 		.start  = IRQ_USBH1,
520ec68e45bSeric miao 		.end    = IRQ_USBH1,
521ec68e45bSeric miao 		.flags  = IORESOURCE_IRQ,
522ec68e45bSeric miao 	},
523ec68e45bSeric miao };
524ec68e45bSeric miao 
525ec68e45bSeric miao struct platform_device pxa27x_device_ohci = {
526ec68e45bSeric miao 	.name		= "pxa27x-ohci",
527ec68e45bSeric miao 	.id		= -1,
528ec68e45bSeric miao 	.dev		= {
529ec68e45bSeric miao 		.dma_mask = &pxa27x_ohci_dma_mask,
530ec68e45bSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
531ec68e45bSeric miao 	},
532ec68e45bSeric miao 	.num_resources  = ARRAY_SIZE(pxa27x_resource_ohci),
533ec68e45bSeric miao 	.resource       = pxa27x_resource_ohci,
534ec68e45bSeric miao };
535ec68e45bSeric miao 
536ec68e45bSeric miao void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
537ec68e45bSeric miao {
538ec68e45bSeric miao 	pxa_register_device(&pxa27x_device_ohci, info);
539ec68e45bSeric miao }
540ec68e45bSeric miao 
5418f58de7cSeric miao static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
5428f58de7cSeric miao 
5438f58de7cSeric miao static struct resource pxa27x_resource_ssp1[] = {
5448f58de7cSeric miao 	[0] = {
5458f58de7cSeric miao 		.start	= 0x41000000,
5468f58de7cSeric miao 		.end	= 0x4100003f,
5478f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5488f58de7cSeric miao 	},
5498f58de7cSeric miao 	[1] = {
5508f58de7cSeric miao 		.start	= IRQ_SSP,
5518f58de7cSeric miao 		.end	= IRQ_SSP,
5528f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5538f58de7cSeric miao 	},
5548f58de7cSeric miao 	[2] = {
5558f58de7cSeric miao 		/* DRCMR for RX */
5568f58de7cSeric miao 		.start	= 13,
5578f58de7cSeric miao 		.end	= 13,
5588f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5598f58de7cSeric miao 	},
5608f58de7cSeric miao 	[3] = {
5618f58de7cSeric miao 		/* DRCMR for TX */
5628f58de7cSeric miao 		.start	= 14,
5638f58de7cSeric miao 		.end	= 14,
5648f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5658f58de7cSeric miao 	},
5668f58de7cSeric miao };
5678f58de7cSeric miao 
5688f58de7cSeric miao struct platform_device pxa27x_device_ssp1 = {
5698f58de7cSeric miao 	.name		= "pxa27x-ssp",
5708f58de7cSeric miao 	.id		= 0,
5718f58de7cSeric miao 	.dev		= {
5728f58de7cSeric miao 		.dma_mask = &pxa27x_ssp1_dma_mask,
5738f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
5748f58de7cSeric miao 	},
5758f58de7cSeric miao 	.resource	= pxa27x_resource_ssp1,
5768f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
5778f58de7cSeric miao };
5788f58de7cSeric miao 
5798f58de7cSeric miao static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
5808f58de7cSeric miao 
5818f58de7cSeric miao static struct resource pxa27x_resource_ssp2[] = {
5828f58de7cSeric miao 	[0] = {
5838f58de7cSeric miao 		.start	= 0x41700000,
5848f58de7cSeric miao 		.end	= 0x4170003f,
5858f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5868f58de7cSeric miao 	},
5878f58de7cSeric miao 	[1] = {
5888f58de7cSeric miao 		.start	= IRQ_SSP2,
5898f58de7cSeric miao 		.end	= IRQ_SSP2,
5908f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5918f58de7cSeric miao 	},
5928f58de7cSeric miao 	[2] = {
5938f58de7cSeric miao 		/* DRCMR for RX */
5948f58de7cSeric miao 		.start	= 15,
5958f58de7cSeric miao 		.end	= 15,
5968f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5978f58de7cSeric miao 	},
5988f58de7cSeric miao 	[3] = {
5998f58de7cSeric miao 		/* DRCMR for TX */
6008f58de7cSeric miao 		.start	= 16,
6018f58de7cSeric miao 		.end	= 16,
6028f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6038f58de7cSeric miao 	},
6048f58de7cSeric miao };
6058f58de7cSeric miao 
6068f58de7cSeric miao struct platform_device pxa27x_device_ssp2 = {
6078f58de7cSeric miao 	.name		= "pxa27x-ssp",
6088f58de7cSeric miao 	.id		= 1,
6098f58de7cSeric miao 	.dev		= {
6108f58de7cSeric miao 		.dma_mask = &pxa27x_ssp2_dma_mask,
6118f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
6128f58de7cSeric miao 	},
6138f58de7cSeric miao 	.resource	= pxa27x_resource_ssp2,
6148f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
6158f58de7cSeric miao };
6168f58de7cSeric miao 
6178f58de7cSeric miao static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
6188f58de7cSeric miao 
6198f58de7cSeric miao static struct resource pxa27x_resource_ssp3[] = {
6208f58de7cSeric miao 	[0] = {
6218f58de7cSeric miao 		.start	= 0x41900000,
6228f58de7cSeric miao 		.end	= 0x4190003f,
6238f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
6248f58de7cSeric miao 	},
6258f58de7cSeric miao 	[1] = {
6268f58de7cSeric miao 		.start	= IRQ_SSP3,
6278f58de7cSeric miao 		.end	= IRQ_SSP3,
6288f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
6298f58de7cSeric miao 	},
6308f58de7cSeric miao 	[2] = {
6318f58de7cSeric miao 		/* DRCMR for RX */
6328f58de7cSeric miao 		.start	= 66,
6338f58de7cSeric miao 		.end	= 66,
6348f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6358f58de7cSeric miao 	},
6368f58de7cSeric miao 	[3] = {
6378f58de7cSeric miao 		/* DRCMR for TX */
6388f58de7cSeric miao 		.start	= 67,
6398f58de7cSeric miao 		.end	= 67,
6408f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6418f58de7cSeric miao 	},
6428f58de7cSeric miao };
6438f58de7cSeric miao 
6448f58de7cSeric miao struct platform_device pxa27x_device_ssp3 = {
6458f58de7cSeric miao 	.name		= "pxa27x-ssp",
6468f58de7cSeric miao 	.id		= 2,
6478f58de7cSeric miao 	.dev		= {
6488f58de7cSeric miao 		.dma_mask = &pxa27x_ssp3_dma_mask,
6498f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
6508f58de7cSeric miao 	},
6518f58de7cSeric miao 	.resource	= pxa27x_resource_ssp3,
6528f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
6538f58de7cSeric miao };
6543f3acefbSGuennadi Liakhovetski 
65575540c1aSeric miao static struct resource pxa27x_resource_pwm0[] = {
65675540c1aSeric miao 	[0] = {
65775540c1aSeric miao 		.start	= 0x40b00000,
65875540c1aSeric miao 		.end	= 0x40b0001f,
65975540c1aSeric miao 		.flags	= IORESOURCE_MEM,
66075540c1aSeric miao 	},
66175540c1aSeric miao };
66275540c1aSeric miao 
66375540c1aSeric miao struct platform_device pxa27x_device_pwm0 = {
66475540c1aSeric miao 	.name		= "pxa27x-pwm",
66575540c1aSeric miao 	.id		= 0,
66675540c1aSeric miao 	.resource	= pxa27x_resource_pwm0,
66775540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm0),
66875540c1aSeric miao };
66975540c1aSeric miao 
67075540c1aSeric miao static struct resource pxa27x_resource_pwm1[] = {
67175540c1aSeric miao 	[0] = {
67275540c1aSeric miao 		.start	= 0x40c00000,
67375540c1aSeric miao 		.end	= 0x40c0001f,
67475540c1aSeric miao 		.flags	= IORESOURCE_MEM,
67575540c1aSeric miao 	},
67675540c1aSeric miao };
67775540c1aSeric miao 
67875540c1aSeric miao struct platform_device pxa27x_device_pwm1 = {
67975540c1aSeric miao 	.name		= "pxa27x-pwm",
68075540c1aSeric miao 	.id		= 1,
68175540c1aSeric miao 	.resource	= pxa27x_resource_pwm1,
68275540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm1),
68375540c1aSeric miao };
68475540c1aSeric miao 
6853f3acefbSGuennadi Liakhovetski static struct resource pxa27x_resource_camera[] = {
6863f3acefbSGuennadi Liakhovetski 	[0] = {
6873f3acefbSGuennadi Liakhovetski 		.start	= 0x50000000,
6883f3acefbSGuennadi Liakhovetski 		.end	= 0x50000fff,
6893f3acefbSGuennadi Liakhovetski 		.flags	= IORESOURCE_MEM,
6903f3acefbSGuennadi Liakhovetski 	},
6913f3acefbSGuennadi Liakhovetski 	[1] = {
6923f3acefbSGuennadi Liakhovetski 		.start	= IRQ_CAMERA,
6933f3acefbSGuennadi Liakhovetski 		.end	= IRQ_CAMERA,
6943f3acefbSGuennadi Liakhovetski 		.flags	= IORESOURCE_IRQ,
6953f3acefbSGuennadi Liakhovetski 	},
6963f3acefbSGuennadi Liakhovetski };
6973f3acefbSGuennadi Liakhovetski 
6983f3acefbSGuennadi Liakhovetski static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
6993f3acefbSGuennadi Liakhovetski 
7003f3acefbSGuennadi Liakhovetski static struct platform_device pxa27x_device_camera = {
7013f3acefbSGuennadi Liakhovetski 	.name		= "pxa27x-camera",
7023f3acefbSGuennadi Liakhovetski 	.id		= 0, /* This is used to put cameras on this interface */
7033f3acefbSGuennadi Liakhovetski 	.dev		= {
7043f3acefbSGuennadi Liakhovetski 		.dma_mask      		= &pxa27x_dma_mask_camera,
7053f3acefbSGuennadi Liakhovetski 		.coherent_dma_mask	= 0xffffffff,
7063f3acefbSGuennadi Liakhovetski 	},
7073f3acefbSGuennadi Liakhovetski 	.num_resources	= ARRAY_SIZE(pxa27x_resource_camera),
7083f3acefbSGuennadi Liakhovetski 	.resource	= pxa27x_resource_camera,
7093f3acefbSGuennadi Liakhovetski };
7103f3acefbSGuennadi Liakhovetski 
7113f3acefbSGuennadi Liakhovetski void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
7123f3acefbSGuennadi Liakhovetski {
7133f3acefbSGuennadi Liakhovetski 	pxa_register_device(&pxa27x_device_camera, info);
7143f3acefbSGuennadi Liakhovetski }
7158f58de7cSeric miao #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
7168f58de7cSeric miao 
7178f58de7cSeric miao #ifdef CONFIG_PXA3xx
7188f58de7cSeric miao static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
7198f58de7cSeric miao 
7208f58de7cSeric miao static struct resource pxa3xx_resource_ssp4[] = {
7218f58de7cSeric miao 	[0] = {
7228f58de7cSeric miao 		.start	= 0x41a00000,
7238f58de7cSeric miao 		.end	= 0x41a0003f,
7248f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
7258f58de7cSeric miao 	},
7268f58de7cSeric miao 	[1] = {
7278f58de7cSeric miao 		.start	= IRQ_SSP4,
7288f58de7cSeric miao 		.end	= IRQ_SSP4,
7298f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
7308f58de7cSeric miao 	},
7318f58de7cSeric miao 	[2] = {
7328f58de7cSeric miao 		/* DRCMR for RX */
7338f58de7cSeric miao 		.start	= 2,
7348f58de7cSeric miao 		.end	= 2,
7358f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7368f58de7cSeric miao 	},
7378f58de7cSeric miao 	[3] = {
7388f58de7cSeric miao 		/* DRCMR for TX */
7398f58de7cSeric miao 		.start	= 3,
7408f58de7cSeric miao 		.end	= 3,
7418f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7428f58de7cSeric miao 	},
7438f58de7cSeric miao };
7448f58de7cSeric miao 
7458f58de7cSeric miao struct platform_device pxa3xx_device_ssp4 = {
7468f58de7cSeric miao 	/* PXA3xx SSP is basically equivalent to PXA27x */
7478f58de7cSeric miao 	.name		= "pxa27x-ssp",
7488f58de7cSeric miao 	.id		= 3,
7498f58de7cSeric miao 	.dev		= {
7508f58de7cSeric miao 		.dma_mask = &pxa3xx_ssp4_dma_mask,
7518f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
7528f58de7cSeric miao 	},
7538f58de7cSeric miao 	.resource	= pxa3xx_resource_ssp4,
7548f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa3xx_resource_ssp4),
7558f58de7cSeric miao };
7568d33b055SBridge Wu 
7578d33b055SBridge Wu static struct resource pxa3xx_resources_mci2[] = {
7588d33b055SBridge Wu 	[0] = {
7598d33b055SBridge Wu 		.start	= 0x42000000,
7608d33b055SBridge Wu 		.end	= 0x42000fff,
7618d33b055SBridge Wu 		.flags	= IORESOURCE_MEM,
7628d33b055SBridge Wu 	},
7638d33b055SBridge Wu 	[1] = {
7648d33b055SBridge Wu 		.start	= IRQ_MMC2,
7658d33b055SBridge Wu 		.end	= IRQ_MMC2,
7668d33b055SBridge Wu 		.flags	= IORESOURCE_IRQ,
7678d33b055SBridge Wu 	},
7688d33b055SBridge Wu 	[2] = {
7698d33b055SBridge Wu 		.start	= 93,
7708d33b055SBridge Wu 		.end	= 93,
7718d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
7728d33b055SBridge Wu 	},
7738d33b055SBridge Wu 	[3] = {
7748d33b055SBridge Wu 		.start	= 94,
7758d33b055SBridge Wu 		.end	= 94,
7768d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
7778d33b055SBridge Wu 	},
7788d33b055SBridge Wu };
7798d33b055SBridge Wu 
7808d33b055SBridge Wu struct platform_device pxa3xx_device_mci2 = {
7818d33b055SBridge Wu 	.name		= "pxa2xx-mci",
7828d33b055SBridge Wu 	.id		= 1,
7838d33b055SBridge Wu 	.dev		= {
7848d33b055SBridge Wu 		.dma_mask = &pxamci_dmamask,
7858d33b055SBridge Wu 		.coherent_dma_mask =	0xffffffff,
7868d33b055SBridge Wu 	},
7878d33b055SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci2),
7888d33b055SBridge Wu 	.resource	= pxa3xx_resources_mci2,
7898d33b055SBridge Wu };
7908d33b055SBridge Wu 
7918d33b055SBridge Wu void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
7928d33b055SBridge Wu {
7938d33b055SBridge Wu 	pxa_register_device(&pxa3xx_device_mci2, info);
7948d33b055SBridge Wu }
7958d33b055SBridge Wu 
7965a1f21b1SBridge Wu static struct resource pxa3xx_resources_mci3[] = {
7975a1f21b1SBridge Wu 	[0] = {
7985a1f21b1SBridge Wu 		.start	= 0x42500000,
7995a1f21b1SBridge Wu 		.end	= 0x42500fff,
8005a1f21b1SBridge Wu 		.flags	= IORESOURCE_MEM,
8015a1f21b1SBridge Wu 	},
8025a1f21b1SBridge Wu 	[1] = {
8035a1f21b1SBridge Wu 		.start	= IRQ_MMC3,
8045a1f21b1SBridge Wu 		.end	= IRQ_MMC3,
8055a1f21b1SBridge Wu 		.flags	= IORESOURCE_IRQ,
8065a1f21b1SBridge Wu 	},
8075a1f21b1SBridge Wu 	[2] = {
8085a1f21b1SBridge Wu 		.start	= 100,
8095a1f21b1SBridge Wu 		.end	= 100,
8105a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
8115a1f21b1SBridge Wu 	},
8125a1f21b1SBridge Wu 	[3] = {
8135a1f21b1SBridge Wu 		.start	= 101,
8145a1f21b1SBridge Wu 		.end	= 101,
8155a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
8165a1f21b1SBridge Wu 	},
8175a1f21b1SBridge Wu };
8185a1f21b1SBridge Wu 
8195a1f21b1SBridge Wu struct platform_device pxa3xx_device_mci3 = {
8205a1f21b1SBridge Wu 	.name		= "pxa2xx-mci",
8215a1f21b1SBridge Wu 	.id		= 2,
8225a1f21b1SBridge Wu 	.dev		= {
8235a1f21b1SBridge Wu 		.dma_mask = &pxamci_dmamask,
8245a1f21b1SBridge Wu 		.coherent_dma_mask = 0xffffffff,
8255a1f21b1SBridge Wu 	},
8265a1f21b1SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci3),
8275a1f21b1SBridge Wu 	.resource	= pxa3xx_resources_mci3,
8285a1f21b1SBridge Wu };
8295a1f21b1SBridge Wu 
8305a1f21b1SBridge Wu void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
8315a1f21b1SBridge Wu {
8325a1f21b1SBridge Wu 	pxa_register_device(&pxa3xx_device_mci3, info);
8335a1f21b1SBridge Wu }
8345a1f21b1SBridge Wu 
835*9ae819a8SEric Miao static struct resource pxa3xx_resources_nand[] = {
836*9ae819a8SEric Miao 	[0] = {
837*9ae819a8SEric Miao 		.start	= 0x43100000,
838*9ae819a8SEric Miao 		.end	= 0x43100053,
839*9ae819a8SEric Miao 		.flags	= IORESOURCE_MEM,
840*9ae819a8SEric Miao 	},
841*9ae819a8SEric Miao 	[1] = {
842*9ae819a8SEric Miao 		.start	= IRQ_NAND,
843*9ae819a8SEric Miao 		.end	= IRQ_NAND,
844*9ae819a8SEric Miao 		.flags	= IORESOURCE_IRQ,
845*9ae819a8SEric Miao 	},
846*9ae819a8SEric Miao 	[2] = {
847*9ae819a8SEric Miao 		/* DRCMR for Data DMA */
848*9ae819a8SEric Miao 		.start	= 97,
849*9ae819a8SEric Miao 		.end	= 97,
850*9ae819a8SEric Miao 		.flags	= IORESOURCE_DMA,
851*9ae819a8SEric Miao 	},
852*9ae819a8SEric Miao 	[3] = {
853*9ae819a8SEric Miao 		/* DRCMR for Command DMA */
854*9ae819a8SEric Miao 		.start	= 99,
855*9ae819a8SEric Miao 		.end	= 99,
856*9ae819a8SEric Miao 		.flags	= IORESOURCE_DMA,
857*9ae819a8SEric Miao 	},
858*9ae819a8SEric Miao };
859*9ae819a8SEric Miao 
860*9ae819a8SEric Miao static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
861*9ae819a8SEric Miao 
862*9ae819a8SEric Miao struct platform_device pxa3xx_device_nand = {
863*9ae819a8SEric Miao 	.name		= "pxa3xx-nand",
864*9ae819a8SEric Miao 	.id		= -1,
865*9ae819a8SEric Miao 	.dev		= {
866*9ae819a8SEric Miao 		.dma_mask = &pxa3xx_nand_dma_mask,
867*9ae819a8SEric Miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
868*9ae819a8SEric Miao 	},
869*9ae819a8SEric Miao 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_nand),
870*9ae819a8SEric Miao 	.resource	= pxa3xx_resources_nand,
871*9ae819a8SEric Miao };
872*9ae819a8SEric Miao 
873*9ae819a8SEric Miao void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
874*9ae819a8SEric Miao {
875*9ae819a8SEric Miao 	pxa_register_device(&pxa3xx_device_nand, info);
876*9ae819a8SEric Miao }
8778f58de7cSeric miao #endif /* CONFIG_PXA3xx */
878e172274cSGuennadi Liakhovetski 
879e172274cSGuennadi Liakhovetski /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
880e172274cSGuennadi Liakhovetski  * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
881e172274cSGuennadi Liakhovetski void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
882e172274cSGuennadi Liakhovetski {
883e172274cSGuennadi Liakhovetski 	struct platform_device *pd;
884e172274cSGuennadi Liakhovetski 
885e172274cSGuennadi Liakhovetski 	pd = platform_device_alloc("pxa2xx-spi", id);
886e172274cSGuennadi Liakhovetski 	if (pd == NULL) {
887e172274cSGuennadi Liakhovetski 		printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
888e172274cSGuennadi Liakhovetski 		       id);
889e172274cSGuennadi Liakhovetski 		return;
890e172274cSGuennadi Liakhovetski 	}
891e172274cSGuennadi Liakhovetski 
892e172274cSGuennadi Liakhovetski 	pd->dev.platform_data = info;
893e172274cSGuennadi Liakhovetski 	platform_device_add(pd);
894e172274cSGuennadi Liakhovetski }
895