xref: /linux/arch/arm/mach-pxa/devices.c (revision 7a8576204333d133d58cbcc59dacf49a5546e3e4)
18f58de7cSeric miao #include <linux/module.h>
28f58de7cSeric miao #include <linux/kernel.h>
38f58de7cSeric miao #include <linux/init.h>
48f58de7cSeric miao #include <linux/platform_device.h>
58f58de7cSeric miao #include <linux/dma-mapping.h>
68f58de7cSeric miao 
78f58de7cSeric miao #include <asm/arch/gpio.h>
88f58de7cSeric miao #include <asm/arch/udc.h>
98f58de7cSeric miao #include <asm/arch/pxafb.h>
108f58de7cSeric miao #include <asm/arch/mmc.h>
118f58de7cSeric miao #include <asm/arch/irda.h>
128f58de7cSeric miao #include <asm/arch/i2c.h>
13bc3a5959SPhilipp Zabel #include <asm/arch/mfp-pxa27x.h>
14cd5604d5Seric miao #include <asm/arch/ohci.h>
1537320980Seric miao #include <asm/arch/pxa27x_keypad.h>
163f3acefbSGuennadi Liakhovetski #include <asm/arch/camera.h>
178f58de7cSeric miao 
188f58de7cSeric miao #include "devices.h"
19bc3a5959SPhilipp Zabel #include "generic.h"
208f58de7cSeric miao 
218f58de7cSeric miao void __init pxa_register_device(struct platform_device *dev, void *data)
228f58de7cSeric miao {
238f58de7cSeric miao 	int ret;
248f58de7cSeric miao 
258f58de7cSeric miao 	dev->dev.platform_data = data;
268f58de7cSeric miao 
278f58de7cSeric miao 	ret = platform_device_register(dev);
288f58de7cSeric miao 	if (ret)
298f58de7cSeric miao 		dev_err(&dev->dev, "unable to register device: %d\n", ret);
308f58de7cSeric miao }
318f58de7cSeric miao 
328f58de7cSeric miao static struct resource pxamci_resources[] = {
338f58de7cSeric miao 	[0] = {
348f58de7cSeric miao 		.start	= 0x41100000,
358f58de7cSeric miao 		.end	= 0x41100fff,
368f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
378f58de7cSeric miao 	},
388f58de7cSeric miao 	[1] = {
398f58de7cSeric miao 		.start	= IRQ_MMC,
408f58de7cSeric miao 		.end	= IRQ_MMC,
418f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
428f58de7cSeric miao 	},
438f58de7cSeric miao 	[2] = {
448f58de7cSeric miao 		.start	= 21,
458f58de7cSeric miao 		.end	= 21,
468f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
478f58de7cSeric miao 	},
488f58de7cSeric miao 	[3] = {
498f58de7cSeric miao 		.start	= 22,
508f58de7cSeric miao 		.end	= 22,
518f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
528f58de7cSeric miao 	},
538f58de7cSeric miao };
548f58de7cSeric miao 
558f58de7cSeric miao static u64 pxamci_dmamask = 0xffffffffUL;
568f58de7cSeric miao 
578f58de7cSeric miao struct platform_device pxa_device_mci = {
588f58de7cSeric miao 	.name		= "pxa2xx-mci",
59fafc9d3fSBridge Wu 	.id		= 0,
608f58de7cSeric miao 	.dev		= {
618f58de7cSeric miao 		.dma_mask = &pxamci_dmamask,
628f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
638f58de7cSeric miao 	},
648f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxamci_resources),
658f58de7cSeric miao 	.resource	= pxamci_resources,
668f58de7cSeric miao };
678f58de7cSeric miao 
688f58de7cSeric miao void __init pxa_set_mci_info(struct pxamci_platform_data *info)
698f58de7cSeric miao {
708f58de7cSeric miao 	pxa_register_device(&pxa_device_mci, info);
718f58de7cSeric miao }
728f58de7cSeric miao 
738f58de7cSeric miao 
748f58de7cSeric miao static struct pxa2xx_udc_mach_info pxa_udc_info;
758f58de7cSeric miao 
768f58de7cSeric miao void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
778f58de7cSeric miao {
788f58de7cSeric miao 	memcpy(&pxa_udc_info, info, sizeof *info);
798f58de7cSeric miao }
808f58de7cSeric miao 
818f58de7cSeric miao static struct resource pxa2xx_udc_resources[] = {
828f58de7cSeric miao 	[0] = {
838f58de7cSeric miao 		.start	= 0x40600000,
848f58de7cSeric miao 		.end	= 0x4060ffff,
858f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
868f58de7cSeric miao 	},
878f58de7cSeric miao 	[1] = {
888f58de7cSeric miao 		.start	= IRQ_USB,
898f58de7cSeric miao 		.end	= IRQ_USB,
908f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
918f58de7cSeric miao 	},
928f58de7cSeric miao };
938f58de7cSeric miao 
948f58de7cSeric miao static u64 udc_dma_mask = ~(u32)0;
958f58de7cSeric miao 
96*7a857620SPhilipp Zabel struct platform_device pxa25x_device_udc = {
97*7a857620SPhilipp Zabel 	.name		= "pxa25x-udc",
98*7a857620SPhilipp Zabel 	.id		= -1,
99*7a857620SPhilipp Zabel 	.resource	= pxa2xx_udc_resources,
100*7a857620SPhilipp Zabel 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
101*7a857620SPhilipp Zabel 	.dev		=  {
102*7a857620SPhilipp Zabel 		.platform_data	= &pxa_udc_info,
103*7a857620SPhilipp Zabel 		.dma_mask	= &udc_dma_mask,
104*7a857620SPhilipp Zabel 	}
105*7a857620SPhilipp Zabel };
106*7a857620SPhilipp Zabel 
107*7a857620SPhilipp Zabel struct platform_device pxa27x_device_udc = {
108*7a857620SPhilipp Zabel 	.name		= "pxa27x-udc",
1098f58de7cSeric miao 	.id		= -1,
1108f58de7cSeric miao 	.resource	= pxa2xx_udc_resources,
1118f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
1128f58de7cSeric miao 	.dev		=  {
1138f58de7cSeric miao 		.platform_data	= &pxa_udc_info,
1148f58de7cSeric miao 		.dma_mask	= &udc_dma_mask,
1158f58de7cSeric miao 	}
1168f58de7cSeric miao };
1178f58de7cSeric miao 
1188f58de7cSeric miao static struct resource pxafb_resources[] = {
1198f58de7cSeric miao 	[0] = {
1208f58de7cSeric miao 		.start	= 0x44000000,
1218f58de7cSeric miao 		.end	= 0x4400ffff,
1228f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1238f58de7cSeric miao 	},
1248f58de7cSeric miao 	[1] = {
1258f58de7cSeric miao 		.start	= IRQ_LCD,
1268f58de7cSeric miao 		.end	= IRQ_LCD,
1278f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1288f58de7cSeric miao 	},
1298f58de7cSeric miao };
1308f58de7cSeric miao 
1318f58de7cSeric miao static u64 fb_dma_mask = ~(u64)0;
1328f58de7cSeric miao 
1338f58de7cSeric miao struct platform_device pxa_device_fb = {
1348f58de7cSeric miao 	.name		= "pxa2xx-fb",
1358f58de7cSeric miao 	.id		= -1,
1368f58de7cSeric miao 	.dev		= {
1378f58de7cSeric miao 		.dma_mask	= &fb_dma_mask,
1388f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
1398f58de7cSeric miao 	},
1408f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxafb_resources),
1418f58de7cSeric miao 	.resource	= pxafb_resources,
1428f58de7cSeric miao };
1438f58de7cSeric miao 
1448f58de7cSeric miao void __init set_pxa_fb_info(struct pxafb_mach_info *info)
1458f58de7cSeric miao {
1468f58de7cSeric miao 	pxa_register_device(&pxa_device_fb, info);
1478f58de7cSeric miao }
1488f58de7cSeric miao 
1498f58de7cSeric miao void __init set_pxa_fb_parent(struct device *parent_dev)
1508f58de7cSeric miao {
1518f58de7cSeric miao 	pxa_device_fb.dev.parent = parent_dev;
1528f58de7cSeric miao }
1538f58de7cSeric miao 
1548f58de7cSeric miao static struct resource pxa_resource_ffuart[] = {
1558f58de7cSeric miao 	{
1568f58de7cSeric miao 		.start	= __PREG(FFUART),
1578f58de7cSeric miao 		.end	= __PREG(FFUART) + 35,
1588f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1598f58de7cSeric miao 	}, {
1608f58de7cSeric miao 		.start	= IRQ_FFUART,
1618f58de7cSeric miao 		.end	= IRQ_FFUART,
1628f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1638f58de7cSeric miao 	}
1648f58de7cSeric miao };
1658f58de7cSeric miao 
1668f58de7cSeric miao struct platform_device pxa_device_ffuart= {
1678f58de7cSeric miao 	.name		= "pxa2xx-uart",
1688f58de7cSeric miao 	.id		= 0,
1698f58de7cSeric miao 	.resource	= pxa_resource_ffuart,
1708f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_ffuart),
1718f58de7cSeric miao };
1728f58de7cSeric miao 
1738f58de7cSeric miao static struct resource pxa_resource_btuart[] = {
1748f58de7cSeric miao 	{
1758f58de7cSeric miao 		.start	= __PREG(BTUART),
1768f58de7cSeric miao 		.end	= __PREG(BTUART) + 35,
1778f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1788f58de7cSeric miao 	}, {
1798f58de7cSeric miao 		.start	= IRQ_BTUART,
1808f58de7cSeric miao 		.end	= IRQ_BTUART,
1818f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1828f58de7cSeric miao 	}
1838f58de7cSeric miao };
1848f58de7cSeric miao 
1858f58de7cSeric miao struct platform_device pxa_device_btuart = {
1868f58de7cSeric miao 	.name		= "pxa2xx-uart",
1878f58de7cSeric miao 	.id		= 1,
1888f58de7cSeric miao 	.resource	= pxa_resource_btuart,
1898f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_btuart),
1908f58de7cSeric miao };
1918f58de7cSeric miao 
1928f58de7cSeric miao static struct resource pxa_resource_stuart[] = {
1938f58de7cSeric miao 	{
1948f58de7cSeric miao 		.start	= __PREG(STUART),
1958f58de7cSeric miao 		.end	= __PREG(STUART) + 35,
1968f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1978f58de7cSeric miao 	}, {
1988f58de7cSeric miao 		.start	= IRQ_STUART,
1998f58de7cSeric miao 		.end	= IRQ_STUART,
2008f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2018f58de7cSeric miao 	}
2028f58de7cSeric miao };
2038f58de7cSeric miao 
2048f58de7cSeric miao struct platform_device pxa_device_stuart = {
2058f58de7cSeric miao 	.name		= "pxa2xx-uart",
2068f58de7cSeric miao 	.id		= 2,
2078f58de7cSeric miao 	.resource	= pxa_resource_stuart,
2088f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_stuart),
2098f58de7cSeric miao };
2108f58de7cSeric miao 
2118f58de7cSeric miao static struct resource pxa_resource_hwuart[] = {
2128f58de7cSeric miao 	{
2138f58de7cSeric miao 		.start	= __PREG(HWUART),
2148f58de7cSeric miao 		.end	= __PREG(HWUART) + 47,
2158f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2168f58de7cSeric miao 	}, {
2178f58de7cSeric miao 		.start	= IRQ_HWUART,
2188f58de7cSeric miao 		.end	= IRQ_HWUART,
2198f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2208f58de7cSeric miao 	}
2218f58de7cSeric miao };
2228f58de7cSeric miao 
2238f58de7cSeric miao struct platform_device pxa_device_hwuart = {
2248f58de7cSeric miao 	.name		= "pxa2xx-uart",
2258f58de7cSeric miao 	.id		= 3,
2268f58de7cSeric miao 	.resource	= pxa_resource_hwuart,
2278f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
2288f58de7cSeric miao };
2298f58de7cSeric miao 
2308f58de7cSeric miao static struct resource pxai2c_resources[] = {
2318f58de7cSeric miao 	{
2328f58de7cSeric miao 		.start	= 0x40301680,
2338f58de7cSeric miao 		.end	= 0x403016a3,
2348f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2358f58de7cSeric miao 	}, {
2368f58de7cSeric miao 		.start	= IRQ_I2C,
2378f58de7cSeric miao 		.end	= IRQ_I2C,
2388f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2398f58de7cSeric miao 	},
2408f58de7cSeric miao };
2418f58de7cSeric miao 
2428f58de7cSeric miao struct platform_device pxa_device_i2c = {
2438f58de7cSeric miao 	.name		= "pxa2xx-i2c",
2448f58de7cSeric miao 	.id		= 0,
2458f58de7cSeric miao 	.resource	= pxai2c_resources,
2468f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2c_resources),
2478f58de7cSeric miao };
2488f58de7cSeric miao 
249bc3a5959SPhilipp Zabel static unsigned long pxa27x_i2c_mfp_cfg[] = {
250bc3a5959SPhilipp Zabel 	GPIO117_I2C_SCL,
251bc3a5959SPhilipp Zabel 	GPIO118_I2C_SDA,
252bc3a5959SPhilipp Zabel };
253bc3a5959SPhilipp Zabel 
2548f58de7cSeric miao void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
2558f58de7cSeric miao {
256bc3a5959SPhilipp Zabel 	if (cpu_is_pxa27x())
257bc3a5959SPhilipp Zabel 		pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg));
2588f58de7cSeric miao 	pxa_register_device(&pxa_device_i2c, info);
2598f58de7cSeric miao }
2608f58de7cSeric miao 
2618f58de7cSeric miao static struct resource pxai2s_resources[] = {
2628f58de7cSeric miao 	{
2638f58de7cSeric miao 		.start	= 0x40400000,
2648f58de7cSeric miao 		.end	= 0x40400083,
2658f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2668f58de7cSeric miao 	}, {
2678f58de7cSeric miao 		.start	= IRQ_I2S,
2688f58de7cSeric miao 		.end	= IRQ_I2S,
2698f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2708f58de7cSeric miao 	},
2718f58de7cSeric miao };
2728f58de7cSeric miao 
2738f58de7cSeric miao struct platform_device pxa_device_i2s = {
2748f58de7cSeric miao 	.name		= "pxa2xx-i2s",
2758f58de7cSeric miao 	.id		= -1,
2768f58de7cSeric miao 	.resource	= pxai2s_resources,
2778f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2s_resources),
2788f58de7cSeric miao };
2798f58de7cSeric miao 
2808f58de7cSeric miao static u64 pxaficp_dmamask = ~(u32)0;
2818f58de7cSeric miao 
2828f58de7cSeric miao struct platform_device pxa_device_ficp = {
2838f58de7cSeric miao 	.name		= "pxa2xx-ir",
2848f58de7cSeric miao 	.id		= -1,
2858f58de7cSeric miao 	.dev		= {
2868f58de7cSeric miao 		.dma_mask = &pxaficp_dmamask,
2878f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
2888f58de7cSeric miao 	},
2898f58de7cSeric miao };
2908f58de7cSeric miao 
2918f58de7cSeric miao void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
2928f58de7cSeric miao {
2938f58de7cSeric miao 	pxa_register_device(&pxa_device_ficp, info);
2948f58de7cSeric miao }
2958f58de7cSeric miao 
2968f58de7cSeric miao struct platform_device pxa_device_rtc = {
2978f58de7cSeric miao 	.name		= "sa1100-rtc",
2988f58de7cSeric miao 	.id		= -1,
2998f58de7cSeric miao };
3008f58de7cSeric miao 
3018f58de7cSeric miao #ifdef CONFIG_PXA25x
3028f58de7cSeric miao 
30375540c1aSeric miao static struct resource pxa25x_resource_pwm0[] = {
30475540c1aSeric miao 	[0] = {
30575540c1aSeric miao 		.start	= 0x40b00000,
30675540c1aSeric miao 		.end	= 0x40b0000f,
30775540c1aSeric miao 		.flags	= IORESOURCE_MEM,
30875540c1aSeric miao 	},
30975540c1aSeric miao };
31075540c1aSeric miao 
31175540c1aSeric miao struct platform_device pxa25x_device_pwm0 = {
31275540c1aSeric miao 	.name		= "pxa25x-pwm",
31375540c1aSeric miao 	.id		= 0,
31475540c1aSeric miao 	.resource	= pxa25x_resource_pwm0,
31575540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm0),
31675540c1aSeric miao };
31775540c1aSeric miao 
31875540c1aSeric miao static struct resource pxa25x_resource_pwm1[] = {
31975540c1aSeric miao 	[0] = {
32075540c1aSeric miao 		.start	= 0x40c00000,
32175540c1aSeric miao 		.end	= 0x40c0000f,
32275540c1aSeric miao 		.flags	= IORESOURCE_MEM,
32375540c1aSeric miao 	},
32475540c1aSeric miao };
32575540c1aSeric miao 
32675540c1aSeric miao struct platform_device pxa25x_device_pwm1 = {
32775540c1aSeric miao 	.name		= "pxa25x-pwm",
32875540c1aSeric miao 	.id		= 1,
32975540c1aSeric miao 	.resource	= pxa25x_resource_pwm1,
33075540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm1),
33175540c1aSeric miao };
33275540c1aSeric miao 
3338f58de7cSeric miao static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
3348f58de7cSeric miao 
3358f58de7cSeric miao static struct resource pxa25x_resource_ssp[] = {
3368f58de7cSeric miao 	[0] = {
3378f58de7cSeric miao 		.start	= 0x41000000,
3388f58de7cSeric miao 		.end	= 0x4100001f,
3398f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3408f58de7cSeric miao 	},
3418f58de7cSeric miao 	[1] = {
3428f58de7cSeric miao 		.start	= IRQ_SSP,
3438f58de7cSeric miao 		.end	= IRQ_SSP,
3448f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3458f58de7cSeric miao 	},
3468f58de7cSeric miao 	[2] = {
3478f58de7cSeric miao 		/* DRCMR for RX */
3488f58de7cSeric miao 		.start	= 13,
3498f58de7cSeric miao 		.end	= 13,
3508f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
3518f58de7cSeric miao 	},
3528f58de7cSeric miao 	[3] = {
3538f58de7cSeric miao 		/* DRCMR for TX */
3548f58de7cSeric miao 		.start	= 14,
3558f58de7cSeric miao 		.end	= 14,
3568f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
3578f58de7cSeric miao 	},
3588f58de7cSeric miao };
3598f58de7cSeric miao 
3608f58de7cSeric miao struct platform_device pxa25x_device_ssp = {
3618f58de7cSeric miao 	.name		= "pxa25x-ssp",
3628f58de7cSeric miao 	.id		= 0,
3638f58de7cSeric miao 	.dev		= {
3648f58de7cSeric miao 		.dma_mask = &pxa25x_ssp_dma_mask,
3658f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
3668f58de7cSeric miao 	},
3678f58de7cSeric miao 	.resource	= pxa25x_resource_ssp,
3688f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_ssp),
3698f58de7cSeric miao };
3708f58de7cSeric miao 
3718f58de7cSeric miao static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
3728f58de7cSeric miao 
3738f58de7cSeric miao static struct resource pxa25x_resource_nssp[] = {
3748f58de7cSeric miao 	[0] = {
3758f58de7cSeric miao 		.start	= 0x41400000,
3768f58de7cSeric miao 		.end	= 0x4140002f,
3778f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3788f58de7cSeric miao 	},
3798f58de7cSeric miao 	[1] = {
3808f58de7cSeric miao 		.start	= IRQ_NSSP,
3818f58de7cSeric miao 		.end	= IRQ_NSSP,
3828f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3838f58de7cSeric miao 	},
3848f58de7cSeric miao 	[2] = {
3858f58de7cSeric miao 		/* DRCMR for RX */
3868f58de7cSeric miao 		.start	= 15,
3878f58de7cSeric miao 		.end	= 15,
3888f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
3898f58de7cSeric miao 	},
3908f58de7cSeric miao 	[3] = {
3918f58de7cSeric miao 		/* DRCMR for TX */
3928f58de7cSeric miao 		.start	= 16,
3938f58de7cSeric miao 		.end	= 16,
3948f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
3958f58de7cSeric miao 	},
3968f58de7cSeric miao };
3978f58de7cSeric miao 
3988f58de7cSeric miao struct platform_device pxa25x_device_nssp = {
3998f58de7cSeric miao 	.name		= "pxa25x-nssp",
4008f58de7cSeric miao 	.id		= 1,
4018f58de7cSeric miao 	.dev		= {
4028f58de7cSeric miao 		.dma_mask = &pxa25x_nssp_dma_mask,
4038f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
4048f58de7cSeric miao 	},
4058f58de7cSeric miao 	.resource	= pxa25x_resource_nssp,
4068f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_nssp),
4078f58de7cSeric miao };
4088f58de7cSeric miao 
4098f58de7cSeric miao static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
4108f58de7cSeric miao 
4118f58de7cSeric miao static struct resource pxa25x_resource_assp[] = {
4128f58de7cSeric miao 	[0] = {
4138f58de7cSeric miao 		.start	= 0x41500000,
4148f58de7cSeric miao 		.end	= 0x4150002f,
4158f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
4168f58de7cSeric miao 	},
4178f58de7cSeric miao 	[1] = {
4188f58de7cSeric miao 		.start	= IRQ_ASSP,
4198f58de7cSeric miao 		.end	= IRQ_ASSP,
4208f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
4218f58de7cSeric miao 	},
4228f58de7cSeric miao 	[2] = {
4238f58de7cSeric miao 		/* DRCMR for RX */
4248f58de7cSeric miao 		.start	= 23,
4258f58de7cSeric miao 		.end	= 23,
4268f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
4278f58de7cSeric miao 	},
4288f58de7cSeric miao 	[3] = {
4298f58de7cSeric miao 		/* DRCMR for TX */
4308f58de7cSeric miao 		.start	= 24,
4318f58de7cSeric miao 		.end	= 24,
4328f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
4338f58de7cSeric miao 	},
4348f58de7cSeric miao };
4358f58de7cSeric miao 
4368f58de7cSeric miao struct platform_device pxa25x_device_assp = {
4378f58de7cSeric miao 	/* ASSP is basically equivalent to NSSP */
4388f58de7cSeric miao 	.name		= "pxa25x-nssp",
4398f58de7cSeric miao 	.id		= 2,
4408f58de7cSeric miao 	.dev		= {
4418f58de7cSeric miao 		.dma_mask = &pxa25x_assp_dma_mask,
4428f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
4438f58de7cSeric miao 	},
4448f58de7cSeric miao 	.resource	= pxa25x_resource_assp,
4458f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_assp),
4468f58de7cSeric miao };
4478f58de7cSeric miao #endif /* CONFIG_PXA25x */
4488f58de7cSeric miao 
4498f58de7cSeric miao #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
4508f58de7cSeric miao 
45137320980Seric miao static struct resource pxa27x_resource_keypad[] = {
45237320980Seric miao 	[0] = {
45337320980Seric miao 		.start	= 0x41500000,
45437320980Seric miao 		.end	= 0x4150004c,
45537320980Seric miao 		.flags	= IORESOURCE_MEM,
45637320980Seric miao 	},
45737320980Seric miao 	[1] = {
45837320980Seric miao 		.start	= IRQ_KEYPAD,
45937320980Seric miao 		.end	= IRQ_KEYPAD,
46037320980Seric miao 		.flags	= IORESOURCE_IRQ,
46137320980Seric miao 	},
46237320980Seric miao };
46337320980Seric miao 
46437320980Seric miao struct platform_device pxa27x_device_keypad = {
46537320980Seric miao 	.name		= "pxa27x-keypad",
46637320980Seric miao 	.id		= -1,
46737320980Seric miao 	.resource	= pxa27x_resource_keypad,
46837320980Seric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_keypad),
46937320980Seric miao };
47037320980Seric miao 
47137320980Seric miao void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
47237320980Seric miao {
47337320980Seric miao 	pxa_register_device(&pxa27x_device_keypad, info);
47437320980Seric miao }
47537320980Seric miao 
476ec68e45bSeric miao static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
477ec68e45bSeric miao 
478ec68e45bSeric miao static struct resource pxa27x_resource_ohci[] = {
479ec68e45bSeric miao 	[0] = {
480ec68e45bSeric miao 		.start  = 0x4C000000,
481ec68e45bSeric miao 		.end    = 0x4C00ff6f,
482ec68e45bSeric miao 		.flags  = IORESOURCE_MEM,
483ec68e45bSeric miao 	},
484ec68e45bSeric miao 	[1] = {
485ec68e45bSeric miao 		.start  = IRQ_USBH1,
486ec68e45bSeric miao 		.end    = IRQ_USBH1,
487ec68e45bSeric miao 		.flags  = IORESOURCE_IRQ,
488ec68e45bSeric miao 	},
489ec68e45bSeric miao };
490ec68e45bSeric miao 
491ec68e45bSeric miao struct platform_device pxa27x_device_ohci = {
492ec68e45bSeric miao 	.name		= "pxa27x-ohci",
493ec68e45bSeric miao 	.id		= -1,
494ec68e45bSeric miao 	.dev		= {
495ec68e45bSeric miao 		.dma_mask = &pxa27x_ohci_dma_mask,
496ec68e45bSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
497ec68e45bSeric miao 	},
498ec68e45bSeric miao 	.num_resources  = ARRAY_SIZE(pxa27x_resource_ohci),
499ec68e45bSeric miao 	.resource       = pxa27x_resource_ohci,
500ec68e45bSeric miao };
501ec68e45bSeric miao 
502ec68e45bSeric miao void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
503ec68e45bSeric miao {
504ec68e45bSeric miao 	pxa_register_device(&pxa27x_device_ohci, info);
505ec68e45bSeric miao }
506ec68e45bSeric miao 
5078f58de7cSeric miao static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
5088f58de7cSeric miao 
5098f58de7cSeric miao static struct resource pxa27x_resource_ssp1[] = {
5108f58de7cSeric miao 	[0] = {
5118f58de7cSeric miao 		.start	= 0x41000000,
5128f58de7cSeric miao 		.end	= 0x4100003f,
5138f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5148f58de7cSeric miao 	},
5158f58de7cSeric miao 	[1] = {
5168f58de7cSeric miao 		.start	= IRQ_SSP,
5178f58de7cSeric miao 		.end	= IRQ_SSP,
5188f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5198f58de7cSeric miao 	},
5208f58de7cSeric miao 	[2] = {
5218f58de7cSeric miao 		/* DRCMR for RX */
5228f58de7cSeric miao 		.start	= 13,
5238f58de7cSeric miao 		.end	= 13,
5248f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5258f58de7cSeric miao 	},
5268f58de7cSeric miao 	[3] = {
5278f58de7cSeric miao 		/* DRCMR for TX */
5288f58de7cSeric miao 		.start	= 14,
5298f58de7cSeric miao 		.end	= 14,
5308f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5318f58de7cSeric miao 	},
5328f58de7cSeric miao };
5338f58de7cSeric miao 
5348f58de7cSeric miao struct platform_device pxa27x_device_ssp1 = {
5358f58de7cSeric miao 	.name		= "pxa27x-ssp",
5368f58de7cSeric miao 	.id		= 0,
5378f58de7cSeric miao 	.dev		= {
5388f58de7cSeric miao 		.dma_mask = &pxa27x_ssp1_dma_mask,
5398f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
5408f58de7cSeric miao 	},
5418f58de7cSeric miao 	.resource	= pxa27x_resource_ssp1,
5428f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
5438f58de7cSeric miao };
5448f58de7cSeric miao 
5458f58de7cSeric miao static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
5468f58de7cSeric miao 
5478f58de7cSeric miao static struct resource pxa27x_resource_ssp2[] = {
5488f58de7cSeric miao 	[0] = {
5498f58de7cSeric miao 		.start	= 0x41700000,
5508f58de7cSeric miao 		.end	= 0x4170003f,
5518f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5528f58de7cSeric miao 	},
5538f58de7cSeric miao 	[1] = {
5548f58de7cSeric miao 		.start	= IRQ_SSP2,
5558f58de7cSeric miao 		.end	= IRQ_SSP2,
5568f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5578f58de7cSeric miao 	},
5588f58de7cSeric miao 	[2] = {
5598f58de7cSeric miao 		/* DRCMR for RX */
5608f58de7cSeric miao 		.start	= 15,
5618f58de7cSeric miao 		.end	= 15,
5628f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5638f58de7cSeric miao 	},
5648f58de7cSeric miao 	[3] = {
5658f58de7cSeric miao 		/* DRCMR for TX */
5668f58de7cSeric miao 		.start	= 16,
5678f58de7cSeric miao 		.end	= 16,
5688f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5698f58de7cSeric miao 	},
5708f58de7cSeric miao };
5718f58de7cSeric miao 
5728f58de7cSeric miao struct platform_device pxa27x_device_ssp2 = {
5738f58de7cSeric miao 	.name		= "pxa27x-ssp",
5748f58de7cSeric miao 	.id		= 1,
5758f58de7cSeric miao 	.dev		= {
5768f58de7cSeric miao 		.dma_mask = &pxa27x_ssp2_dma_mask,
5778f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
5788f58de7cSeric miao 	},
5798f58de7cSeric miao 	.resource	= pxa27x_resource_ssp2,
5808f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
5818f58de7cSeric miao };
5828f58de7cSeric miao 
5838f58de7cSeric miao static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
5848f58de7cSeric miao 
5858f58de7cSeric miao static struct resource pxa27x_resource_ssp3[] = {
5868f58de7cSeric miao 	[0] = {
5878f58de7cSeric miao 		.start	= 0x41900000,
5888f58de7cSeric miao 		.end	= 0x4190003f,
5898f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5908f58de7cSeric miao 	},
5918f58de7cSeric miao 	[1] = {
5928f58de7cSeric miao 		.start	= IRQ_SSP3,
5938f58de7cSeric miao 		.end	= IRQ_SSP3,
5948f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5958f58de7cSeric miao 	},
5968f58de7cSeric miao 	[2] = {
5978f58de7cSeric miao 		/* DRCMR for RX */
5988f58de7cSeric miao 		.start	= 66,
5998f58de7cSeric miao 		.end	= 66,
6008f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6018f58de7cSeric miao 	},
6028f58de7cSeric miao 	[3] = {
6038f58de7cSeric miao 		/* DRCMR for TX */
6048f58de7cSeric miao 		.start	= 67,
6058f58de7cSeric miao 		.end	= 67,
6068f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6078f58de7cSeric miao 	},
6088f58de7cSeric miao };
6098f58de7cSeric miao 
6108f58de7cSeric miao struct platform_device pxa27x_device_ssp3 = {
6118f58de7cSeric miao 	.name		= "pxa27x-ssp",
6128f58de7cSeric miao 	.id		= 2,
6138f58de7cSeric miao 	.dev		= {
6148f58de7cSeric miao 		.dma_mask = &pxa27x_ssp3_dma_mask,
6158f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
6168f58de7cSeric miao 	},
6178f58de7cSeric miao 	.resource	= pxa27x_resource_ssp3,
6188f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
6198f58de7cSeric miao };
6203f3acefbSGuennadi Liakhovetski 
62175540c1aSeric miao static struct resource pxa27x_resource_pwm0[] = {
62275540c1aSeric miao 	[0] = {
62375540c1aSeric miao 		.start	= 0x40b00000,
62475540c1aSeric miao 		.end	= 0x40b0001f,
62575540c1aSeric miao 		.flags	= IORESOURCE_MEM,
62675540c1aSeric miao 	},
62775540c1aSeric miao };
62875540c1aSeric miao 
62975540c1aSeric miao struct platform_device pxa27x_device_pwm0 = {
63075540c1aSeric miao 	.name		= "pxa27x-pwm",
63175540c1aSeric miao 	.id		= 0,
63275540c1aSeric miao 	.resource	= pxa27x_resource_pwm0,
63375540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm0),
63475540c1aSeric miao };
63575540c1aSeric miao 
63675540c1aSeric miao static struct resource pxa27x_resource_pwm1[] = {
63775540c1aSeric miao 	[0] = {
63875540c1aSeric miao 		.start	= 0x40c00000,
63975540c1aSeric miao 		.end	= 0x40c0001f,
64075540c1aSeric miao 		.flags	= IORESOURCE_MEM,
64175540c1aSeric miao 	},
64275540c1aSeric miao };
64375540c1aSeric miao 
64475540c1aSeric miao struct platform_device pxa27x_device_pwm1 = {
64575540c1aSeric miao 	.name		= "pxa27x-pwm",
64675540c1aSeric miao 	.id		= 1,
64775540c1aSeric miao 	.resource	= pxa27x_resource_pwm1,
64875540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm1),
64975540c1aSeric miao };
65075540c1aSeric miao 
6513f3acefbSGuennadi Liakhovetski static struct resource pxa27x_resource_camera[] = {
6523f3acefbSGuennadi Liakhovetski 	[0] = {
6533f3acefbSGuennadi Liakhovetski 		.start	= 0x50000000,
6543f3acefbSGuennadi Liakhovetski 		.end	= 0x50000fff,
6553f3acefbSGuennadi Liakhovetski 		.flags	= IORESOURCE_MEM,
6563f3acefbSGuennadi Liakhovetski 	},
6573f3acefbSGuennadi Liakhovetski 	[1] = {
6583f3acefbSGuennadi Liakhovetski 		.start	= IRQ_CAMERA,
6593f3acefbSGuennadi Liakhovetski 		.end	= IRQ_CAMERA,
6603f3acefbSGuennadi Liakhovetski 		.flags	= IORESOURCE_IRQ,
6613f3acefbSGuennadi Liakhovetski 	},
6623f3acefbSGuennadi Liakhovetski };
6633f3acefbSGuennadi Liakhovetski 
6643f3acefbSGuennadi Liakhovetski static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
6653f3acefbSGuennadi Liakhovetski 
6663f3acefbSGuennadi Liakhovetski static struct platform_device pxa27x_device_camera = {
6673f3acefbSGuennadi Liakhovetski 	.name		= "pxa27x-camera",
6683f3acefbSGuennadi Liakhovetski 	.id		= 0, /* This is used to put cameras on this interface */
6693f3acefbSGuennadi Liakhovetski 	.dev		= {
6703f3acefbSGuennadi Liakhovetski 		.dma_mask      		= &pxa27x_dma_mask_camera,
6713f3acefbSGuennadi Liakhovetski 		.coherent_dma_mask	= 0xffffffff,
6723f3acefbSGuennadi Liakhovetski 	},
6733f3acefbSGuennadi Liakhovetski 	.num_resources	= ARRAY_SIZE(pxa27x_resource_camera),
6743f3acefbSGuennadi Liakhovetski 	.resource	= pxa27x_resource_camera,
6753f3acefbSGuennadi Liakhovetski };
6763f3acefbSGuennadi Liakhovetski 
6773f3acefbSGuennadi Liakhovetski void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
6783f3acefbSGuennadi Liakhovetski {
6793f3acefbSGuennadi Liakhovetski 	pxa_register_device(&pxa27x_device_camera, info);
6803f3acefbSGuennadi Liakhovetski }
6818f58de7cSeric miao #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
6828f58de7cSeric miao 
6838f58de7cSeric miao #ifdef CONFIG_PXA3xx
6848f58de7cSeric miao static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
6858f58de7cSeric miao 
6868f58de7cSeric miao static struct resource pxa3xx_resource_ssp4[] = {
6878f58de7cSeric miao 	[0] = {
6888f58de7cSeric miao 		.start	= 0x41a00000,
6898f58de7cSeric miao 		.end	= 0x41a0003f,
6908f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
6918f58de7cSeric miao 	},
6928f58de7cSeric miao 	[1] = {
6938f58de7cSeric miao 		.start	= IRQ_SSP4,
6948f58de7cSeric miao 		.end	= IRQ_SSP4,
6958f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
6968f58de7cSeric miao 	},
6978f58de7cSeric miao 	[2] = {
6988f58de7cSeric miao 		/* DRCMR for RX */
6998f58de7cSeric miao 		.start	= 2,
7008f58de7cSeric miao 		.end	= 2,
7018f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7028f58de7cSeric miao 	},
7038f58de7cSeric miao 	[3] = {
7048f58de7cSeric miao 		/* DRCMR for TX */
7058f58de7cSeric miao 		.start	= 3,
7068f58de7cSeric miao 		.end	= 3,
7078f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7088f58de7cSeric miao 	},
7098f58de7cSeric miao };
7108f58de7cSeric miao 
7118f58de7cSeric miao struct platform_device pxa3xx_device_ssp4 = {
7128f58de7cSeric miao 	/* PXA3xx SSP is basically equivalent to PXA27x */
7138f58de7cSeric miao 	.name		= "pxa27x-ssp",
7148f58de7cSeric miao 	.id		= 3,
7158f58de7cSeric miao 	.dev		= {
7168f58de7cSeric miao 		.dma_mask = &pxa3xx_ssp4_dma_mask,
7178f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
7188f58de7cSeric miao 	},
7198f58de7cSeric miao 	.resource	= pxa3xx_resource_ssp4,
7208f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa3xx_resource_ssp4),
7218f58de7cSeric miao };
7228d33b055SBridge Wu 
7238d33b055SBridge Wu static struct resource pxa3xx_resources_mci2[] = {
7248d33b055SBridge Wu 	[0] = {
7258d33b055SBridge Wu 		.start	= 0x42000000,
7268d33b055SBridge Wu 		.end	= 0x42000fff,
7278d33b055SBridge Wu 		.flags	= IORESOURCE_MEM,
7288d33b055SBridge Wu 	},
7298d33b055SBridge Wu 	[1] = {
7308d33b055SBridge Wu 		.start	= IRQ_MMC2,
7318d33b055SBridge Wu 		.end	= IRQ_MMC2,
7328d33b055SBridge Wu 		.flags	= IORESOURCE_IRQ,
7338d33b055SBridge Wu 	},
7348d33b055SBridge Wu 	[2] = {
7358d33b055SBridge Wu 		.start	= 93,
7368d33b055SBridge Wu 		.end	= 93,
7378d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
7388d33b055SBridge Wu 	},
7398d33b055SBridge Wu 	[3] = {
7408d33b055SBridge Wu 		.start	= 94,
7418d33b055SBridge Wu 		.end	= 94,
7428d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
7438d33b055SBridge Wu 	},
7448d33b055SBridge Wu };
7458d33b055SBridge Wu 
7468d33b055SBridge Wu struct platform_device pxa3xx_device_mci2 = {
7478d33b055SBridge Wu 	.name		= "pxa2xx-mci",
7488d33b055SBridge Wu 	.id		= 1,
7498d33b055SBridge Wu 	.dev		= {
7508d33b055SBridge Wu 		.dma_mask = &pxamci_dmamask,
7518d33b055SBridge Wu 		.coherent_dma_mask =	0xffffffff,
7528d33b055SBridge Wu 	},
7538d33b055SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci2),
7548d33b055SBridge Wu 	.resource	= pxa3xx_resources_mci2,
7558d33b055SBridge Wu };
7568d33b055SBridge Wu 
7578d33b055SBridge Wu void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
7588d33b055SBridge Wu {
7598d33b055SBridge Wu 	pxa_register_device(&pxa3xx_device_mci2, info);
7608d33b055SBridge Wu }
7618d33b055SBridge Wu 
7625a1f21b1SBridge Wu static struct resource pxa3xx_resources_mci3[] = {
7635a1f21b1SBridge Wu 	[0] = {
7645a1f21b1SBridge Wu 		.start	= 0x42500000,
7655a1f21b1SBridge Wu 		.end	= 0x42500fff,
7665a1f21b1SBridge Wu 		.flags	= IORESOURCE_MEM,
7675a1f21b1SBridge Wu 	},
7685a1f21b1SBridge Wu 	[1] = {
7695a1f21b1SBridge Wu 		.start	= IRQ_MMC3,
7705a1f21b1SBridge Wu 		.end	= IRQ_MMC3,
7715a1f21b1SBridge Wu 		.flags	= IORESOURCE_IRQ,
7725a1f21b1SBridge Wu 	},
7735a1f21b1SBridge Wu 	[2] = {
7745a1f21b1SBridge Wu 		.start	= 100,
7755a1f21b1SBridge Wu 		.end	= 100,
7765a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
7775a1f21b1SBridge Wu 	},
7785a1f21b1SBridge Wu 	[3] = {
7795a1f21b1SBridge Wu 		.start	= 101,
7805a1f21b1SBridge Wu 		.end	= 101,
7815a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
7825a1f21b1SBridge Wu 	},
7835a1f21b1SBridge Wu };
7845a1f21b1SBridge Wu 
7855a1f21b1SBridge Wu struct platform_device pxa3xx_device_mci3 = {
7865a1f21b1SBridge Wu 	.name		= "pxa2xx-mci",
7875a1f21b1SBridge Wu 	.id		= 2,
7885a1f21b1SBridge Wu 	.dev		= {
7895a1f21b1SBridge Wu 		.dma_mask = &pxamci_dmamask,
7905a1f21b1SBridge Wu 		.coherent_dma_mask = 0xffffffff,
7915a1f21b1SBridge Wu 	},
7925a1f21b1SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci3),
7935a1f21b1SBridge Wu 	.resource	= pxa3xx_resources_mci3,
7945a1f21b1SBridge Wu };
7955a1f21b1SBridge Wu 
7965a1f21b1SBridge Wu void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
7975a1f21b1SBridge Wu {
7985a1f21b1SBridge Wu 	pxa_register_device(&pxa3xx_device_mci3, info);
7995a1f21b1SBridge Wu }
8005a1f21b1SBridge Wu 
8018f58de7cSeric miao #endif /* CONFIG_PXA3xx */
802