xref: /linux/arch/arm/mach-pxa/devices.c (revision 4be0856fa34ef3b0681aeec669e50c13e394f145)
18f58de7cSeric miao #include <linux/module.h>
28f58de7cSeric miao #include <linux/kernel.h>
38f58de7cSeric miao #include <linux/init.h>
48f58de7cSeric miao #include <linux/platform_device.h>
58f58de7cSeric miao #include <linux/dma-mapping.h>
68348c259SSebastian Andrzej Siewior #include <linux/spi/pxa2xx_spi.h>
7b459396eSSebastian Andrzej Siewior #include <linux/i2c/pxa-i2c.h>
88f58de7cSeric miao 
9a09e64fbSRussell King #include <mach/udc.h>
10293b2da1SArnd Bergmann #include <linux/platform_data/usb-pxa3xx-ulpi.h>
11293b2da1SArnd Bergmann #include <linux/platform_data/video-pxafb.h>
12293b2da1SArnd Bergmann #include <linux/platform_data/mmc-pxamci.h>
13293b2da1SArnd Bergmann #include <linux/platform_data/irda-pxaficp.h>
144e611091SRob Herring #include <mach/irqs.h>
15293b2da1SArnd Bergmann #include <linux/platform_data/usb-ohci-pxa27x.h>
16293b2da1SArnd Bergmann #include <linux/platform_data/keypad-pxa27x.h>
17293b2da1SArnd Bergmann #include <linux/platform_data/camera-pxa.h>
18a09e64fbSRussell King #include <mach/audio.h>
1975e874c6SEric Miao #include <mach/hardware.h>
20*4be0856fSRobert Jarzmik #include <linux/platform_data/mmp_dma.h>
21293b2da1SArnd Bergmann #include <linux/platform_data/mtd-nand-pxa3xx.h>
228f58de7cSeric miao 
238f58de7cSeric miao #include "devices.h"
24bc3a5959SPhilipp Zabel #include "generic.h"
258f58de7cSeric miao 
268f58de7cSeric miao void __init pxa_register_device(struct platform_device *dev, void *data)
278f58de7cSeric miao {
288f58de7cSeric miao 	int ret;
298f58de7cSeric miao 
308f58de7cSeric miao 	dev->dev.platform_data = data;
318f58de7cSeric miao 
328f58de7cSeric miao 	ret = platform_device_register(dev);
338f58de7cSeric miao 	if (ret)
348f58de7cSeric miao 		dev_err(&dev->dev, "unable to register device: %d\n", ret);
358f58de7cSeric miao }
368f58de7cSeric miao 
3709a5358dSEric Miao static struct resource pxa_resource_pmu = {
3809a5358dSEric Miao 	.start	= IRQ_PMU,
3909a5358dSEric Miao 	.end	= IRQ_PMU,
4009a5358dSEric Miao 	.flags	= IORESOURCE_IRQ,
4109a5358dSEric Miao };
4209a5358dSEric Miao 
4309a5358dSEric Miao struct platform_device pxa_device_pmu = {
44f9eff219SMark Rutland 	.name		= "xscale-pmu",
45df3d17e0SSudeep KarkadaNagesha 	.id		= -1,
4609a5358dSEric Miao 	.resource	= &pxa_resource_pmu,
4709a5358dSEric Miao 	.num_resources	= 1,
4809a5358dSEric Miao };
4909a5358dSEric Miao 
508f58de7cSeric miao static struct resource pxamci_resources[] = {
518f58de7cSeric miao 	[0] = {
528f58de7cSeric miao 		.start	= 0x41100000,
538f58de7cSeric miao 		.end	= 0x41100fff,
548f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
558f58de7cSeric miao 	},
568f58de7cSeric miao 	[1] = {
578f58de7cSeric miao 		.start	= IRQ_MMC,
588f58de7cSeric miao 		.end	= IRQ_MMC,
598f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
608f58de7cSeric miao 	},
618f58de7cSeric miao 	[2] = {
628f58de7cSeric miao 		.start	= 21,
638f58de7cSeric miao 		.end	= 21,
648f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
658f58de7cSeric miao 	},
668f58de7cSeric miao 	[3] = {
678f58de7cSeric miao 		.start	= 22,
688f58de7cSeric miao 		.end	= 22,
698f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
708f58de7cSeric miao 	},
718f58de7cSeric miao };
728f58de7cSeric miao 
738f58de7cSeric miao static u64 pxamci_dmamask = 0xffffffffUL;
748f58de7cSeric miao 
758f58de7cSeric miao struct platform_device pxa_device_mci = {
768f58de7cSeric miao 	.name		= "pxa2xx-mci",
77fafc9d3fSBridge Wu 	.id		= 0,
788f58de7cSeric miao 	.dev		= {
798f58de7cSeric miao 		.dma_mask = &pxamci_dmamask,
808f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
818f58de7cSeric miao 	},
828f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxamci_resources),
838f58de7cSeric miao 	.resource	= pxamci_resources,
848f58de7cSeric miao };
858f58de7cSeric miao 
868f58de7cSeric miao void __init pxa_set_mci_info(struct pxamci_platform_data *info)
878f58de7cSeric miao {
888f58de7cSeric miao 	pxa_register_device(&pxa_device_mci, info);
898f58de7cSeric miao }
908f58de7cSeric miao 
918f58de7cSeric miao 
921257629bSPhilipp Zabel static struct pxa2xx_udc_mach_info pxa_udc_info = {
931257629bSPhilipp Zabel 	.gpio_pullup = -1,
941257629bSPhilipp Zabel };
958f58de7cSeric miao 
968f58de7cSeric miao void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
978f58de7cSeric miao {
988f58de7cSeric miao 	memcpy(&pxa_udc_info, info, sizeof *info);
998f58de7cSeric miao }
1008f58de7cSeric miao 
1018f58de7cSeric miao static struct resource pxa2xx_udc_resources[] = {
1028f58de7cSeric miao 	[0] = {
1038f58de7cSeric miao 		.start	= 0x40600000,
1048f58de7cSeric miao 		.end	= 0x4060ffff,
1058f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1068f58de7cSeric miao 	},
1078f58de7cSeric miao 	[1] = {
1088f58de7cSeric miao 		.start	= IRQ_USB,
1098f58de7cSeric miao 		.end	= IRQ_USB,
1108f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1118f58de7cSeric miao 	},
1128f58de7cSeric miao };
1138f58de7cSeric miao 
1148f58de7cSeric miao static u64 udc_dma_mask = ~(u32)0;
1158f58de7cSeric miao 
1167a857620SPhilipp Zabel struct platform_device pxa25x_device_udc = {
1177a857620SPhilipp Zabel 	.name		= "pxa25x-udc",
1187a857620SPhilipp Zabel 	.id		= -1,
1197a857620SPhilipp Zabel 	.resource	= pxa2xx_udc_resources,
1207a857620SPhilipp Zabel 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
1217a857620SPhilipp Zabel 	.dev		=  {
1227a857620SPhilipp Zabel 		.platform_data	= &pxa_udc_info,
1237a857620SPhilipp Zabel 		.dma_mask	= &udc_dma_mask,
1247a857620SPhilipp Zabel 	}
1257a857620SPhilipp Zabel };
1267a857620SPhilipp Zabel 
1277a857620SPhilipp Zabel struct platform_device pxa27x_device_udc = {
1287a857620SPhilipp Zabel 	.name		= "pxa27x-udc",
1298f58de7cSeric miao 	.id		= -1,
1308f58de7cSeric miao 	.resource	= pxa2xx_udc_resources,
1318f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
1328f58de7cSeric miao 	.dev		=  {
1338f58de7cSeric miao 		.platform_data	= &pxa_udc_info,
1348f58de7cSeric miao 		.dma_mask	= &udc_dma_mask,
1358f58de7cSeric miao 	}
1368f58de7cSeric miao };
1378f58de7cSeric miao 
13869f22be7SIgor Grinberg #ifdef CONFIG_PXA3xx
13969f22be7SIgor Grinberg static struct resource pxa3xx_u2d_resources[] = {
14069f22be7SIgor Grinberg 	[0] = {
14169f22be7SIgor Grinberg 		.start	= 0x54100000,
14269f22be7SIgor Grinberg 		.end	= 0x54100fff,
14369f22be7SIgor Grinberg 		.flags	= IORESOURCE_MEM,
14469f22be7SIgor Grinberg 	},
14569f22be7SIgor Grinberg 	[1] = {
14669f22be7SIgor Grinberg 		.start	= IRQ_USB2,
14769f22be7SIgor Grinberg 		.end	= IRQ_USB2,
14869f22be7SIgor Grinberg 		.flags	= IORESOURCE_IRQ,
14969f22be7SIgor Grinberg 	},
15069f22be7SIgor Grinberg };
15169f22be7SIgor Grinberg 
15269f22be7SIgor Grinberg struct platform_device pxa3xx_device_u2d = {
15369f22be7SIgor Grinberg 	.name		= "pxa3xx-u2d",
15469f22be7SIgor Grinberg 	.id		= -1,
15569f22be7SIgor Grinberg 	.resource	= pxa3xx_u2d_resources,
15669f22be7SIgor Grinberg 	.num_resources	= ARRAY_SIZE(pxa3xx_u2d_resources),
15769f22be7SIgor Grinberg };
15869f22be7SIgor Grinberg 
15969f22be7SIgor Grinberg void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
16069f22be7SIgor Grinberg {
16169f22be7SIgor Grinberg 	pxa_register_device(&pxa3xx_device_u2d, info);
16269f22be7SIgor Grinberg }
16369f22be7SIgor Grinberg #endif /* CONFIG_PXA3xx */
16469f22be7SIgor Grinberg 
1658f58de7cSeric miao static struct resource pxafb_resources[] = {
1668f58de7cSeric miao 	[0] = {
1678f58de7cSeric miao 		.start	= 0x44000000,
1688f58de7cSeric miao 		.end	= 0x4400ffff,
1698f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1708f58de7cSeric miao 	},
1718f58de7cSeric miao 	[1] = {
1728f58de7cSeric miao 		.start	= IRQ_LCD,
1738f58de7cSeric miao 		.end	= IRQ_LCD,
1748f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1758f58de7cSeric miao 	},
1768f58de7cSeric miao };
1778f58de7cSeric miao 
1788f58de7cSeric miao static u64 fb_dma_mask = ~(u64)0;
1798f58de7cSeric miao 
1808f58de7cSeric miao struct platform_device pxa_device_fb = {
1818f58de7cSeric miao 	.name		= "pxa2xx-fb",
1828f58de7cSeric miao 	.id		= -1,
1838f58de7cSeric miao 	.dev		= {
1848f58de7cSeric miao 		.dma_mask	= &fb_dma_mask,
1858f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
1868f58de7cSeric miao 	},
1878f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxafb_resources),
1888f58de7cSeric miao 	.resource	= pxafb_resources,
1898f58de7cSeric miao };
1908f58de7cSeric miao 
1914321e1a1SRussell King - ARM Linux void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
1928f58de7cSeric miao {
1934321e1a1SRussell King - ARM Linux 	pxa_device_fb.dev.parent = parent;
1948f58de7cSeric miao 	pxa_register_device(&pxa_device_fb, info);
1958f58de7cSeric miao }
1968f58de7cSeric miao 
1978f58de7cSeric miao static struct resource pxa_resource_ffuart[] = {
1988f58de7cSeric miao 	{
19902f65262SEric Miao 		.start	= 0x40100000,
20002f65262SEric Miao 		.end	= 0x40100023,
2018f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2028f58de7cSeric miao 	}, {
2038f58de7cSeric miao 		.start	= IRQ_FFUART,
2048f58de7cSeric miao 		.end	= IRQ_FFUART,
2058f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2068f58de7cSeric miao 	}
2078f58de7cSeric miao };
2088f58de7cSeric miao 
2098f58de7cSeric miao struct platform_device pxa_device_ffuart = {
2108f58de7cSeric miao 	.name		= "pxa2xx-uart",
2118f58de7cSeric miao 	.id		= 0,
2128f58de7cSeric miao 	.resource	= pxa_resource_ffuart,
2138f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_ffuart),
2148f58de7cSeric miao };
2158f58de7cSeric miao 
216cc155c6fSRussell King void __init pxa_set_ffuart_info(void *info)
217cc155c6fSRussell King {
218cc155c6fSRussell King 	pxa_register_device(&pxa_device_ffuart, info);
219cc155c6fSRussell King }
220cc155c6fSRussell King 
2218f58de7cSeric miao static struct resource pxa_resource_btuart[] = {
2228f58de7cSeric miao 	{
22302f65262SEric Miao 		.start	= 0x40200000,
22402f65262SEric Miao 		.end	= 0x40200023,
2258f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2268f58de7cSeric miao 	}, {
2278f58de7cSeric miao 		.start	= IRQ_BTUART,
2288f58de7cSeric miao 		.end	= IRQ_BTUART,
2298f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2308f58de7cSeric miao 	}
2318f58de7cSeric miao };
2328f58de7cSeric miao 
2338f58de7cSeric miao struct platform_device pxa_device_btuart = {
2348f58de7cSeric miao 	.name		= "pxa2xx-uart",
2358f58de7cSeric miao 	.id		= 1,
2368f58de7cSeric miao 	.resource	= pxa_resource_btuart,
2378f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_btuart),
2388f58de7cSeric miao };
2398f58de7cSeric miao 
240cc155c6fSRussell King void __init pxa_set_btuart_info(void *info)
241cc155c6fSRussell King {
242cc155c6fSRussell King 	pxa_register_device(&pxa_device_btuart, info);
243cc155c6fSRussell King }
244cc155c6fSRussell King 
2458f58de7cSeric miao static struct resource pxa_resource_stuart[] = {
2468f58de7cSeric miao 	{
24702f65262SEric Miao 		.start	= 0x40700000,
24802f65262SEric Miao 		.end	= 0x40700023,
2498f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2508f58de7cSeric miao 	}, {
2518f58de7cSeric miao 		.start	= IRQ_STUART,
2528f58de7cSeric miao 		.end	= IRQ_STUART,
2538f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2548f58de7cSeric miao 	}
2558f58de7cSeric miao };
2568f58de7cSeric miao 
2578f58de7cSeric miao struct platform_device pxa_device_stuart = {
2588f58de7cSeric miao 	.name		= "pxa2xx-uart",
2598f58de7cSeric miao 	.id		= 2,
2608f58de7cSeric miao 	.resource	= pxa_resource_stuart,
2618f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_stuart),
2628f58de7cSeric miao };
2638f58de7cSeric miao 
264cc155c6fSRussell King void __init pxa_set_stuart_info(void *info)
265cc155c6fSRussell King {
266cc155c6fSRussell King 	pxa_register_device(&pxa_device_stuart, info);
267cc155c6fSRussell King }
268cc155c6fSRussell King 
2698f58de7cSeric miao static struct resource pxa_resource_hwuart[] = {
2708f58de7cSeric miao 	{
27102f65262SEric Miao 		.start	= 0x41600000,
27202f65262SEric Miao 		.end	= 0x4160002F,
2738f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2748f58de7cSeric miao 	}, {
2758f58de7cSeric miao 		.start	= IRQ_HWUART,
2768f58de7cSeric miao 		.end	= IRQ_HWUART,
2778f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2788f58de7cSeric miao 	}
2798f58de7cSeric miao };
2808f58de7cSeric miao 
2818f58de7cSeric miao struct platform_device pxa_device_hwuart = {
2828f58de7cSeric miao 	.name		= "pxa2xx-uart",
2838f58de7cSeric miao 	.id		= 3,
2848f58de7cSeric miao 	.resource	= pxa_resource_hwuart,
2858f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
2868f58de7cSeric miao };
2878f58de7cSeric miao 
288cc155c6fSRussell King void __init pxa_set_hwuart_info(void *info)
289cc155c6fSRussell King {
290cc155c6fSRussell King 	if (cpu_is_pxa255())
291cc155c6fSRussell King 		pxa_register_device(&pxa_device_hwuart, info);
292cc155c6fSRussell King 	else
293cc155c6fSRussell King 		pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
294cc155c6fSRussell King }
295cc155c6fSRussell King 
2968f58de7cSeric miao static struct resource pxai2c_resources[] = {
2978f58de7cSeric miao 	{
2988f58de7cSeric miao 		.start	= 0x40301680,
2998f58de7cSeric miao 		.end	= 0x403016a3,
3008f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3018f58de7cSeric miao 	}, {
3028f58de7cSeric miao 		.start	= IRQ_I2C,
3038f58de7cSeric miao 		.end	= IRQ_I2C,
3048f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3058f58de7cSeric miao 	},
3068f58de7cSeric miao };
3078f58de7cSeric miao 
3088f58de7cSeric miao struct platform_device pxa_device_i2c = {
3098f58de7cSeric miao 	.name		= "pxa2xx-i2c",
3108f58de7cSeric miao 	.id		= 0,
3118f58de7cSeric miao 	.resource	= pxai2c_resources,
3128f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2c_resources),
3138f58de7cSeric miao };
3148f58de7cSeric miao 
3158f58de7cSeric miao void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
3168f58de7cSeric miao {
3178f58de7cSeric miao 	pxa_register_device(&pxa_device_i2c, info);
3188f58de7cSeric miao }
3198f58de7cSeric miao 
32099464293SEric Miao #ifdef CONFIG_PXA27x
32199464293SEric Miao static struct resource pxa27x_resources_i2c_power[] = {
32299464293SEric Miao 	{
32399464293SEric Miao 		.start	= 0x40f00180,
32499464293SEric Miao 		.end	= 0x40f001a3,
32599464293SEric Miao 		.flags	= IORESOURCE_MEM,
32699464293SEric Miao 	}, {
32799464293SEric Miao 		.start	= IRQ_PWRI2C,
32899464293SEric Miao 		.end	= IRQ_PWRI2C,
32999464293SEric Miao 		.flags	= IORESOURCE_IRQ,
33099464293SEric Miao 	},
33199464293SEric Miao };
33299464293SEric Miao 
33399464293SEric Miao struct platform_device pxa27x_device_i2c_power = {
33499464293SEric Miao 	.name		= "pxa2xx-i2c",
33599464293SEric Miao 	.id		= 1,
33699464293SEric Miao 	.resource	= pxa27x_resources_i2c_power,
33799464293SEric Miao 	.num_resources	= ARRAY_SIZE(pxa27x_resources_i2c_power),
33899464293SEric Miao };
33999464293SEric Miao #endif
34099464293SEric Miao 
3418f58de7cSeric miao static struct resource pxai2s_resources[] = {
3428f58de7cSeric miao 	{
3438f58de7cSeric miao 		.start	= 0x40400000,
3448f58de7cSeric miao 		.end	= 0x40400083,
3458f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3468f58de7cSeric miao 	}, {
3478f58de7cSeric miao 		.start	= IRQ_I2S,
3488f58de7cSeric miao 		.end	= IRQ_I2S,
3498f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3508f58de7cSeric miao 	},
3518f58de7cSeric miao };
3528f58de7cSeric miao 
3538f58de7cSeric miao struct platform_device pxa_device_i2s = {
3548f58de7cSeric miao 	.name		= "pxa2xx-i2s",
3558f58de7cSeric miao 	.id		= -1,
3568f58de7cSeric miao 	.resource	= pxai2s_resources,
3578f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2s_resources),
3588f58de7cSeric miao };
3598f58de7cSeric miao 
360f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp1 = {
361f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
362f0fba2adSLiam Girdwood 	.id		= 0,
363f0fba2adSLiam Girdwood };
364f0fba2adSLiam Girdwood 
365f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp2= {
366f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
367f0fba2adSLiam Girdwood 	.id		= 1,
368f0fba2adSLiam Girdwood };
369f0fba2adSLiam Girdwood 
370f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp3 = {
371f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
372f0fba2adSLiam Girdwood 	.id		= 2,
373f0fba2adSLiam Girdwood };
374f0fba2adSLiam Girdwood 
375f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp4 = {
376f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
377f0fba2adSLiam Girdwood 	.id		= 3,
378f0fba2adSLiam Girdwood };
379f0fba2adSLiam Girdwood 
380f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_platform = {
381f0fba2adSLiam Girdwood 	.name		= "pxa-pcm-audio",
382f0fba2adSLiam Girdwood 	.id		= -1,
383f0fba2adSLiam Girdwood };
384f0fba2adSLiam Girdwood 
3858f58de7cSeric miao static u64 pxaficp_dmamask = ~(u32)0;
3868f58de7cSeric miao 
387121f3f9bSRob Herring static struct resource pxa_ir_resources[] = {
388121f3f9bSRob Herring 	[0] = {
389121f3f9bSRob Herring 		.start  = IRQ_STUART,
390121f3f9bSRob Herring 		.end    = IRQ_STUART,
391121f3f9bSRob Herring 		.flags  = IORESOURCE_IRQ,
392121f3f9bSRob Herring 	},
393121f3f9bSRob Herring 	[1] = {
394121f3f9bSRob Herring 		.start  = IRQ_ICP,
395121f3f9bSRob Herring 		.end    = IRQ_ICP,
396121f3f9bSRob Herring 		.flags  = IORESOURCE_IRQ,
397121f3f9bSRob Herring 	},
398121f3f9bSRob Herring };
399121f3f9bSRob Herring 
4008f58de7cSeric miao struct platform_device pxa_device_ficp = {
4018f58de7cSeric miao 	.name		= "pxa2xx-ir",
4028f58de7cSeric miao 	.id		= -1,
403121f3f9bSRob Herring 	.num_resources	= ARRAY_SIZE(pxa_ir_resources),
404121f3f9bSRob Herring 	.resource	= pxa_ir_resources,
4058f58de7cSeric miao 	.dev		= {
4068f58de7cSeric miao 		.dma_mask = &pxaficp_dmamask,
4078f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
4088f58de7cSeric miao 	},
4098f58de7cSeric miao };
4108f58de7cSeric miao 
4118f58de7cSeric miao void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
4128f58de7cSeric miao {
4138f58de7cSeric miao 	pxa_register_device(&pxa_device_ficp, info);
4148f58de7cSeric miao }
4158f58de7cSeric miao 
41672493146SRobert Jarzmik static struct resource pxa_rtc_resources[] = {
41772493146SRobert Jarzmik 	[0] = {
41872493146SRobert Jarzmik 		.start  = 0x40900000,
41972493146SRobert Jarzmik 		.end	= 0x40900000 + 0x3b,
42072493146SRobert Jarzmik 		.flags  = IORESOURCE_MEM,
42172493146SRobert Jarzmik 	},
42272493146SRobert Jarzmik 	[1] = {
42372493146SRobert Jarzmik 		.start  = IRQ_RTC1Hz,
42472493146SRobert Jarzmik 		.end    = IRQ_RTC1Hz,
4253888c090SHaojian Zhuang 		.name	= "rtc 1Hz",
42672493146SRobert Jarzmik 		.flags  = IORESOURCE_IRQ,
42772493146SRobert Jarzmik 	},
42872493146SRobert Jarzmik 	[2] = {
42972493146SRobert Jarzmik 		.start  = IRQ_RTCAlrm,
43072493146SRobert Jarzmik 		.end    = IRQ_RTCAlrm,
4313888c090SHaojian Zhuang 		.name	= "rtc alarm",
43272493146SRobert Jarzmik 		.flags  = IORESOURCE_IRQ,
43372493146SRobert Jarzmik 	},
43472493146SRobert Jarzmik };
43572493146SRobert Jarzmik 
43672493146SRobert Jarzmik struct platform_device pxa_device_rtc = {
43772493146SRobert Jarzmik 	.name		= "pxa-rtc",
43872493146SRobert Jarzmik 	.id		= -1,
43972493146SRobert Jarzmik 	.num_resources  = ARRAY_SIZE(pxa_rtc_resources),
44072493146SRobert Jarzmik 	.resource       = pxa_rtc_resources,
44172493146SRobert Jarzmik };
44272493146SRobert Jarzmik 
4433888c090SHaojian Zhuang static struct resource sa1100_rtc_resources[] = {
4443888c090SHaojian Zhuang 	{
4453888c090SHaojian Zhuang 		.start  = IRQ_RTC1Hz,
4463888c090SHaojian Zhuang 		.end    = IRQ_RTC1Hz,
4473888c090SHaojian Zhuang 		.name	= "rtc 1Hz",
4483888c090SHaojian Zhuang 		.flags  = IORESOURCE_IRQ,
4493888c090SHaojian Zhuang 	}, {
4503888c090SHaojian Zhuang 		.start  = IRQ_RTCAlrm,
4513888c090SHaojian Zhuang 		.end    = IRQ_RTCAlrm,
4523888c090SHaojian Zhuang 		.name	= "rtc alarm",
4533888c090SHaojian Zhuang 		.flags  = IORESOURCE_IRQ,
4543888c090SHaojian Zhuang 	},
4553888c090SHaojian Zhuang };
4563888c090SHaojian Zhuang 
4573888c090SHaojian Zhuang struct platform_device sa1100_device_rtc = {
4583888c090SHaojian Zhuang 	.name		= "sa1100-rtc",
4593888c090SHaojian Zhuang 	.id		= -1,
4603888c090SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(sa1100_rtc_resources),
4613888c090SHaojian Zhuang 	.resource	= sa1100_rtc_resources,
4623888c090SHaojian Zhuang };
4633888c090SHaojian Zhuang 
4649f19d638SMark Brown static struct resource pxa_ac97_resources[] = {
4659f19d638SMark Brown 	[0] = {
4669f19d638SMark Brown 		.start  = 0x40500000,
4679f19d638SMark Brown 		.end	= 0x40500000 + 0xfff,
4689f19d638SMark Brown 		.flags  = IORESOURCE_MEM,
4699f19d638SMark Brown 	},
4709f19d638SMark Brown 	[1] = {
4719f19d638SMark Brown 		.start  = IRQ_AC97,
4729f19d638SMark Brown 		.end    = IRQ_AC97,
4739f19d638SMark Brown 		.flags  = IORESOURCE_IRQ,
4749f19d638SMark Brown 	},
4759f19d638SMark Brown };
4769f19d638SMark Brown 
4779f19d638SMark Brown static u64 pxa_ac97_dmamask = 0xffffffffUL;
4789f19d638SMark Brown 
4799f19d638SMark Brown struct platform_device pxa_device_ac97 = {
4809f19d638SMark Brown 	.name           = "pxa2xx-ac97",
4819f19d638SMark Brown 	.id             = -1,
4829f19d638SMark Brown 	.dev            = {
4839f19d638SMark Brown 		.dma_mask = &pxa_ac97_dmamask,
4849f19d638SMark Brown 		.coherent_dma_mask = 0xffffffff,
4859f19d638SMark Brown 	},
4869f19d638SMark Brown 	.num_resources  = ARRAY_SIZE(pxa_ac97_resources),
4879f19d638SMark Brown 	.resource       = pxa_ac97_resources,
4889f19d638SMark Brown };
4899f19d638SMark Brown 
4909f19d638SMark Brown void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
4919f19d638SMark Brown {
4929f19d638SMark Brown 	pxa_register_device(&pxa_device_ac97, ops);
4939f19d638SMark Brown }
4949f19d638SMark Brown 
4958f58de7cSeric miao #ifdef CONFIG_PXA25x
4968f58de7cSeric miao 
49775540c1aSeric miao static struct resource pxa25x_resource_pwm0[] = {
49875540c1aSeric miao 	[0] = {
49975540c1aSeric miao 		.start	= 0x40b00000,
50075540c1aSeric miao 		.end	= 0x40b0000f,
50175540c1aSeric miao 		.flags	= IORESOURCE_MEM,
50275540c1aSeric miao 	},
50375540c1aSeric miao };
50475540c1aSeric miao 
50575540c1aSeric miao struct platform_device pxa25x_device_pwm0 = {
50675540c1aSeric miao 	.name		= "pxa25x-pwm",
50775540c1aSeric miao 	.id		= 0,
50875540c1aSeric miao 	.resource	= pxa25x_resource_pwm0,
50975540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm0),
51075540c1aSeric miao };
51175540c1aSeric miao 
51275540c1aSeric miao static struct resource pxa25x_resource_pwm1[] = {
51375540c1aSeric miao 	[0] = {
51475540c1aSeric miao 		.start	= 0x40c00000,
51575540c1aSeric miao 		.end	= 0x40c0000f,
51675540c1aSeric miao 		.flags	= IORESOURCE_MEM,
51775540c1aSeric miao 	},
51875540c1aSeric miao };
51975540c1aSeric miao 
52075540c1aSeric miao struct platform_device pxa25x_device_pwm1 = {
52175540c1aSeric miao 	.name		= "pxa25x-pwm",
52275540c1aSeric miao 	.id		= 1,
52375540c1aSeric miao 	.resource	= pxa25x_resource_pwm1,
52475540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm1),
52575540c1aSeric miao };
52675540c1aSeric miao 
5278f58de7cSeric miao static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
5288f58de7cSeric miao 
5298f58de7cSeric miao static struct resource pxa25x_resource_ssp[] = {
5308f58de7cSeric miao 	[0] = {
5318f58de7cSeric miao 		.start	= 0x41000000,
5328f58de7cSeric miao 		.end	= 0x4100001f,
5338f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5348f58de7cSeric miao 	},
5358f58de7cSeric miao 	[1] = {
5368f58de7cSeric miao 		.start	= IRQ_SSP,
5378f58de7cSeric miao 		.end	= IRQ_SSP,
5388f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5398f58de7cSeric miao 	},
5408f58de7cSeric miao 	[2] = {
5418f58de7cSeric miao 		/* DRCMR for RX */
5428f58de7cSeric miao 		.start	= 13,
5438f58de7cSeric miao 		.end	= 13,
5448f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5458f58de7cSeric miao 	},
5468f58de7cSeric miao 	[3] = {
5478f58de7cSeric miao 		/* DRCMR for TX */
5488f58de7cSeric miao 		.start	= 14,
5498f58de7cSeric miao 		.end	= 14,
5508f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5518f58de7cSeric miao 	},
5528f58de7cSeric miao };
5538f58de7cSeric miao 
5548f58de7cSeric miao struct platform_device pxa25x_device_ssp = {
5558f58de7cSeric miao 	.name		= "pxa25x-ssp",
5568f58de7cSeric miao 	.id		= 0,
5578f58de7cSeric miao 	.dev		= {
5588f58de7cSeric miao 		.dma_mask = &pxa25x_ssp_dma_mask,
5598f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
5608f58de7cSeric miao 	},
5618f58de7cSeric miao 	.resource	= pxa25x_resource_ssp,
5628f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_ssp),
5638f58de7cSeric miao };
5648f58de7cSeric miao 
5658f58de7cSeric miao static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
5668f58de7cSeric miao 
5678f58de7cSeric miao static struct resource pxa25x_resource_nssp[] = {
5688f58de7cSeric miao 	[0] = {
5698f58de7cSeric miao 		.start	= 0x41400000,
5708f58de7cSeric miao 		.end	= 0x4140002f,
5718f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5728f58de7cSeric miao 	},
5738f58de7cSeric miao 	[1] = {
5748f58de7cSeric miao 		.start	= IRQ_NSSP,
5758f58de7cSeric miao 		.end	= IRQ_NSSP,
5768f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5778f58de7cSeric miao 	},
5788f58de7cSeric miao 	[2] = {
5798f58de7cSeric miao 		/* DRCMR for RX */
5808f58de7cSeric miao 		.start	= 15,
5818f58de7cSeric miao 		.end	= 15,
5828f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5838f58de7cSeric miao 	},
5848f58de7cSeric miao 	[3] = {
5858f58de7cSeric miao 		/* DRCMR for TX */
5868f58de7cSeric miao 		.start	= 16,
5878f58de7cSeric miao 		.end	= 16,
5888f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5898f58de7cSeric miao 	},
5908f58de7cSeric miao };
5918f58de7cSeric miao 
5928f58de7cSeric miao struct platform_device pxa25x_device_nssp = {
5938f58de7cSeric miao 	.name		= "pxa25x-nssp",
5948f58de7cSeric miao 	.id		= 1,
5958f58de7cSeric miao 	.dev		= {
5968f58de7cSeric miao 		.dma_mask = &pxa25x_nssp_dma_mask,
5978f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
5988f58de7cSeric miao 	},
5998f58de7cSeric miao 	.resource	= pxa25x_resource_nssp,
6008f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_nssp),
6018f58de7cSeric miao };
6028f58de7cSeric miao 
6038f58de7cSeric miao static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
6048f58de7cSeric miao 
6058f58de7cSeric miao static struct resource pxa25x_resource_assp[] = {
6068f58de7cSeric miao 	[0] = {
6078f58de7cSeric miao 		.start	= 0x41500000,
6088f58de7cSeric miao 		.end	= 0x4150002f,
6098f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
6108f58de7cSeric miao 	},
6118f58de7cSeric miao 	[1] = {
6128f58de7cSeric miao 		.start	= IRQ_ASSP,
6138f58de7cSeric miao 		.end	= IRQ_ASSP,
6148f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
6158f58de7cSeric miao 	},
6168f58de7cSeric miao 	[2] = {
6178f58de7cSeric miao 		/* DRCMR for RX */
6188f58de7cSeric miao 		.start	= 23,
6198f58de7cSeric miao 		.end	= 23,
6208f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6218f58de7cSeric miao 	},
6228f58de7cSeric miao 	[3] = {
6238f58de7cSeric miao 		/* DRCMR for TX */
6248f58de7cSeric miao 		.start	= 24,
6258f58de7cSeric miao 		.end	= 24,
6268f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6278f58de7cSeric miao 	},
6288f58de7cSeric miao };
6298f58de7cSeric miao 
6308f58de7cSeric miao struct platform_device pxa25x_device_assp = {
6318f58de7cSeric miao 	/* ASSP is basically equivalent to NSSP */
6328f58de7cSeric miao 	.name		= "pxa25x-nssp",
6338f58de7cSeric miao 	.id		= 2,
6348f58de7cSeric miao 	.dev		= {
6358f58de7cSeric miao 		.dma_mask = &pxa25x_assp_dma_mask,
6368f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
6378f58de7cSeric miao 	},
6388f58de7cSeric miao 	.resource	= pxa25x_resource_assp,
6398f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_assp),
6408f58de7cSeric miao };
6418f58de7cSeric miao #endif /* CONFIG_PXA25x */
6428f58de7cSeric miao 
6438f58de7cSeric miao #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
644a4553358SHaojian Zhuang static struct resource pxa27x_resource_camera[] = {
64537320980Seric miao 	[0] = {
646a4553358SHaojian Zhuang 		.start	= 0x50000000,
647a4553358SHaojian Zhuang 		.end	= 0x50000fff,
64837320980Seric miao 		.flags	= IORESOURCE_MEM,
64937320980Seric miao 	},
65037320980Seric miao 	[1] = {
651a4553358SHaojian Zhuang 		.start	= IRQ_CAMERA,
652a4553358SHaojian Zhuang 		.end	= IRQ_CAMERA,
65337320980Seric miao 		.flags	= IORESOURCE_IRQ,
65437320980Seric miao 	},
65537320980Seric miao };
65637320980Seric miao 
657a4553358SHaojian Zhuang static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
658a4553358SHaojian Zhuang 
659a4553358SHaojian Zhuang static struct platform_device pxa27x_device_camera = {
660a4553358SHaojian Zhuang 	.name		= "pxa27x-camera",
661a4553358SHaojian Zhuang 	.id		= 0, /* This is used to put cameras on this interface */
662a4553358SHaojian Zhuang 	.dev		= {
663a4553358SHaojian Zhuang 		.dma_mask      		= &pxa27x_dma_mask_camera,
664a4553358SHaojian Zhuang 		.coherent_dma_mask	= 0xffffffff,
665a4553358SHaojian Zhuang 	},
666a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa27x_resource_camera),
667a4553358SHaojian Zhuang 	.resource	= pxa27x_resource_camera,
66837320980Seric miao };
66937320980Seric miao 
670a4553358SHaojian Zhuang void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
67137320980Seric miao {
672a4553358SHaojian Zhuang 	pxa_register_device(&pxa27x_device_camera, info);
67337320980Seric miao }
67437320980Seric miao 
675ec68e45bSeric miao static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
676ec68e45bSeric miao 
677ec68e45bSeric miao static struct resource pxa27x_resource_ohci[] = {
678ec68e45bSeric miao 	[0] = {
679ec68e45bSeric miao 		.start  = 0x4C000000,
680ec68e45bSeric miao 		.end    = 0x4C00ff6f,
681ec68e45bSeric miao 		.flags  = IORESOURCE_MEM,
682ec68e45bSeric miao 	},
683ec68e45bSeric miao 	[1] = {
684ec68e45bSeric miao 		.start  = IRQ_USBH1,
685ec68e45bSeric miao 		.end    = IRQ_USBH1,
686ec68e45bSeric miao 		.flags  = IORESOURCE_IRQ,
687ec68e45bSeric miao 	},
688ec68e45bSeric miao };
689ec68e45bSeric miao 
690ec68e45bSeric miao struct platform_device pxa27x_device_ohci = {
691ec68e45bSeric miao 	.name		= "pxa27x-ohci",
692ec68e45bSeric miao 	.id		= -1,
693ec68e45bSeric miao 	.dev		= {
694ec68e45bSeric miao 		.dma_mask = &pxa27x_ohci_dma_mask,
695ec68e45bSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
696ec68e45bSeric miao 	},
697ec68e45bSeric miao 	.num_resources  = ARRAY_SIZE(pxa27x_resource_ohci),
698ec68e45bSeric miao 	.resource       = pxa27x_resource_ohci,
699ec68e45bSeric miao };
700ec68e45bSeric miao 
701ec68e45bSeric miao void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
702ec68e45bSeric miao {
703ec68e45bSeric miao 	pxa_register_device(&pxa27x_device_ohci, info);
704ec68e45bSeric miao }
705a4553358SHaojian Zhuang #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
706a4553358SHaojian Zhuang 
70749ea7fc0SHaojian Zhuang #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
708a4553358SHaojian Zhuang static struct resource pxa27x_resource_keypad[] = {
709a4553358SHaojian Zhuang 	[0] = {
710a4553358SHaojian Zhuang 		.start	= 0x41500000,
711a4553358SHaojian Zhuang 		.end	= 0x4150004c,
712a4553358SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
713a4553358SHaojian Zhuang 	},
714a4553358SHaojian Zhuang 	[1] = {
715a4553358SHaojian Zhuang 		.start	= IRQ_KEYPAD,
716a4553358SHaojian Zhuang 		.end	= IRQ_KEYPAD,
717a4553358SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
718a4553358SHaojian Zhuang 	},
719a4553358SHaojian Zhuang };
720a4553358SHaojian Zhuang 
721a4553358SHaojian Zhuang struct platform_device pxa27x_device_keypad = {
722a4553358SHaojian Zhuang 	.name		= "pxa27x-keypad",
723a4553358SHaojian Zhuang 	.id		= -1,
724a4553358SHaojian Zhuang 	.resource	= pxa27x_resource_keypad,
725a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa27x_resource_keypad),
726a4553358SHaojian Zhuang };
727a4553358SHaojian Zhuang 
728a4553358SHaojian Zhuang void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
729a4553358SHaojian Zhuang {
730a4553358SHaojian Zhuang 	pxa_register_device(&pxa27x_device_keypad, info);
731a4553358SHaojian Zhuang }
732ec68e45bSeric miao 
7338f58de7cSeric miao static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
7348f58de7cSeric miao 
7358f58de7cSeric miao static struct resource pxa27x_resource_ssp1[] = {
7368f58de7cSeric miao 	[0] = {
7378f58de7cSeric miao 		.start	= 0x41000000,
7388f58de7cSeric miao 		.end	= 0x4100003f,
7398f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
7408f58de7cSeric miao 	},
7418f58de7cSeric miao 	[1] = {
7428f58de7cSeric miao 		.start	= IRQ_SSP,
7438f58de7cSeric miao 		.end	= IRQ_SSP,
7448f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
7458f58de7cSeric miao 	},
7468f58de7cSeric miao 	[2] = {
7478f58de7cSeric miao 		/* DRCMR for RX */
7488f58de7cSeric miao 		.start	= 13,
7498f58de7cSeric miao 		.end	= 13,
7508f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7518f58de7cSeric miao 	},
7528f58de7cSeric miao 	[3] = {
7538f58de7cSeric miao 		/* DRCMR for TX */
7548f58de7cSeric miao 		.start	= 14,
7558f58de7cSeric miao 		.end	= 14,
7568f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7578f58de7cSeric miao 	},
7588f58de7cSeric miao };
7598f58de7cSeric miao 
7608f58de7cSeric miao struct platform_device pxa27x_device_ssp1 = {
7618f58de7cSeric miao 	.name		= "pxa27x-ssp",
7628f58de7cSeric miao 	.id		= 0,
7638f58de7cSeric miao 	.dev		= {
7648f58de7cSeric miao 		.dma_mask = &pxa27x_ssp1_dma_mask,
7658f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
7668f58de7cSeric miao 	},
7678f58de7cSeric miao 	.resource	= pxa27x_resource_ssp1,
7688f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
7698f58de7cSeric miao };
7708f58de7cSeric miao 
7718f58de7cSeric miao static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
7728f58de7cSeric miao 
7738f58de7cSeric miao static struct resource pxa27x_resource_ssp2[] = {
7748f58de7cSeric miao 	[0] = {
7758f58de7cSeric miao 		.start	= 0x41700000,
7768f58de7cSeric miao 		.end	= 0x4170003f,
7778f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
7788f58de7cSeric miao 	},
7798f58de7cSeric miao 	[1] = {
7808f58de7cSeric miao 		.start	= IRQ_SSP2,
7818f58de7cSeric miao 		.end	= IRQ_SSP2,
7828f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
7838f58de7cSeric miao 	},
7848f58de7cSeric miao 	[2] = {
7858f58de7cSeric miao 		/* DRCMR for RX */
7868f58de7cSeric miao 		.start	= 15,
7878f58de7cSeric miao 		.end	= 15,
7888f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7898f58de7cSeric miao 	},
7908f58de7cSeric miao 	[3] = {
7918f58de7cSeric miao 		/* DRCMR for TX */
7928f58de7cSeric miao 		.start	= 16,
7938f58de7cSeric miao 		.end	= 16,
7948f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7958f58de7cSeric miao 	},
7968f58de7cSeric miao };
7978f58de7cSeric miao 
7988f58de7cSeric miao struct platform_device pxa27x_device_ssp2 = {
7998f58de7cSeric miao 	.name		= "pxa27x-ssp",
8008f58de7cSeric miao 	.id		= 1,
8018f58de7cSeric miao 	.dev		= {
8028f58de7cSeric miao 		.dma_mask = &pxa27x_ssp2_dma_mask,
8038f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
8048f58de7cSeric miao 	},
8058f58de7cSeric miao 	.resource	= pxa27x_resource_ssp2,
8068f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
8078f58de7cSeric miao };
8088f58de7cSeric miao 
8098f58de7cSeric miao static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
8108f58de7cSeric miao 
8118f58de7cSeric miao static struct resource pxa27x_resource_ssp3[] = {
8128f58de7cSeric miao 	[0] = {
8138f58de7cSeric miao 		.start	= 0x41900000,
8148f58de7cSeric miao 		.end	= 0x4190003f,
8158f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
8168f58de7cSeric miao 	},
8178f58de7cSeric miao 	[1] = {
8188f58de7cSeric miao 		.start	= IRQ_SSP3,
8198f58de7cSeric miao 		.end	= IRQ_SSP3,
8208f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
8218f58de7cSeric miao 	},
8228f58de7cSeric miao 	[2] = {
8238f58de7cSeric miao 		/* DRCMR for RX */
8248f58de7cSeric miao 		.start	= 66,
8258f58de7cSeric miao 		.end	= 66,
8268f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
8278f58de7cSeric miao 	},
8288f58de7cSeric miao 	[3] = {
8298f58de7cSeric miao 		/* DRCMR for TX */
8308f58de7cSeric miao 		.start	= 67,
8318f58de7cSeric miao 		.end	= 67,
8328f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
8338f58de7cSeric miao 	},
8348f58de7cSeric miao };
8358f58de7cSeric miao 
8368f58de7cSeric miao struct platform_device pxa27x_device_ssp3 = {
8378f58de7cSeric miao 	.name		= "pxa27x-ssp",
8388f58de7cSeric miao 	.id		= 2,
8398f58de7cSeric miao 	.dev		= {
8408f58de7cSeric miao 		.dma_mask = &pxa27x_ssp3_dma_mask,
8418f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
8428f58de7cSeric miao 	},
8438f58de7cSeric miao 	.resource	= pxa27x_resource_ssp3,
8448f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
8458f58de7cSeric miao };
8463f3acefbSGuennadi Liakhovetski 
84775540c1aSeric miao static struct resource pxa27x_resource_pwm0[] = {
84875540c1aSeric miao 	[0] = {
84975540c1aSeric miao 		.start	= 0x40b00000,
85075540c1aSeric miao 		.end	= 0x40b0001f,
85175540c1aSeric miao 		.flags	= IORESOURCE_MEM,
85275540c1aSeric miao 	},
85375540c1aSeric miao };
85475540c1aSeric miao 
85575540c1aSeric miao struct platform_device pxa27x_device_pwm0 = {
85675540c1aSeric miao 	.name		= "pxa27x-pwm",
85775540c1aSeric miao 	.id		= 0,
85875540c1aSeric miao 	.resource	= pxa27x_resource_pwm0,
85975540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm0),
86075540c1aSeric miao };
86175540c1aSeric miao 
86275540c1aSeric miao static struct resource pxa27x_resource_pwm1[] = {
86375540c1aSeric miao 	[0] = {
86475540c1aSeric miao 		.start	= 0x40c00000,
86575540c1aSeric miao 		.end	= 0x40c0001f,
86675540c1aSeric miao 		.flags	= IORESOURCE_MEM,
86775540c1aSeric miao 	},
86875540c1aSeric miao };
86975540c1aSeric miao 
87075540c1aSeric miao struct platform_device pxa27x_device_pwm1 = {
87175540c1aSeric miao 	.name		= "pxa27x-pwm",
87275540c1aSeric miao 	.id		= 1,
87375540c1aSeric miao 	.resource	= pxa27x_resource_pwm1,
87475540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm1),
87575540c1aSeric miao };
87649ea7fc0SHaojian Zhuang #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
8778f58de7cSeric miao 
8788f58de7cSeric miao #ifdef CONFIG_PXA3xx
8798d33b055SBridge Wu static struct resource pxa3xx_resources_mci2[] = {
8808d33b055SBridge Wu 	[0] = {
8818d33b055SBridge Wu 		.start	= 0x42000000,
8828d33b055SBridge Wu 		.end	= 0x42000fff,
8838d33b055SBridge Wu 		.flags	= IORESOURCE_MEM,
8848d33b055SBridge Wu 	},
8858d33b055SBridge Wu 	[1] = {
8868d33b055SBridge Wu 		.start	= IRQ_MMC2,
8878d33b055SBridge Wu 		.end	= IRQ_MMC2,
8888d33b055SBridge Wu 		.flags	= IORESOURCE_IRQ,
8898d33b055SBridge Wu 	},
8908d33b055SBridge Wu 	[2] = {
8918d33b055SBridge Wu 		.start	= 93,
8928d33b055SBridge Wu 		.end	= 93,
8938d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
8948d33b055SBridge Wu 	},
8958d33b055SBridge Wu 	[3] = {
8968d33b055SBridge Wu 		.start	= 94,
8978d33b055SBridge Wu 		.end	= 94,
8988d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
8998d33b055SBridge Wu 	},
9008d33b055SBridge Wu };
9018d33b055SBridge Wu 
9028d33b055SBridge Wu struct platform_device pxa3xx_device_mci2 = {
9038d33b055SBridge Wu 	.name		= "pxa2xx-mci",
9048d33b055SBridge Wu 	.id		= 1,
9058d33b055SBridge Wu 	.dev		= {
9068d33b055SBridge Wu 		.dma_mask = &pxamci_dmamask,
9078d33b055SBridge Wu 		.coherent_dma_mask =	0xffffffff,
9088d33b055SBridge Wu 	},
9098d33b055SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci2),
9108d33b055SBridge Wu 	.resource	= pxa3xx_resources_mci2,
9118d33b055SBridge Wu };
9128d33b055SBridge Wu 
9138d33b055SBridge Wu void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
9148d33b055SBridge Wu {
9158d33b055SBridge Wu 	pxa_register_device(&pxa3xx_device_mci2, info);
9168d33b055SBridge Wu }
9178d33b055SBridge Wu 
9185a1f21b1SBridge Wu static struct resource pxa3xx_resources_mci3[] = {
9195a1f21b1SBridge Wu 	[0] = {
9205a1f21b1SBridge Wu 		.start	= 0x42500000,
9215a1f21b1SBridge Wu 		.end	= 0x42500fff,
9225a1f21b1SBridge Wu 		.flags	= IORESOURCE_MEM,
9235a1f21b1SBridge Wu 	},
9245a1f21b1SBridge Wu 	[1] = {
9255a1f21b1SBridge Wu 		.start	= IRQ_MMC3,
9265a1f21b1SBridge Wu 		.end	= IRQ_MMC3,
9275a1f21b1SBridge Wu 		.flags	= IORESOURCE_IRQ,
9285a1f21b1SBridge Wu 	},
9295a1f21b1SBridge Wu 	[2] = {
9305a1f21b1SBridge Wu 		.start	= 100,
9315a1f21b1SBridge Wu 		.end	= 100,
9325a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
9335a1f21b1SBridge Wu 	},
9345a1f21b1SBridge Wu 	[3] = {
9355a1f21b1SBridge Wu 		.start	= 101,
9365a1f21b1SBridge Wu 		.end	= 101,
9375a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
9385a1f21b1SBridge Wu 	},
9395a1f21b1SBridge Wu };
9405a1f21b1SBridge Wu 
9415a1f21b1SBridge Wu struct platform_device pxa3xx_device_mci3 = {
9425a1f21b1SBridge Wu 	.name		= "pxa2xx-mci",
9435a1f21b1SBridge Wu 	.id		= 2,
9445a1f21b1SBridge Wu 	.dev		= {
9455a1f21b1SBridge Wu 		.dma_mask = &pxamci_dmamask,
9465a1f21b1SBridge Wu 		.coherent_dma_mask = 0xffffffff,
9475a1f21b1SBridge Wu 	},
9485a1f21b1SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci3),
9495a1f21b1SBridge Wu 	.resource	= pxa3xx_resources_mci3,
9505a1f21b1SBridge Wu };
9515a1f21b1SBridge Wu 
9525a1f21b1SBridge Wu void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
9535a1f21b1SBridge Wu {
9545a1f21b1SBridge Wu 	pxa_register_device(&pxa3xx_device_mci3, info);
9555a1f21b1SBridge Wu }
9565a1f21b1SBridge Wu 
957a4553358SHaojian Zhuang static struct resource pxa3xx_resources_gcu[] = {
958a4553358SHaojian Zhuang 	{
959a4553358SHaojian Zhuang 		.start	= 0x54000000,
960a4553358SHaojian Zhuang 		.end	= 0x54000fff,
961a4553358SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
962a4553358SHaojian Zhuang 	},
963a4553358SHaojian Zhuang 	{
964a4553358SHaojian Zhuang 		.start	= IRQ_GCU,
965a4553358SHaojian Zhuang 		.end	= IRQ_GCU,
966a4553358SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
967a4553358SHaojian Zhuang 	},
968a4553358SHaojian Zhuang };
969a4553358SHaojian Zhuang 
970a4553358SHaojian Zhuang static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
971a4553358SHaojian Zhuang 
972a4553358SHaojian Zhuang struct platform_device pxa3xx_device_gcu = {
973a4553358SHaojian Zhuang 	.name		= "pxa3xx-gcu",
974a4553358SHaojian Zhuang 	.id		= -1,
975a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_gcu),
976a4553358SHaojian Zhuang 	.resource	= pxa3xx_resources_gcu,
977a4553358SHaojian Zhuang 	.dev		= {
978a4553358SHaojian Zhuang 		.dma_mask = &pxa3xx_gcu_dmamask,
979a4553358SHaojian Zhuang 		.coherent_dma_mask = 0xffffffff,
980a4553358SHaojian Zhuang 	},
981a4553358SHaojian Zhuang };
982a4553358SHaojian Zhuang 
983a4553358SHaojian Zhuang #endif /* CONFIG_PXA3xx */
984a4553358SHaojian Zhuang 
98549ea7fc0SHaojian Zhuang #if defined(CONFIG_PXA3xx)
986a4553358SHaojian Zhuang static struct resource pxa3xx_resources_i2c_power[] = {
987a4553358SHaojian Zhuang 	{
988a4553358SHaojian Zhuang 		.start  = 0x40f500c0,
989a4553358SHaojian Zhuang 		.end    = 0x40f500d3,
990a4553358SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
991a4553358SHaojian Zhuang 	}, {
992a4553358SHaojian Zhuang 		.start	= IRQ_PWRI2C,
993a4553358SHaojian Zhuang 		.end	= IRQ_PWRI2C,
994a4553358SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
995a4553358SHaojian Zhuang 	},
996a4553358SHaojian Zhuang };
997a4553358SHaojian Zhuang 
998a4553358SHaojian Zhuang struct platform_device pxa3xx_device_i2c_power = {
999a4553358SHaojian Zhuang 	.name		= "pxa3xx-pwri2c",
1000a4553358SHaojian Zhuang 	.id		= 1,
1001a4553358SHaojian Zhuang 	.resource	= pxa3xx_resources_i2c_power,
1002a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_i2c_power),
1003a4553358SHaojian Zhuang };
1004a4553358SHaojian Zhuang 
10059ae819a8SEric Miao static struct resource pxa3xx_resources_nand[] = {
10069ae819a8SEric Miao 	[0] = {
10079ae819a8SEric Miao 		.start	= 0x43100000,
10089ae819a8SEric Miao 		.end	= 0x43100053,
10099ae819a8SEric Miao 		.flags	= IORESOURCE_MEM,
10109ae819a8SEric Miao 	},
10119ae819a8SEric Miao 	[1] = {
10129ae819a8SEric Miao 		.start	= IRQ_NAND,
10139ae819a8SEric Miao 		.end	= IRQ_NAND,
10149ae819a8SEric Miao 		.flags	= IORESOURCE_IRQ,
10159ae819a8SEric Miao 	},
10169ae819a8SEric Miao 	[2] = {
10179ae819a8SEric Miao 		/* DRCMR for Data DMA */
10189ae819a8SEric Miao 		.start	= 97,
10199ae819a8SEric Miao 		.end	= 97,
10209ae819a8SEric Miao 		.flags	= IORESOURCE_DMA,
10219ae819a8SEric Miao 	},
10229ae819a8SEric Miao 	[3] = {
10239ae819a8SEric Miao 		/* DRCMR for Command DMA */
10249ae819a8SEric Miao 		.start	= 99,
10259ae819a8SEric Miao 		.end	= 99,
10269ae819a8SEric Miao 		.flags	= IORESOURCE_DMA,
10279ae819a8SEric Miao 	},
10289ae819a8SEric Miao };
10299ae819a8SEric Miao 
10309ae819a8SEric Miao static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
10319ae819a8SEric Miao 
10329ae819a8SEric Miao struct platform_device pxa3xx_device_nand = {
10339ae819a8SEric Miao 	.name		= "pxa3xx-nand",
10349ae819a8SEric Miao 	.id		= -1,
10359ae819a8SEric Miao 	.dev		= {
10369ae819a8SEric Miao 		.dma_mask = &pxa3xx_nand_dma_mask,
10379ae819a8SEric Miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
10389ae819a8SEric Miao 	},
10399ae819a8SEric Miao 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_nand),
10409ae819a8SEric Miao 	.resource	= pxa3xx_resources_nand,
10419ae819a8SEric Miao };
10429ae819a8SEric Miao 
10439ae819a8SEric Miao void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
10449ae819a8SEric Miao {
10459ae819a8SEric Miao 	pxa_register_device(&pxa3xx_device_nand, info);
10469ae819a8SEric Miao }
10471ff2c33eSDaniel Mack 
1048a4553358SHaojian Zhuang static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
1049a4553358SHaojian Zhuang 
1050a4553358SHaojian Zhuang static struct resource pxa3xx_resource_ssp4[] = {
1051a4553358SHaojian Zhuang 	[0] = {
1052a4553358SHaojian Zhuang 		.start	= 0x41a00000,
1053a4553358SHaojian Zhuang 		.end	= 0x41a0003f,
10541ff2c33eSDaniel Mack 		.flags	= IORESOURCE_MEM,
10551ff2c33eSDaniel Mack 	},
1056a4553358SHaojian Zhuang 	[1] = {
1057a4553358SHaojian Zhuang 		.start	= IRQ_SSP4,
1058a4553358SHaojian Zhuang 		.end	= IRQ_SSP4,
10591ff2c33eSDaniel Mack 		.flags	= IORESOURCE_IRQ,
10601ff2c33eSDaniel Mack 	},
1061a4553358SHaojian Zhuang 	[2] = {
1062a4553358SHaojian Zhuang 		/* DRCMR for RX */
1063a4553358SHaojian Zhuang 		.start	= 2,
1064a4553358SHaojian Zhuang 		.end	= 2,
1065a4553358SHaojian Zhuang 		.flags	= IORESOURCE_DMA,
1066a4553358SHaojian Zhuang 	},
1067a4553358SHaojian Zhuang 	[3] = {
1068a4553358SHaojian Zhuang 		/* DRCMR for TX */
1069a4553358SHaojian Zhuang 		.start	= 3,
1070a4553358SHaojian Zhuang 		.end	= 3,
1071a4553358SHaojian Zhuang 		.flags	= IORESOURCE_DMA,
10721ff2c33eSDaniel Mack 	},
10731ff2c33eSDaniel Mack };
10741ff2c33eSDaniel Mack 
10750da0e227SDaniel Mack /*
10760da0e227SDaniel Mack  * PXA3xx SSP is basically equivalent to PXA27x.
10770da0e227SDaniel Mack  * However, we need to register the device by the correct name in order to
10780da0e227SDaniel Mack  * make the driver set the correct internal type, hence we provide specific
10790da0e227SDaniel Mack  * platform_devices for each of them.
10800da0e227SDaniel Mack  */
10810da0e227SDaniel Mack struct platform_device pxa3xx_device_ssp1 = {
10820da0e227SDaniel Mack 	.name		= "pxa3xx-ssp",
10830da0e227SDaniel Mack 	.id		= 0,
10840da0e227SDaniel Mack 	.dev		= {
10850da0e227SDaniel Mack 		.dma_mask = &pxa27x_ssp1_dma_mask,
10860da0e227SDaniel Mack 		.coherent_dma_mask = DMA_BIT_MASK(32),
10870da0e227SDaniel Mack 	},
10880da0e227SDaniel Mack 	.resource	= pxa27x_resource_ssp1,
10890da0e227SDaniel Mack 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
10900da0e227SDaniel Mack };
10910da0e227SDaniel Mack 
10920da0e227SDaniel Mack struct platform_device pxa3xx_device_ssp2 = {
10930da0e227SDaniel Mack 	.name		= "pxa3xx-ssp",
10940da0e227SDaniel Mack 	.id		= 1,
10950da0e227SDaniel Mack 	.dev		= {
10960da0e227SDaniel Mack 		.dma_mask = &pxa27x_ssp2_dma_mask,
10970da0e227SDaniel Mack 		.coherent_dma_mask = DMA_BIT_MASK(32),
10980da0e227SDaniel Mack 	},
10990da0e227SDaniel Mack 	.resource	= pxa27x_resource_ssp2,
11000da0e227SDaniel Mack 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
11010da0e227SDaniel Mack };
11020da0e227SDaniel Mack 
11030da0e227SDaniel Mack struct platform_device pxa3xx_device_ssp3 = {
11040da0e227SDaniel Mack 	.name		= "pxa3xx-ssp",
11050da0e227SDaniel Mack 	.id		= 2,
11060da0e227SDaniel Mack 	.dev		= {
11070da0e227SDaniel Mack 		.dma_mask = &pxa27x_ssp3_dma_mask,
11080da0e227SDaniel Mack 		.coherent_dma_mask = DMA_BIT_MASK(32),
11090da0e227SDaniel Mack 	},
11100da0e227SDaniel Mack 	.resource	= pxa27x_resource_ssp3,
11110da0e227SDaniel Mack 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
11120da0e227SDaniel Mack };
11130da0e227SDaniel Mack 
1114a4553358SHaojian Zhuang struct platform_device pxa3xx_device_ssp4 = {
11150da0e227SDaniel Mack 	.name		= "pxa3xx-ssp",
1116a4553358SHaojian Zhuang 	.id		= 3,
1117a4553358SHaojian Zhuang 	.dev		= {
1118a4553358SHaojian Zhuang 		.dma_mask = &pxa3xx_ssp4_dma_mask,
1119a4553358SHaojian Zhuang 		.coherent_dma_mask = DMA_BIT_MASK(32),
1120a4553358SHaojian Zhuang 	},
1121a4553358SHaojian Zhuang 	.resource	= pxa3xx_resource_ssp4,
1122a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa3xx_resource_ssp4),
1123a4553358SHaojian Zhuang };
112449ea7fc0SHaojian Zhuang #endif /* CONFIG_PXA3xx */
1125e172274cSGuennadi Liakhovetski 
1126157d2644SHaojian Zhuang struct resource pxa_resource_gpio[] = {
1127157d2644SHaojian Zhuang 	{
1128157d2644SHaojian Zhuang 		.start	= 0x40e00000,
1129157d2644SHaojian Zhuang 		.end	= 0x40e0ffff,
1130157d2644SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
1131157d2644SHaojian Zhuang 	}, {
1132157d2644SHaojian Zhuang 		.start	= IRQ_GPIO0,
1133157d2644SHaojian Zhuang 		.end	= IRQ_GPIO0,
1134157d2644SHaojian Zhuang 		.name	= "gpio0",
1135157d2644SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1136157d2644SHaojian Zhuang 	}, {
1137157d2644SHaojian Zhuang 		.start	= IRQ_GPIO1,
1138157d2644SHaojian Zhuang 		.end	= IRQ_GPIO1,
1139157d2644SHaojian Zhuang 		.name	= "gpio1",
1140157d2644SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1141157d2644SHaojian Zhuang 	}, {
1142157d2644SHaojian Zhuang 		.start	= IRQ_GPIO_2_x,
1143157d2644SHaojian Zhuang 		.end	= IRQ_GPIO_2_x,
1144157d2644SHaojian Zhuang 		.name	= "gpio_mux",
1145157d2644SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1146157d2644SHaojian Zhuang 	},
1147157d2644SHaojian Zhuang };
1148157d2644SHaojian Zhuang 
11492cab0292SHaojian Zhuang struct platform_device pxa25x_device_gpio = {
11502cab0292SHaojian Zhuang #ifdef CONFIG_CPU_PXA26x
11512cab0292SHaojian Zhuang 	.name		= "pxa26x-gpio",
11522cab0292SHaojian Zhuang #else
11532cab0292SHaojian Zhuang 	.name		= "pxa25x-gpio",
11542cab0292SHaojian Zhuang #endif
11552cab0292SHaojian Zhuang 	.id		= -1,
11562cab0292SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa_resource_gpio),
11572cab0292SHaojian Zhuang 	.resource	= pxa_resource_gpio,
11582cab0292SHaojian Zhuang };
11592cab0292SHaojian Zhuang 
11602cab0292SHaojian Zhuang struct platform_device pxa27x_device_gpio = {
11612cab0292SHaojian Zhuang 	.name		= "pxa27x-gpio",
11622cab0292SHaojian Zhuang 	.id		= -1,
11632cab0292SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa_resource_gpio),
11642cab0292SHaojian Zhuang 	.resource	= pxa_resource_gpio,
11652cab0292SHaojian Zhuang };
11662cab0292SHaojian Zhuang 
11672cab0292SHaojian Zhuang struct platform_device pxa3xx_device_gpio = {
11682cab0292SHaojian Zhuang 	.name		= "pxa3xx-gpio",
11692cab0292SHaojian Zhuang 	.id		= -1,
11702cab0292SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa_resource_gpio),
11712cab0292SHaojian Zhuang 	.resource	= pxa_resource_gpio,
11722cab0292SHaojian Zhuang };
11732cab0292SHaojian Zhuang 
11742cab0292SHaojian Zhuang struct platform_device pxa93x_device_gpio = {
11752cab0292SHaojian Zhuang 	.name		= "pxa93x-gpio",
1176157d2644SHaojian Zhuang 	.id		= -1,
1177157d2644SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa_resource_gpio),
1178157d2644SHaojian Zhuang 	.resource	= pxa_resource_gpio,
1179157d2644SHaojian Zhuang };
1180157d2644SHaojian Zhuang 
1181e172274cSGuennadi Liakhovetski /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
1182e172274cSGuennadi Liakhovetski  * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
1183e172274cSGuennadi Liakhovetski void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
1184e172274cSGuennadi Liakhovetski {
1185e172274cSGuennadi Liakhovetski 	struct platform_device *pd;
1186e172274cSGuennadi Liakhovetski 
1187e172274cSGuennadi Liakhovetski 	pd = platform_device_alloc("pxa2xx-spi", id);
1188e172274cSGuennadi Liakhovetski 	if (pd == NULL) {
1189e172274cSGuennadi Liakhovetski 		printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
1190e172274cSGuennadi Liakhovetski 		       id);
1191e172274cSGuennadi Liakhovetski 		return;
1192e172274cSGuennadi Liakhovetski 	}
1193e172274cSGuennadi Liakhovetski 
1194e172274cSGuennadi Liakhovetski 	pd->dev.platform_data = info;
1195e172274cSGuennadi Liakhovetski 	platform_device_add(pd);
1196e172274cSGuennadi Liakhovetski }
1197*4be0856fSRobert Jarzmik 
1198*4be0856fSRobert Jarzmik static struct mmp_dma_platdata pxa_dma_pdata = {
1199*4be0856fSRobert Jarzmik 	.dma_channels	= 0,
1200*4be0856fSRobert Jarzmik };
1201*4be0856fSRobert Jarzmik 
1202*4be0856fSRobert Jarzmik static struct resource pxa_dma_resource[] = {
1203*4be0856fSRobert Jarzmik 	[0] = {
1204*4be0856fSRobert Jarzmik 		.start	= 0x40000000,
1205*4be0856fSRobert Jarzmik 		.end	= 0x4000ffff,
1206*4be0856fSRobert Jarzmik 		.flags	= IORESOURCE_MEM,
1207*4be0856fSRobert Jarzmik 	},
1208*4be0856fSRobert Jarzmik 	[1] = {
1209*4be0856fSRobert Jarzmik 		.start	= IRQ_DMA,
1210*4be0856fSRobert Jarzmik 		.end	= IRQ_DMA,
1211*4be0856fSRobert Jarzmik 		.flags	= IORESOURCE_IRQ,
1212*4be0856fSRobert Jarzmik 	},
1213*4be0856fSRobert Jarzmik };
1214*4be0856fSRobert Jarzmik 
1215*4be0856fSRobert Jarzmik static u64 pxadma_dmamask = 0xffffffffUL;
1216*4be0856fSRobert Jarzmik 
1217*4be0856fSRobert Jarzmik static struct platform_device pxa2xx_pxa_dma = {
1218*4be0856fSRobert Jarzmik 	.name		= "pxa-dma",
1219*4be0856fSRobert Jarzmik 	.id		= 0,
1220*4be0856fSRobert Jarzmik 	.dev		= {
1221*4be0856fSRobert Jarzmik 		.dma_mask = &pxadma_dmamask,
1222*4be0856fSRobert Jarzmik 		.coherent_dma_mask = 0xffffffff,
1223*4be0856fSRobert Jarzmik 	},
1224*4be0856fSRobert Jarzmik 	.num_resources	= ARRAY_SIZE(pxa_dma_resource),
1225*4be0856fSRobert Jarzmik 	.resource	= pxa_dma_resource,
1226*4be0856fSRobert Jarzmik };
1227*4be0856fSRobert Jarzmik 
1228*4be0856fSRobert Jarzmik void __init pxa2xx_set_dmac_info(int nb_channels)
1229*4be0856fSRobert Jarzmik {
1230*4be0856fSRobert Jarzmik 	pxa_dma_pdata.dma_channels = nb_channels;
1231*4be0856fSRobert Jarzmik 	pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata);
1232*4be0856fSRobert Jarzmik }
1233