xref: /linux/arch/arm/mach-pxa/devices.c (revision 37320980414f5a7654ee08a047194224c6bba46e)
18f58de7cSeric miao #include <linux/module.h>
28f58de7cSeric miao #include <linux/kernel.h>
38f58de7cSeric miao #include <linux/init.h>
48f58de7cSeric miao #include <linux/platform_device.h>
58f58de7cSeric miao #include <linux/dma-mapping.h>
68f58de7cSeric miao 
78f58de7cSeric miao #include <asm/arch/gpio.h>
88f58de7cSeric miao #include <asm/arch/udc.h>
98f58de7cSeric miao #include <asm/arch/pxafb.h>
108f58de7cSeric miao #include <asm/arch/mmc.h>
118f58de7cSeric miao #include <asm/arch/irda.h>
128f58de7cSeric miao #include <asm/arch/i2c.h>
13cd5604d5Seric miao #include <asm/arch/ohci.h>
14*37320980Seric miao #include <asm/arch/pxa27x_keypad.h>
158f58de7cSeric miao 
168f58de7cSeric miao #include "devices.h"
178f58de7cSeric miao 
188f58de7cSeric miao void __init pxa_register_device(struct platform_device *dev, void *data)
198f58de7cSeric miao {
208f58de7cSeric miao 	int ret;
218f58de7cSeric miao 
228f58de7cSeric miao 	dev->dev.platform_data = data;
238f58de7cSeric miao 
248f58de7cSeric miao 	ret = platform_device_register(dev);
258f58de7cSeric miao 	if (ret)
268f58de7cSeric miao 		dev_err(&dev->dev, "unable to register device: %d\n", ret);
278f58de7cSeric miao }
288f58de7cSeric miao 
298f58de7cSeric miao static struct resource pxamci_resources[] = {
308f58de7cSeric miao 	[0] = {
318f58de7cSeric miao 		.start	= 0x41100000,
328f58de7cSeric miao 		.end	= 0x41100fff,
338f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
348f58de7cSeric miao 	},
358f58de7cSeric miao 	[1] = {
368f58de7cSeric miao 		.start	= IRQ_MMC,
378f58de7cSeric miao 		.end	= IRQ_MMC,
388f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
398f58de7cSeric miao 	},
408f58de7cSeric miao 	[2] = {
418f58de7cSeric miao 		.start	= 21,
428f58de7cSeric miao 		.end	= 21,
438f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
448f58de7cSeric miao 	},
458f58de7cSeric miao 	[3] = {
468f58de7cSeric miao 		.start	= 22,
478f58de7cSeric miao 		.end	= 22,
488f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
498f58de7cSeric miao 	},
508f58de7cSeric miao };
518f58de7cSeric miao 
528f58de7cSeric miao static u64 pxamci_dmamask = 0xffffffffUL;
538f58de7cSeric miao 
548f58de7cSeric miao struct platform_device pxa_device_mci = {
558f58de7cSeric miao 	.name		= "pxa2xx-mci",
56fafc9d3fSBridge Wu 	.id		= 0,
578f58de7cSeric miao 	.dev		= {
588f58de7cSeric miao 		.dma_mask = &pxamci_dmamask,
598f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
608f58de7cSeric miao 	},
618f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxamci_resources),
628f58de7cSeric miao 	.resource	= pxamci_resources,
638f58de7cSeric miao };
648f58de7cSeric miao 
658f58de7cSeric miao void __init pxa_set_mci_info(struct pxamci_platform_data *info)
668f58de7cSeric miao {
678f58de7cSeric miao 	pxa_register_device(&pxa_device_mci, info);
688f58de7cSeric miao }
698f58de7cSeric miao 
708f58de7cSeric miao 
718f58de7cSeric miao static struct pxa2xx_udc_mach_info pxa_udc_info;
728f58de7cSeric miao 
738f58de7cSeric miao void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
748f58de7cSeric miao {
758f58de7cSeric miao 	memcpy(&pxa_udc_info, info, sizeof *info);
768f58de7cSeric miao }
778f58de7cSeric miao 
788f58de7cSeric miao static struct resource pxa2xx_udc_resources[] = {
798f58de7cSeric miao 	[0] = {
808f58de7cSeric miao 		.start	= 0x40600000,
818f58de7cSeric miao 		.end	= 0x4060ffff,
828f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
838f58de7cSeric miao 	},
848f58de7cSeric miao 	[1] = {
858f58de7cSeric miao 		.start	= IRQ_USB,
868f58de7cSeric miao 		.end	= IRQ_USB,
878f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
888f58de7cSeric miao 	},
898f58de7cSeric miao };
908f58de7cSeric miao 
918f58de7cSeric miao static u64 udc_dma_mask = ~(u32)0;
928f58de7cSeric miao 
938f58de7cSeric miao struct platform_device pxa_device_udc = {
948f58de7cSeric miao 	.name		= "pxa2xx-udc",
958f58de7cSeric miao 	.id		= -1,
968f58de7cSeric miao 	.resource	= pxa2xx_udc_resources,
978f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
988f58de7cSeric miao 	.dev		=  {
998f58de7cSeric miao 		.platform_data	= &pxa_udc_info,
1008f58de7cSeric miao 		.dma_mask	= &udc_dma_mask,
1018f58de7cSeric miao 	}
1028f58de7cSeric miao };
1038f58de7cSeric miao 
1048f58de7cSeric miao static struct resource pxafb_resources[] = {
1058f58de7cSeric miao 	[0] = {
1068f58de7cSeric miao 		.start	= 0x44000000,
1078f58de7cSeric miao 		.end	= 0x4400ffff,
1088f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1098f58de7cSeric miao 	},
1108f58de7cSeric miao 	[1] = {
1118f58de7cSeric miao 		.start	= IRQ_LCD,
1128f58de7cSeric miao 		.end	= IRQ_LCD,
1138f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1148f58de7cSeric miao 	},
1158f58de7cSeric miao };
1168f58de7cSeric miao 
1178f58de7cSeric miao static u64 fb_dma_mask = ~(u64)0;
1188f58de7cSeric miao 
1198f58de7cSeric miao struct platform_device pxa_device_fb = {
1208f58de7cSeric miao 	.name		= "pxa2xx-fb",
1218f58de7cSeric miao 	.id		= -1,
1228f58de7cSeric miao 	.dev		= {
1238f58de7cSeric miao 		.dma_mask	= &fb_dma_mask,
1248f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
1258f58de7cSeric miao 	},
1268f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxafb_resources),
1278f58de7cSeric miao 	.resource	= pxafb_resources,
1288f58de7cSeric miao };
1298f58de7cSeric miao 
1308f58de7cSeric miao void __init set_pxa_fb_info(struct pxafb_mach_info *info)
1318f58de7cSeric miao {
1328f58de7cSeric miao 	pxa_register_device(&pxa_device_fb, info);
1338f58de7cSeric miao }
1348f58de7cSeric miao 
1358f58de7cSeric miao void __init set_pxa_fb_parent(struct device *parent_dev)
1368f58de7cSeric miao {
1378f58de7cSeric miao 	pxa_device_fb.dev.parent = parent_dev;
1388f58de7cSeric miao }
1398f58de7cSeric miao 
1408f58de7cSeric miao static struct resource pxa_resource_ffuart[] = {
1418f58de7cSeric miao 	{
1428f58de7cSeric miao 		.start	= __PREG(FFUART),
1438f58de7cSeric miao 		.end	= __PREG(FFUART) + 35,
1448f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1458f58de7cSeric miao 	}, {
1468f58de7cSeric miao 		.start	= IRQ_FFUART,
1478f58de7cSeric miao 		.end	= IRQ_FFUART,
1488f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1498f58de7cSeric miao 	}
1508f58de7cSeric miao };
1518f58de7cSeric miao 
1528f58de7cSeric miao struct platform_device pxa_device_ffuart= {
1538f58de7cSeric miao 	.name		= "pxa2xx-uart",
1548f58de7cSeric miao 	.id		= 0,
1558f58de7cSeric miao 	.resource	= pxa_resource_ffuart,
1568f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_ffuart),
1578f58de7cSeric miao };
1588f58de7cSeric miao 
1598f58de7cSeric miao static struct resource pxa_resource_btuart[] = {
1608f58de7cSeric miao 	{
1618f58de7cSeric miao 		.start	= __PREG(BTUART),
1628f58de7cSeric miao 		.end	= __PREG(BTUART) + 35,
1638f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1648f58de7cSeric miao 	}, {
1658f58de7cSeric miao 		.start	= IRQ_BTUART,
1668f58de7cSeric miao 		.end	= IRQ_BTUART,
1678f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1688f58de7cSeric miao 	}
1698f58de7cSeric miao };
1708f58de7cSeric miao 
1718f58de7cSeric miao struct platform_device pxa_device_btuart = {
1728f58de7cSeric miao 	.name		= "pxa2xx-uart",
1738f58de7cSeric miao 	.id		= 1,
1748f58de7cSeric miao 	.resource	= pxa_resource_btuart,
1758f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_btuart),
1768f58de7cSeric miao };
1778f58de7cSeric miao 
1788f58de7cSeric miao static struct resource pxa_resource_stuart[] = {
1798f58de7cSeric miao 	{
1808f58de7cSeric miao 		.start	= __PREG(STUART),
1818f58de7cSeric miao 		.end	= __PREG(STUART) + 35,
1828f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1838f58de7cSeric miao 	}, {
1848f58de7cSeric miao 		.start	= IRQ_STUART,
1858f58de7cSeric miao 		.end	= IRQ_STUART,
1868f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1878f58de7cSeric miao 	}
1888f58de7cSeric miao };
1898f58de7cSeric miao 
1908f58de7cSeric miao struct platform_device pxa_device_stuart = {
1918f58de7cSeric miao 	.name		= "pxa2xx-uart",
1928f58de7cSeric miao 	.id		= 2,
1938f58de7cSeric miao 	.resource	= pxa_resource_stuart,
1948f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_stuart),
1958f58de7cSeric miao };
1968f58de7cSeric miao 
1978f58de7cSeric miao static struct resource pxa_resource_hwuart[] = {
1988f58de7cSeric miao 	{
1998f58de7cSeric miao 		.start	= __PREG(HWUART),
2008f58de7cSeric miao 		.end	= __PREG(HWUART) + 47,
2018f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2028f58de7cSeric miao 	}, {
2038f58de7cSeric miao 		.start	= IRQ_HWUART,
2048f58de7cSeric miao 		.end	= IRQ_HWUART,
2058f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2068f58de7cSeric miao 	}
2078f58de7cSeric miao };
2088f58de7cSeric miao 
2098f58de7cSeric miao struct platform_device pxa_device_hwuart = {
2108f58de7cSeric miao 	.name		= "pxa2xx-uart",
2118f58de7cSeric miao 	.id		= 3,
2128f58de7cSeric miao 	.resource	= pxa_resource_hwuart,
2138f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
2148f58de7cSeric miao };
2158f58de7cSeric miao 
2168f58de7cSeric miao static struct resource pxai2c_resources[] = {
2178f58de7cSeric miao 	{
2188f58de7cSeric miao 		.start	= 0x40301680,
2198f58de7cSeric miao 		.end	= 0x403016a3,
2208f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2218f58de7cSeric miao 	}, {
2228f58de7cSeric miao 		.start	= IRQ_I2C,
2238f58de7cSeric miao 		.end	= IRQ_I2C,
2248f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2258f58de7cSeric miao 	},
2268f58de7cSeric miao };
2278f58de7cSeric miao 
2288f58de7cSeric miao struct platform_device pxa_device_i2c = {
2298f58de7cSeric miao 	.name		= "pxa2xx-i2c",
2308f58de7cSeric miao 	.id		= 0,
2318f58de7cSeric miao 	.resource	= pxai2c_resources,
2328f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2c_resources),
2338f58de7cSeric miao };
2348f58de7cSeric miao 
2358f58de7cSeric miao void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
2368f58de7cSeric miao {
2378f58de7cSeric miao 	pxa_register_device(&pxa_device_i2c, info);
2388f58de7cSeric miao }
2398f58de7cSeric miao 
2408f58de7cSeric miao static struct resource pxai2s_resources[] = {
2418f58de7cSeric miao 	{
2428f58de7cSeric miao 		.start	= 0x40400000,
2438f58de7cSeric miao 		.end	= 0x40400083,
2448f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2458f58de7cSeric miao 	}, {
2468f58de7cSeric miao 		.start	= IRQ_I2S,
2478f58de7cSeric miao 		.end	= IRQ_I2S,
2488f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2498f58de7cSeric miao 	},
2508f58de7cSeric miao };
2518f58de7cSeric miao 
2528f58de7cSeric miao struct platform_device pxa_device_i2s = {
2538f58de7cSeric miao 	.name		= "pxa2xx-i2s",
2548f58de7cSeric miao 	.id		= -1,
2558f58de7cSeric miao 	.resource	= pxai2s_resources,
2568f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2s_resources),
2578f58de7cSeric miao };
2588f58de7cSeric miao 
2598f58de7cSeric miao static u64 pxaficp_dmamask = ~(u32)0;
2608f58de7cSeric miao 
2618f58de7cSeric miao struct platform_device pxa_device_ficp = {
2628f58de7cSeric miao 	.name		= "pxa2xx-ir",
2638f58de7cSeric miao 	.id		= -1,
2648f58de7cSeric miao 	.dev		= {
2658f58de7cSeric miao 		.dma_mask = &pxaficp_dmamask,
2668f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
2678f58de7cSeric miao 	},
2688f58de7cSeric miao };
2698f58de7cSeric miao 
2708f58de7cSeric miao void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
2718f58de7cSeric miao {
2728f58de7cSeric miao 	pxa_register_device(&pxa_device_ficp, info);
2738f58de7cSeric miao }
2748f58de7cSeric miao 
2758f58de7cSeric miao struct platform_device pxa_device_rtc = {
2768f58de7cSeric miao 	.name		= "sa1100-rtc",
2778f58de7cSeric miao 	.id		= -1,
2788f58de7cSeric miao };
2798f58de7cSeric miao 
2808f58de7cSeric miao #ifdef CONFIG_PXA25x
2818f58de7cSeric miao 
2828f58de7cSeric miao static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
2838f58de7cSeric miao 
2848f58de7cSeric miao static struct resource pxa25x_resource_ssp[] = {
2858f58de7cSeric miao 	[0] = {
2868f58de7cSeric miao 		.start	= 0x41000000,
2878f58de7cSeric miao 		.end	= 0x4100001f,
2888f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2898f58de7cSeric miao 	},
2908f58de7cSeric miao 	[1] = {
2918f58de7cSeric miao 		.start	= IRQ_SSP,
2928f58de7cSeric miao 		.end	= IRQ_SSP,
2938f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2948f58de7cSeric miao 	},
2958f58de7cSeric miao 	[2] = {
2968f58de7cSeric miao 		/* DRCMR for RX */
2978f58de7cSeric miao 		.start	= 13,
2988f58de7cSeric miao 		.end	= 13,
2998f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
3008f58de7cSeric miao 	},
3018f58de7cSeric miao 	[3] = {
3028f58de7cSeric miao 		/* DRCMR for TX */
3038f58de7cSeric miao 		.start	= 14,
3048f58de7cSeric miao 		.end	= 14,
3058f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
3068f58de7cSeric miao 	},
3078f58de7cSeric miao };
3088f58de7cSeric miao 
3098f58de7cSeric miao struct platform_device pxa25x_device_ssp = {
3108f58de7cSeric miao 	.name		= "pxa25x-ssp",
3118f58de7cSeric miao 	.id		= 0,
3128f58de7cSeric miao 	.dev		= {
3138f58de7cSeric miao 		.dma_mask = &pxa25x_ssp_dma_mask,
3148f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
3158f58de7cSeric miao 	},
3168f58de7cSeric miao 	.resource	= pxa25x_resource_ssp,
3178f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_ssp),
3188f58de7cSeric miao };
3198f58de7cSeric miao 
3208f58de7cSeric miao static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
3218f58de7cSeric miao 
3228f58de7cSeric miao static struct resource pxa25x_resource_nssp[] = {
3238f58de7cSeric miao 	[0] = {
3248f58de7cSeric miao 		.start	= 0x41400000,
3258f58de7cSeric miao 		.end	= 0x4140002f,
3268f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3278f58de7cSeric miao 	},
3288f58de7cSeric miao 	[1] = {
3298f58de7cSeric miao 		.start	= IRQ_NSSP,
3308f58de7cSeric miao 		.end	= IRQ_NSSP,
3318f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3328f58de7cSeric miao 	},
3338f58de7cSeric miao 	[2] = {
3348f58de7cSeric miao 		/* DRCMR for RX */
3358f58de7cSeric miao 		.start	= 15,
3368f58de7cSeric miao 		.end	= 15,
3378f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
3388f58de7cSeric miao 	},
3398f58de7cSeric miao 	[3] = {
3408f58de7cSeric miao 		/* DRCMR for TX */
3418f58de7cSeric miao 		.start	= 16,
3428f58de7cSeric miao 		.end	= 16,
3438f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
3448f58de7cSeric miao 	},
3458f58de7cSeric miao };
3468f58de7cSeric miao 
3478f58de7cSeric miao struct platform_device pxa25x_device_nssp = {
3488f58de7cSeric miao 	.name		= "pxa25x-nssp",
3498f58de7cSeric miao 	.id		= 1,
3508f58de7cSeric miao 	.dev		= {
3518f58de7cSeric miao 		.dma_mask = &pxa25x_nssp_dma_mask,
3528f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
3538f58de7cSeric miao 	},
3548f58de7cSeric miao 	.resource	= pxa25x_resource_nssp,
3558f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_nssp),
3568f58de7cSeric miao };
3578f58de7cSeric miao 
3588f58de7cSeric miao static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
3598f58de7cSeric miao 
3608f58de7cSeric miao static struct resource pxa25x_resource_assp[] = {
3618f58de7cSeric miao 	[0] = {
3628f58de7cSeric miao 		.start	= 0x41500000,
3638f58de7cSeric miao 		.end	= 0x4150002f,
3648f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3658f58de7cSeric miao 	},
3668f58de7cSeric miao 	[1] = {
3678f58de7cSeric miao 		.start	= IRQ_ASSP,
3688f58de7cSeric miao 		.end	= IRQ_ASSP,
3698f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3708f58de7cSeric miao 	},
3718f58de7cSeric miao 	[2] = {
3728f58de7cSeric miao 		/* DRCMR for RX */
3738f58de7cSeric miao 		.start	= 23,
3748f58de7cSeric miao 		.end	= 23,
3758f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
3768f58de7cSeric miao 	},
3778f58de7cSeric miao 	[3] = {
3788f58de7cSeric miao 		/* DRCMR for TX */
3798f58de7cSeric miao 		.start	= 24,
3808f58de7cSeric miao 		.end	= 24,
3818f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
3828f58de7cSeric miao 	},
3838f58de7cSeric miao };
3848f58de7cSeric miao 
3858f58de7cSeric miao struct platform_device pxa25x_device_assp = {
3868f58de7cSeric miao 	/* ASSP is basically equivalent to NSSP */
3878f58de7cSeric miao 	.name		= "pxa25x-nssp",
3888f58de7cSeric miao 	.id		= 2,
3898f58de7cSeric miao 	.dev		= {
3908f58de7cSeric miao 		.dma_mask = &pxa25x_assp_dma_mask,
3918f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
3928f58de7cSeric miao 	},
3938f58de7cSeric miao 	.resource	= pxa25x_resource_assp,
3948f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_assp),
3958f58de7cSeric miao };
3968f58de7cSeric miao #endif /* CONFIG_PXA25x */
3978f58de7cSeric miao 
3988f58de7cSeric miao #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
3998f58de7cSeric miao 
400*37320980Seric miao static struct resource pxa27x_resource_keypad[] = {
401*37320980Seric miao 	[0] = {
402*37320980Seric miao 		.start	= 0x41500000,
403*37320980Seric miao 		.end	= 0x4150004c,
404*37320980Seric miao 		.flags	= IORESOURCE_MEM,
405*37320980Seric miao 	},
406*37320980Seric miao 	[1] = {
407*37320980Seric miao 		.start	= IRQ_KEYPAD,
408*37320980Seric miao 		.end	= IRQ_KEYPAD,
409*37320980Seric miao 		.flags	= IORESOURCE_IRQ,
410*37320980Seric miao 	},
411*37320980Seric miao };
412*37320980Seric miao 
413*37320980Seric miao struct platform_device pxa27x_device_keypad = {
414*37320980Seric miao 	.name		= "pxa27x-keypad",
415*37320980Seric miao 	.id		= -1,
416*37320980Seric miao 	.resource	= pxa27x_resource_keypad,
417*37320980Seric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_keypad),
418*37320980Seric miao };
419*37320980Seric miao 
420*37320980Seric miao void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
421*37320980Seric miao {
422*37320980Seric miao 	pxa_register_device(&pxa27x_device_keypad, info);
423*37320980Seric miao }
424*37320980Seric miao 
425ec68e45bSeric miao static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
426ec68e45bSeric miao 
427ec68e45bSeric miao static struct resource pxa27x_resource_ohci[] = {
428ec68e45bSeric miao 	[0] = {
429ec68e45bSeric miao 		.start  = 0x4C000000,
430ec68e45bSeric miao 		.end    = 0x4C00ff6f,
431ec68e45bSeric miao 		.flags  = IORESOURCE_MEM,
432ec68e45bSeric miao 	},
433ec68e45bSeric miao 	[1] = {
434ec68e45bSeric miao 		.start  = IRQ_USBH1,
435ec68e45bSeric miao 		.end    = IRQ_USBH1,
436ec68e45bSeric miao 		.flags  = IORESOURCE_IRQ,
437ec68e45bSeric miao 	},
438ec68e45bSeric miao };
439ec68e45bSeric miao 
440ec68e45bSeric miao struct platform_device pxa27x_device_ohci = {
441ec68e45bSeric miao 	.name		= "pxa27x-ohci",
442ec68e45bSeric miao 	.id		= -1,
443ec68e45bSeric miao 	.dev		= {
444ec68e45bSeric miao 		.dma_mask = &pxa27x_ohci_dma_mask,
445ec68e45bSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
446ec68e45bSeric miao 	},
447ec68e45bSeric miao 	.num_resources  = ARRAY_SIZE(pxa27x_resource_ohci),
448ec68e45bSeric miao 	.resource       = pxa27x_resource_ohci,
449ec68e45bSeric miao };
450ec68e45bSeric miao 
451ec68e45bSeric miao void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
452ec68e45bSeric miao {
453ec68e45bSeric miao 	pxa_register_device(&pxa27x_device_ohci, info);
454ec68e45bSeric miao }
455ec68e45bSeric miao 
4568f58de7cSeric miao static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
4578f58de7cSeric miao 
4588f58de7cSeric miao static struct resource pxa27x_resource_ssp1[] = {
4598f58de7cSeric miao 	[0] = {
4608f58de7cSeric miao 		.start	= 0x41000000,
4618f58de7cSeric miao 		.end	= 0x4100003f,
4628f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
4638f58de7cSeric miao 	},
4648f58de7cSeric miao 	[1] = {
4658f58de7cSeric miao 		.start	= IRQ_SSP,
4668f58de7cSeric miao 		.end	= IRQ_SSP,
4678f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
4688f58de7cSeric miao 	},
4698f58de7cSeric miao 	[2] = {
4708f58de7cSeric miao 		/* DRCMR for RX */
4718f58de7cSeric miao 		.start	= 13,
4728f58de7cSeric miao 		.end	= 13,
4738f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
4748f58de7cSeric miao 	},
4758f58de7cSeric miao 	[3] = {
4768f58de7cSeric miao 		/* DRCMR for TX */
4778f58de7cSeric miao 		.start	= 14,
4788f58de7cSeric miao 		.end	= 14,
4798f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
4808f58de7cSeric miao 	},
4818f58de7cSeric miao };
4828f58de7cSeric miao 
4838f58de7cSeric miao struct platform_device pxa27x_device_ssp1 = {
4848f58de7cSeric miao 	.name		= "pxa27x-ssp",
4858f58de7cSeric miao 	.id		= 0,
4868f58de7cSeric miao 	.dev		= {
4878f58de7cSeric miao 		.dma_mask = &pxa27x_ssp1_dma_mask,
4888f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
4898f58de7cSeric miao 	},
4908f58de7cSeric miao 	.resource	= pxa27x_resource_ssp1,
4918f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
4928f58de7cSeric miao };
4938f58de7cSeric miao 
4948f58de7cSeric miao static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
4958f58de7cSeric miao 
4968f58de7cSeric miao static struct resource pxa27x_resource_ssp2[] = {
4978f58de7cSeric miao 	[0] = {
4988f58de7cSeric miao 		.start	= 0x41700000,
4998f58de7cSeric miao 		.end	= 0x4170003f,
5008f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5018f58de7cSeric miao 	},
5028f58de7cSeric miao 	[1] = {
5038f58de7cSeric miao 		.start	= IRQ_SSP2,
5048f58de7cSeric miao 		.end	= IRQ_SSP2,
5058f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5068f58de7cSeric miao 	},
5078f58de7cSeric miao 	[2] = {
5088f58de7cSeric miao 		/* DRCMR for RX */
5098f58de7cSeric miao 		.start	= 15,
5108f58de7cSeric miao 		.end	= 15,
5118f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5128f58de7cSeric miao 	},
5138f58de7cSeric miao 	[3] = {
5148f58de7cSeric miao 		/* DRCMR for TX */
5158f58de7cSeric miao 		.start	= 16,
5168f58de7cSeric miao 		.end	= 16,
5178f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5188f58de7cSeric miao 	},
5198f58de7cSeric miao };
5208f58de7cSeric miao 
5218f58de7cSeric miao struct platform_device pxa27x_device_ssp2 = {
5228f58de7cSeric miao 	.name		= "pxa27x-ssp",
5238f58de7cSeric miao 	.id		= 1,
5248f58de7cSeric miao 	.dev		= {
5258f58de7cSeric miao 		.dma_mask = &pxa27x_ssp2_dma_mask,
5268f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
5278f58de7cSeric miao 	},
5288f58de7cSeric miao 	.resource	= pxa27x_resource_ssp2,
5298f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
5308f58de7cSeric miao };
5318f58de7cSeric miao 
5328f58de7cSeric miao static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
5338f58de7cSeric miao 
5348f58de7cSeric miao static struct resource pxa27x_resource_ssp3[] = {
5358f58de7cSeric miao 	[0] = {
5368f58de7cSeric miao 		.start	= 0x41900000,
5378f58de7cSeric miao 		.end	= 0x4190003f,
5388f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5398f58de7cSeric miao 	},
5408f58de7cSeric miao 	[1] = {
5418f58de7cSeric miao 		.start	= IRQ_SSP3,
5428f58de7cSeric miao 		.end	= IRQ_SSP3,
5438f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5448f58de7cSeric miao 	},
5458f58de7cSeric miao 	[2] = {
5468f58de7cSeric miao 		/* DRCMR for RX */
5478f58de7cSeric miao 		.start	= 66,
5488f58de7cSeric miao 		.end	= 66,
5498f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5508f58de7cSeric miao 	},
5518f58de7cSeric miao 	[3] = {
5528f58de7cSeric miao 		/* DRCMR for TX */
5538f58de7cSeric miao 		.start	= 67,
5548f58de7cSeric miao 		.end	= 67,
5558f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5568f58de7cSeric miao 	},
5578f58de7cSeric miao };
5588f58de7cSeric miao 
5598f58de7cSeric miao struct platform_device pxa27x_device_ssp3 = {
5608f58de7cSeric miao 	.name		= "pxa27x-ssp",
5618f58de7cSeric miao 	.id		= 2,
5628f58de7cSeric miao 	.dev		= {
5638f58de7cSeric miao 		.dma_mask = &pxa27x_ssp3_dma_mask,
5648f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
5658f58de7cSeric miao 	},
5668f58de7cSeric miao 	.resource	= pxa27x_resource_ssp3,
5678f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
5688f58de7cSeric miao };
5698f58de7cSeric miao #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
5708f58de7cSeric miao 
5718f58de7cSeric miao #ifdef CONFIG_PXA3xx
5728f58de7cSeric miao static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
5738f58de7cSeric miao 
5748f58de7cSeric miao static struct resource pxa3xx_resource_ssp4[] = {
5758f58de7cSeric miao 	[0] = {
5768f58de7cSeric miao 		.start	= 0x41a00000,
5778f58de7cSeric miao 		.end	= 0x41a0003f,
5788f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5798f58de7cSeric miao 	},
5808f58de7cSeric miao 	[1] = {
5818f58de7cSeric miao 		.start	= IRQ_SSP4,
5828f58de7cSeric miao 		.end	= IRQ_SSP4,
5838f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5848f58de7cSeric miao 	},
5858f58de7cSeric miao 	[2] = {
5868f58de7cSeric miao 		/* DRCMR for RX */
5878f58de7cSeric miao 		.start	= 2,
5888f58de7cSeric miao 		.end	= 2,
5898f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5908f58de7cSeric miao 	},
5918f58de7cSeric miao 	[3] = {
5928f58de7cSeric miao 		/* DRCMR for TX */
5938f58de7cSeric miao 		.start	= 3,
5948f58de7cSeric miao 		.end	= 3,
5958f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5968f58de7cSeric miao 	},
5978f58de7cSeric miao };
5988f58de7cSeric miao 
5998f58de7cSeric miao struct platform_device pxa3xx_device_ssp4 = {
6008f58de7cSeric miao 	/* PXA3xx SSP is basically equivalent to PXA27x */
6018f58de7cSeric miao 	.name		= "pxa27x-ssp",
6028f58de7cSeric miao 	.id		= 3,
6038f58de7cSeric miao 	.dev		= {
6048f58de7cSeric miao 		.dma_mask = &pxa3xx_ssp4_dma_mask,
6058f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
6068f58de7cSeric miao 	},
6078f58de7cSeric miao 	.resource	= pxa3xx_resource_ssp4,
6088f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa3xx_resource_ssp4),
6098f58de7cSeric miao };
6108d33b055SBridge Wu 
6118d33b055SBridge Wu static struct resource pxa3xx_resources_mci2[] = {
6128d33b055SBridge Wu 	[0] = {
6138d33b055SBridge Wu 		.start	= 0x42000000,
6148d33b055SBridge Wu 		.end	= 0x42000fff,
6158d33b055SBridge Wu 		.flags	= IORESOURCE_MEM,
6168d33b055SBridge Wu 	},
6178d33b055SBridge Wu 	[1] = {
6188d33b055SBridge Wu 		.start	= IRQ_MMC2,
6198d33b055SBridge Wu 		.end	= IRQ_MMC2,
6208d33b055SBridge Wu 		.flags	= IORESOURCE_IRQ,
6218d33b055SBridge Wu 	},
6228d33b055SBridge Wu 	[2] = {
6238d33b055SBridge Wu 		.start	= 93,
6248d33b055SBridge Wu 		.end	= 93,
6258d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
6268d33b055SBridge Wu 	},
6278d33b055SBridge Wu 	[3] = {
6288d33b055SBridge Wu 		.start	= 94,
6298d33b055SBridge Wu 		.end	= 94,
6308d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
6318d33b055SBridge Wu 	},
6328d33b055SBridge Wu };
6338d33b055SBridge Wu 
6348d33b055SBridge Wu struct platform_device pxa3xx_device_mci2 = {
6358d33b055SBridge Wu 	.name		= "pxa2xx-mci",
6368d33b055SBridge Wu 	.id		= 1,
6378d33b055SBridge Wu 	.dev		= {
6388d33b055SBridge Wu 		.dma_mask = &pxamci_dmamask,
6398d33b055SBridge Wu 		.coherent_dma_mask =	0xffffffff,
6408d33b055SBridge Wu 	},
6418d33b055SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci2),
6428d33b055SBridge Wu 	.resource	= pxa3xx_resources_mci2,
6438d33b055SBridge Wu };
6448d33b055SBridge Wu 
6458d33b055SBridge Wu void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
6468d33b055SBridge Wu {
6478d33b055SBridge Wu 	pxa_register_device(&pxa3xx_device_mci2, info);
6488d33b055SBridge Wu }
6498d33b055SBridge Wu 
6505a1f21b1SBridge Wu static struct resource pxa3xx_resources_mci3[] = {
6515a1f21b1SBridge Wu 	[0] = {
6525a1f21b1SBridge Wu 		.start	= 0x42500000,
6535a1f21b1SBridge Wu 		.end	= 0x42500fff,
6545a1f21b1SBridge Wu 		.flags	= IORESOURCE_MEM,
6555a1f21b1SBridge Wu 	},
6565a1f21b1SBridge Wu 	[1] = {
6575a1f21b1SBridge Wu 		.start	= IRQ_MMC3,
6585a1f21b1SBridge Wu 		.end	= IRQ_MMC3,
6595a1f21b1SBridge Wu 		.flags	= IORESOURCE_IRQ,
6605a1f21b1SBridge Wu 	},
6615a1f21b1SBridge Wu 	[2] = {
6625a1f21b1SBridge Wu 		.start	= 100,
6635a1f21b1SBridge Wu 		.end	= 100,
6645a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
6655a1f21b1SBridge Wu 	},
6665a1f21b1SBridge Wu 	[3] = {
6675a1f21b1SBridge Wu 		.start	= 101,
6685a1f21b1SBridge Wu 		.end	= 101,
6695a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
6705a1f21b1SBridge Wu 	},
6715a1f21b1SBridge Wu };
6725a1f21b1SBridge Wu 
6735a1f21b1SBridge Wu struct platform_device pxa3xx_device_mci3 = {
6745a1f21b1SBridge Wu 	.name		= "pxa2xx-mci",
6755a1f21b1SBridge Wu 	.id		= 2,
6765a1f21b1SBridge Wu 	.dev		= {
6775a1f21b1SBridge Wu 		.dma_mask = &pxamci_dmamask,
6785a1f21b1SBridge Wu 		.coherent_dma_mask = 0xffffffff,
6795a1f21b1SBridge Wu 	},
6805a1f21b1SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci3),
6815a1f21b1SBridge Wu 	.resource	= pxa3xx_resources_mci3,
6825a1f21b1SBridge Wu };
6835a1f21b1SBridge Wu 
6845a1f21b1SBridge Wu void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
6855a1f21b1SBridge Wu {
6865a1f21b1SBridge Wu 	pxa_register_device(&pxa3xx_device_mci3, info);
6875a1f21b1SBridge Wu }
6885a1f21b1SBridge Wu 
6898f58de7cSeric miao #endif /* CONFIG_PXA3xx */
690