18f58de7cSeric miao #include <linux/module.h> 28f58de7cSeric miao #include <linux/kernel.h> 38f58de7cSeric miao #include <linux/init.h> 48f58de7cSeric miao #include <linux/platform_device.h> 58f58de7cSeric miao #include <linux/dma-mapping.h> 68348c259SSebastian Andrzej Siewior #include <linux/spi/pxa2xx_spi.h> 7b459396eSSebastian Andrzej Siewior #include <linux/i2c/pxa-i2c.h> 88f58de7cSeric miao 909a5358dSEric Miao #include <asm/pmu.h> 10a09e64fbSRussell King #include <mach/udc.h> 11*293b2da1SArnd Bergmann #include <linux/platform_data/usb-pxa3xx-ulpi.h> 12*293b2da1SArnd Bergmann #include <linux/platform_data/video-pxafb.h> 13*293b2da1SArnd Bergmann #include <linux/platform_data/mmc-pxamci.h> 14*293b2da1SArnd Bergmann #include <linux/platform_data/irda-pxaficp.h> 154e611091SRob Herring #include <mach/irqs.h> 16*293b2da1SArnd Bergmann #include <linux/platform_data/usb-ohci-pxa27x.h> 17*293b2da1SArnd Bergmann #include <linux/platform_data/keypad-pxa27x.h> 18*293b2da1SArnd Bergmann #include <linux/platform_data/camera-pxa.h> 19a09e64fbSRussell King #include <mach/audio.h> 2075e874c6SEric Miao #include <mach/hardware.h> 21*293b2da1SArnd Bergmann #include <linux/platform_data/mtd-nand-pxa3xx.h> 228f58de7cSeric miao 238f58de7cSeric miao #include "devices.h" 24bc3a5959SPhilipp Zabel #include "generic.h" 258f58de7cSeric miao 268f58de7cSeric miao void __init pxa_register_device(struct platform_device *dev, void *data) 278f58de7cSeric miao { 288f58de7cSeric miao int ret; 298f58de7cSeric miao 308f58de7cSeric miao dev->dev.platform_data = data; 318f58de7cSeric miao 328f58de7cSeric miao ret = platform_device_register(dev); 338f58de7cSeric miao if (ret) 348f58de7cSeric miao dev_err(&dev->dev, "unable to register device: %d\n", ret); 358f58de7cSeric miao } 368f58de7cSeric miao 3709a5358dSEric Miao static struct resource pxa_resource_pmu = { 3809a5358dSEric Miao .start = IRQ_PMU, 3909a5358dSEric Miao .end = IRQ_PMU, 4009a5358dSEric Miao .flags = IORESOURCE_IRQ, 4109a5358dSEric Miao }; 4209a5358dSEric Miao 4309a5358dSEric Miao struct platform_device pxa_device_pmu = { 4409a5358dSEric Miao .name = "arm-pmu", 4509a5358dSEric Miao .id = ARM_PMU_DEVICE_CPU, 4609a5358dSEric Miao .resource = &pxa_resource_pmu, 4709a5358dSEric Miao .num_resources = 1, 4809a5358dSEric Miao }; 4909a5358dSEric Miao 508f58de7cSeric miao static struct resource pxamci_resources[] = { 518f58de7cSeric miao [0] = { 528f58de7cSeric miao .start = 0x41100000, 538f58de7cSeric miao .end = 0x41100fff, 548f58de7cSeric miao .flags = IORESOURCE_MEM, 558f58de7cSeric miao }, 568f58de7cSeric miao [1] = { 578f58de7cSeric miao .start = IRQ_MMC, 588f58de7cSeric miao .end = IRQ_MMC, 598f58de7cSeric miao .flags = IORESOURCE_IRQ, 608f58de7cSeric miao }, 618f58de7cSeric miao [2] = { 628f58de7cSeric miao .start = 21, 638f58de7cSeric miao .end = 21, 648f58de7cSeric miao .flags = IORESOURCE_DMA, 658f58de7cSeric miao }, 668f58de7cSeric miao [3] = { 678f58de7cSeric miao .start = 22, 688f58de7cSeric miao .end = 22, 698f58de7cSeric miao .flags = IORESOURCE_DMA, 708f58de7cSeric miao }, 718f58de7cSeric miao }; 728f58de7cSeric miao 738f58de7cSeric miao static u64 pxamci_dmamask = 0xffffffffUL; 748f58de7cSeric miao 758f58de7cSeric miao struct platform_device pxa_device_mci = { 768f58de7cSeric miao .name = "pxa2xx-mci", 77fafc9d3fSBridge Wu .id = 0, 788f58de7cSeric miao .dev = { 798f58de7cSeric miao .dma_mask = &pxamci_dmamask, 808f58de7cSeric miao .coherent_dma_mask = 0xffffffff, 818f58de7cSeric miao }, 828f58de7cSeric miao .num_resources = ARRAY_SIZE(pxamci_resources), 838f58de7cSeric miao .resource = pxamci_resources, 848f58de7cSeric miao }; 858f58de7cSeric miao 868f58de7cSeric miao void __init pxa_set_mci_info(struct pxamci_platform_data *info) 878f58de7cSeric miao { 888f58de7cSeric miao pxa_register_device(&pxa_device_mci, info); 898f58de7cSeric miao } 908f58de7cSeric miao 918f58de7cSeric miao 921257629bSPhilipp Zabel static struct pxa2xx_udc_mach_info pxa_udc_info = { 931257629bSPhilipp Zabel .gpio_pullup = -1, 941257629bSPhilipp Zabel }; 958f58de7cSeric miao 968f58de7cSeric miao void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info) 978f58de7cSeric miao { 988f58de7cSeric miao memcpy(&pxa_udc_info, info, sizeof *info); 998f58de7cSeric miao } 1008f58de7cSeric miao 1018f58de7cSeric miao static struct resource pxa2xx_udc_resources[] = { 1028f58de7cSeric miao [0] = { 1038f58de7cSeric miao .start = 0x40600000, 1048f58de7cSeric miao .end = 0x4060ffff, 1058f58de7cSeric miao .flags = IORESOURCE_MEM, 1068f58de7cSeric miao }, 1078f58de7cSeric miao [1] = { 1088f58de7cSeric miao .start = IRQ_USB, 1098f58de7cSeric miao .end = IRQ_USB, 1108f58de7cSeric miao .flags = IORESOURCE_IRQ, 1118f58de7cSeric miao }, 1128f58de7cSeric miao }; 1138f58de7cSeric miao 1148f58de7cSeric miao static u64 udc_dma_mask = ~(u32)0; 1158f58de7cSeric miao 1167a857620SPhilipp Zabel struct platform_device pxa25x_device_udc = { 1177a857620SPhilipp Zabel .name = "pxa25x-udc", 1187a857620SPhilipp Zabel .id = -1, 1197a857620SPhilipp Zabel .resource = pxa2xx_udc_resources, 1207a857620SPhilipp Zabel .num_resources = ARRAY_SIZE(pxa2xx_udc_resources), 1217a857620SPhilipp Zabel .dev = { 1227a857620SPhilipp Zabel .platform_data = &pxa_udc_info, 1237a857620SPhilipp Zabel .dma_mask = &udc_dma_mask, 1247a857620SPhilipp Zabel } 1257a857620SPhilipp Zabel }; 1267a857620SPhilipp Zabel 1277a857620SPhilipp Zabel struct platform_device pxa27x_device_udc = { 1287a857620SPhilipp Zabel .name = "pxa27x-udc", 1298f58de7cSeric miao .id = -1, 1308f58de7cSeric miao .resource = pxa2xx_udc_resources, 1318f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa2xx_udc_resources), 1328f58de7cSeric miao .dev = { 1338f58de7cSeric miao .platform_data = &pxa_udc_info, 1348f58de7cSeric miao .dma_mask = &udc_dma_mask, 1358f58de7cSeric miao } 1368f58de7cSeric miao }; 1378f58de7cSeric miao 13869f22be7SIgor Grinberg #ifdef CONFIG_PXA3xx 13969f22be7SIgor Grinberg static struct resource pxa3xx_u2d_resources[] = { 14069f22be7SIgor Grinberg [0] = { 14169f22be7SIgor Grinberg .start = 0x54100000, 14269f22be7SIgor Grinberg .end = 0x54100fff, 14369f22be7SIgor Grinberg .flags = IORESOURCE_MEM, 14469f22be7SIgor Grinberg }, 14569f22be7SIgor Grinberg [1] = { 14669f22be7SIgor Grinberg .start = IRQ_USB2, 14769f22be7SIgor Grinberg .end = IRQ_USB2, 14869f22be7SIgor Grinberg .flags = IORESOURCE_IRQ, 14969f22be7SIgor Grinberg }, 15069f22be7SIgor Grinberg }; 15169f22be7SIgor Grinberg 15269f22be7SIgor Grinberg struct platform_device pxa3xx_device_u2d = { 15369f22be7SIgor Grinberg .name = "pxa3xx-u2d", 15469f22be7SIgor Grinberg .id = -1, 15569f22be7SIgor Grinberg .resource = pxa3xx_u2d_resources, 15669f22be7SIgor Grinberg .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources), 15769f22be7SIgor Grinberg }; 15869f22be7SIgor Grinberg 15969f22be7SIgor Grinberg void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info) 16069f22be7SIgor Grinberg { 16169f22be7SIgor Grinberg pxa_register_device(&pxa3xx_device_u2d, info); 16269f22be7SIgor Grinberg } 16369f22be7SIgor Grinberg #endif /* CONFIG_PXA3xx */ 16469f22be7SIgor Grinberg 1658f58de7cSeric miao static struct resource pxafb_resources[] = { 1668f58de7cSeric miao [0] = { 1678f58de7cSeric miao .start = 0x44000000, 1688f58de7cSeric miao .end = 0x4400ffff, 1698f58de7cSeric miao .flags = IORESOURCE_MEM, 1708f58de7cSeric miao }, 1718f58de7cSeric miao [1] = { 1728f58de7cSeric miao .start = IRQ_LCD, 1738f58de7cSeric miao .end = IRQ_LCD, 1748f58de7cSeric miao .flags = IORESOURCE_IRQ, 1758f58de7cSeric miao }, 1768f58de7cSeric miao }; 1778f58de7cSeric miao 1788f58de7cSeric miao static u64 fb_dma_mask = ~(u64)0; 1798f58de7cSeric miao 1808f58de7cSeric miao struct platform_device pxa_device_fb = { 1818f58de7cSeric miao .name = "pxa2xx-fb", 1828f58de7cSeric miao .id = -1, 1838f58de7cSeric miao .dev = { 1848f58de7cSeric miao .dma_mask = &fb_dma_mask, 1858f58de7cSeric miao .coherent_dma_mask = 0xffffffff, 1868f58de7cSeric miao }, 1878f58de7cSeric miao .num_resources = ARRAY_SIZE(pxafb_resources), 1888f58de7cSeric miao .resource = pxafb_resources, 1898f58de7cSeric miao }; 1908f58de7cSeric miao 1914321e1a1SRussell King - ARM Linux void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info) 1928f58de7cSeric miao { 1934321e1a1SRussell King - ARM Linux pxa_device_fb.dev.parent = parent; 1948f58de7cSeric miao pxa_register_device(&pxa_device_fb, info); 1958f58de7cSeric miao } 1968f58de7cSeric miao 1978f58de7cSeric miao static struct resource pxa_resource_ffuart[] = { 1988f58de7cSeric miao { 19902f65262SEric Miao .start = 0x40100000, 20002f65262SEric Miao .end = 0x40100023, 2018f58de7cSeric miao .flags = IORESOURCE_MEM, 2028f58de7cSeric miao }, { 2038f58de7cSeric miao .start = IRQ_FFUART, 2048f58de7cSeric miao .end = IRQ_FFUART, 2058f58de7cSeric miao .flags = IORESOURCE_IRQ, 2068f58de7cSeric miao } 2078f58de7cSeric miao }; 2088f58de7cSeric miao 2098f58de7cSeric miao struct platform_device pxa_device_ffuart = { 2108f58de7cSeric miao .name = "pxa2xx-uart", 2118f58de7cSeric miao .id = 0, 2128f58de7cSeric miao .resource = pxa_resource_ffuart, 2138f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa_resource_ffuart), 2148f58de7cSeric miao }; 2158f58de7cSeric miao 216cc155c6fSRussell King void __init pxa_set_ffuart_info(void *info) 217cc155c6fSRussell King { 218cc155c6fSRussell King pxa_register_device(&pxa_device_ffuart, info); 219cc155c6fSRussell King } 220cc155c6fSRussell King 2218f58de7cSeric miao static struct resource pxa_resource_btuart[] = { 2228f58de7cSeric miao { 22302f65262SEric Miao .start = 0x40200000, 22402f65262SEric Miao .end = 0x40200023, 2258f58de7cSeric miao .flags = IORESOURCE_MEM, 2268f58de7cSeric miao }, { 2278f58de7cSeric miao .start = IRQ_BTUART, 2288f58de7cSeric miao .end = IRQ_BTUART, 2298f58de7cSeric miao .flags = IORESOURCE_IRQ, 2308f58de7cSeric miao } 2318f58de7cSeric miao }; 2328f58de7cSeric miao 2338f58de7cSeric miao struct platform_device pxa_device_btuart = { 2348f58de7cSeric miao .name = "pxa2xx-uart", 2358f58de7cSeric miao .id = 1, 2368f58de7cSeric miao .resource = pxa_resource_btuart, 2378f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa_resource_btuart), 2388f58de7cSeric miao }; 2398f58de7cSeric miao 240cc155c6fSRussell King void __init pxa_set_btuart_info(void *info) 241cc155c6fSRussell King { 242cc155c6fSRussell King pxa_register_device(&pxa_device_btuart, info); 243cc155c6fSRussell King } 244cc155c6fSRussell King 2458f58de7cSeric miao static struct resource pxa_resource_stuart[] = { 2468f58de7cSeric miao { 24702f65262SEric Miao .start = 0x40700000, 24802f65262SEric Miao .end = 0x40700023, 2498f58de7cSeric miao .flags = IORESOURCE_MEM, 2508f58de7cSeric miao }, { 2518f58de7cSeric miao .start = IRQ_STUART, 2528f58de7cSeric miao .end = IRQ_STUART, 2538f58de7cSeric miao .flags = IORESOURCE_IRQ, 2548f58de7cSeric miao } 2558f58de7cSeric miao }; 2568f58de7cSeric miao 2578f58de7cSeric miao struct platform_device pxa_device_stuart = { 2588f58de7cSeric miao .name = "pxa2xx-uart", 2598f58de7cSeric miao .id = 2, 2608f58de7cSeric miao .resource = pxa_resource_stuart, 2618f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa_resource_stuart), 2628f58de7cSeric miao }; 2638f58de7cSeric miao 264cc155c6fSRussell King void __init pxa_set_stuart_info(void *info) 265cc155c6fSRussell King { 266cc155c6fSRussell King pxa_register_device(&pxa_device_stuart, info); 267cc155c6fSRussell King } 268cc155c6fSRussell King 2698f58de7cSeric miao static struct resource pxa_resource_hwuart[] = { 2708f58de7cSeric miao { 27102f65262SEric Miao .start = 0x41600000, 27202f65262SEric Miao .end = 0x4160002F, 2738f58de7cSeric miao .flags = IORESOURCE_MEM, 2748f58de7cSeric miao }, { 2758f58de7cSeric miao .start = IRQ_HWUART, 2768f58de7cSeric miao .end = IRQ_HWUART, 2778f58de7cSeric miao .flags = IORESOURCE_IRQ, 2788f58de7cSeric miao } 2798f58de7cSeric miao }; 2808f58de7cSeric miao 2818f58de7cSeric miao struct platform_device pxa_device_hwuart = { 2828f58de7cSeric miao .name = "pxa2xx-uart", 2838f58de7cSeric miao .id = 3, 2848f58de7cSeric miao .resource = pxa_resource_hwuart, 2858f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa_resource_hwuart), 2868f58de7cSeric miao }; 2878f58de7cSeric miao 288cc155c6fSRussell King void __init pxa_set_hwuart_info(void *info) 289cc155c6fSRussell King { 290cc155c6fSRussell King if (cpu_is_pxa255()) 291cc155c6fSRussell King pxa_register_device(&pxa_device_hwuart, info); 292cc155c6fSRussell King else 293cc155c6fSRussell King pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware"); 294cc155c6fSRussell King } 295cc155c6fSRussell King 2968f58de7cSeric miao static struct resource pxai2c_resources[] = { 2978f58de7cSeric miao { 2988f58de7cSeric miao .start = 0x40301680, 2998f58de7cSeric miao .end = 0x403016a3, 3008f58de7cSeric miao .flags = IORESOURCE_MEM, 3018f58de7cSeric miao }, { 3028f58de7cSeric miao .start = IRQ_I2C, 3038f58de7cSeric miao .end = IRQ_I2C, 3048f58de7cSeric miao .flags = IORESOURCE_IRQ, 3058f58de7cSeric miao }, 3068f58de7cSeric miao }; 3078f58de7cSeric miao 3088f58de7cSeric miao struct platform_device pxa_device_i2c = { 3098f58de7cSeric miao .name = "pxa2xx-i2c", 3108f58de7cSeric miao .id = 0, 3118f58de7cSeric miao .resource = pxai2c_resources, 3128f58de7cSeric miao .num_resources = ARRAY_SIZE(pxai2c_resources), 3138f58de7cSeric miao }; 3148f58de7cSeric miao 3158f58de7cSeric miao void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) 3168f58de7cSeric miao { 3178f58de7cSeric miao pxa_register_device(&pxa_device_i2c, info); 3188f58de7cSeric miao } 3198f58de7cSeric miao 32099464293SEric Miao #ifdef CONFIG_PXA27x 32199464293SEric Miao static struct resource pxa27x_resources_i2c_power[] = { 32299464293SEric Miao { 32399464293SEric Miao .start = 0x40f00180, 32499464293SEric Miao .end = 0x40f001a3, 32599464293SEric Miao .flags = IORESOURCE_MEM, 32699464293SEric Miao }, { 32799464293SEric Miao .start = IRQ_PWRI2C, 32899464293SEric Miao .end = IRQ_PWRI2C, 32999464293SEric Miao .flags = IORESOURCE_IRQ, 33099464293SEric Miao }, 33199464293SEric Miao }; 33299464293SEric Miao 33399464293SEric Miao struct platform_device pxa27x_device_i2c_power = { 33499464293SEric Miao .name = "pxa2xx-i2c", 33599464293SEric Miao .id = 1, 33699464293SEric Miao .resource = pxa27x_resources_i2c_power, 33799464293SEric Miao .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power), 33899464293SEric Miao }; 33999464293SEric Miao #endif 34099464293SEric Miao 3418f58de7cSeric miao static struct resource pxai2s_resources[] = { 3428f58de7cSeric miao { 3438f58de7cSeric miao .start = 0x40400000, 3448f58de7cSeric miao .end = 0x40400083, 3458f58de7cSeric miao .flags = IORESOURCE_MEM, 3468f58de7cSeric miao }, { 3478f58de7cSeric miao .start = IRQ_I2S, 3488f58de7cSeric miao .end = IRQ_I2S, 3498f58de7cSeric miao .flags = IORESOURCE_IRQ, 3508f58de7cSeric miao }, 3518f58de7cSeric miao }; 3528f58de7cSeric miao 3538f58de7cSeric miao struct platform_device pxa_device_i2s = { 3548f58de7cSeric miao .name = "pxa2xx-i2s", 3558f58de7cSeric miao .id = -1, 3568f58de7cSeric miao .resource = pxai2s_resources, 3578f58de7cSeric miao .num_resources = ARRAY_SIZE(pxai2s_resources), 3588f58de7cSeric miao }; 3598f58de7cSeric miao 360f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp1 = { 361f0fba2adSLiam Girdwood .name = "pxa-ssp-dai", 362f0fba2adSLiam Girdwood .id = 0, 363f0fba2adSLiam Girdwood }; 364f0fba2adSLiam Girdwood 365f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp2= { 366f0fba2adSLiam Girdwood .name = "pxa-ssp-dai", 367f0fba2adSLiam Girdwood .id = 1, 368f0fba2adSLiam Girdwood }; 369f0fba2adSLiam Girdwood 370f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp3 = { 371f0fba2adSLiam Girdwood .name = "pxa-ssp-dai", 372f0fba2adSLiam Girdwood .id = 2, 373f0fba2adSLiam Girdwood }; 374f0fba2adSLiam Girdwood 375f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp4 = { 376f0fba2adSLiam Girdwood .name = "pxa-ssp-dai", 377f0fba2adSLiam Girdwood .id = 3, 378f0fba2adSLiam Girdwood }; 379f0fba2adSLiam Girdwood 380f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_platform = { 381f0fba2adSLiam Girdwood .name = "pxa-pcm-audio", 382f0fba2adSLiam Girdwood .id = -1, 383f0fba2adSLiam Girdwood }; 384f0fba2adSLiam Girdwood 3858f58de7cSeric miao static u64 pxaficp_dmamask = ~(u32)0; 3868f58de7cSeric miao 3878f58de7cSeric miao struct platform_device pxa_device_ficp = { 3888f58de7cSeric miao .name = "pxa2xx-ir", 3898f58de7cSeric miao .id = -1, 3908f58de7cSeric miao .dev = { 3918f58de7cSeric miao .dma_mask = &pxaficp_dmamask, 3928f58de7cSeric miao .coherent_dma_mask = 0xffffffff, 3938f58de7cSeric miao }, 3948f58de7cSeric miao }; 3958f58de7cSeric miao 3968f58de7cSeric miao void __init pxa_set_ficp_info(struct pxaficp_platform_data *info) 3978f58de7cSeric miao { 3988f58de7cSeric miao pxa_register_device(&pxa_device_ficp, info); 3998f58de7cSeric miao } 4008f58de7cSeric miao 40172493146SRobert Jarzmik static struct resource pxa_rtc_resources[] = { 40272493146SRobert Jarzmik [0] = { 40372493146SRobert Jarzmik .start = 0x40900000, 40472493146SRobert Jarzmik .end = 0x40900000 + 0x3b, 40572493146SRobert Jarzmik .flags = IORESOURCE_MEM, 40672493146SRobert Jarzmik }, 40772493146SRobert Jarzmik [1] = { 40872493146SRobert Jarzmik .start = IRQ_RTC1Hz, 40972493146SRobert Jarzmik .end = IRQ_RTC1Hz, 4103888c090SHaojian Zhuang .name = "rtc 1Hz", 41172493146SRobert Jarzmik .flags = IORESOURCE_IRQ, 41272493146SRobert Jarzmik }, 41372493146SRobert Jarzmik [2] = { 41472493146SRobert Jarzmik .start = IRQ_RTCAlrm, 41572493146SRobert Jarzmik .end = IRQ_RTCAlrm, 4163888c090SHaojian Zhuang .name = "rtc alarm", 41772493146SRobert Jarzmik .flags = IORESOURCE_IRQ, 41872493146SRobert Jarzmik }, 41972493146SRobert Jarzmik }; 42072493146SRobert Jarzmik 42172493146SRobert Jarzmik struct platform_device pxa_device_rtc = { 42272493146SRobert Jarzmik .name = "pxa-rtc", 42372493146SRobert Jarzmik .id = -1, 42472493146SRobert Jarzmik .num_resources = ARRAY_SIZE(pxa_rtc_resources), 42572493146SRobert Jarzmik .resource = pxa_rtc_resources, 42672493146SRobert Jarzmik }; 42772493146SRobert Jarzmik 4283888c090SHaojian Zhuang static struct resource sa1100_rtc_resources[] = { 4293888c090SHaojian Zhuang { 4303888c090SHaojian Zhuang .start = IRQ_RTC1Hz, 4313888c090SHaojian Zhuang .end = IRQ_RTC1Hz, 4323888c090SHaojian Zhuang .name = "rtc 1Hz", 4333888c090SHaojian Zhuang .flags = IORESOURCE_IRQ, 4343888c090SHaojian Zhuang }, { 4353888c090SHaojian Zhuang .start = IRQ_RTCAlrm, 4363888c090SHaojian Zhuang .end = IRQ_RTCAlrm, 4373888c090SHaojian Zhuang .name = "rtc alarm", 4383888c090SHaojian Zhuang .flags = IORESOURCE_IRQ, 4393888c090SHaojian Zhuang }, 4403888c090SHaojian Zhuang }; 4413888c090SHaojian Zhuang 4423888c090SHaojian Zhuang struct platform_device sa1100_device_rtc = { 4433888c090SHaojian Zhuang .name = "sa1100-rtc", 4443888c090SHaojian Zhuang .id = -1, 4453888c090SHaojian Zhuang .num_resources = ARRAY_SIZE(sa1100_rtc_resources), 4463888c090SHaojian Zhuang .resource = sa1100_rtc_resources, 4473888c090SHaojian Zhuang }; 4483888c090SHaojian Zhuang 4499f19d638SMark Brown static struct resource pxa_ac97_resources[] = { 4509f19d638SMark Brown [0] = { 4519f19d638SMark Brown .start = 0x40500000, 4529f19d638SMark Brown .end = 0x40500000 + 0xfff, 4539f19d638SMark Brown .flags = IORESOURCE_MEM, 4549f19d638SMark Brown }, 4559f19d638SMark Brown [1] = { 4569f19d638SMark Brown .start = IRQ_AC97, 4579f19d638SMark Brown .end = IRQ_AC97, 4589f19d638SMark Brown .flags = IORESOURCE_IRQ, 4599f19d638SMark Brown }, 4609f19d638SMark Brown }; 4619f19d638SMark Brown 4629f19d638SMark Brown static u64 pxa_ac97_dmamask = 0xffffffffUL; 4639f19d638SMark Brown 4649f19d638SMark Brown struct platform_device pxa_device_ac97 = { 4659f19d638SMark Brown .name = "pxa2xx-ac97", 4669f19d638SMark Brown .id = -1, 4679f19d638SMark Brown .dev = { 4689f19d638SMark Brown .dma_mask = &pxa_ac97_dmamask, 4699f19d638SMark Brown .coherent_dma_mask = 0xffffffff, 4709f19d638SMark Brown }, 4719f19d638SMark Brown .num_resources = ARRAY_SIZE(pxa_ac97_resources), 4729f19d638SMark Brown .resource = pxa_ac97_resources, 4739f19d638SMark Brown }; 4749f19d638SMark Brown 4759f19d638SMark Brown void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops) 4769f19d638SMark Brown { 4779f19d638SMark Brown pxa_register_device(&pxa_device_ac97, ops); 4789f19d638SMark Brown } 4799f19d638SMark Brown 4808f58de7cSeric miao #ifdef CONFIG_PXA25x 4818f58de7cSeric miao 48275540c1aSeric miao static struct resource pxa25x_resource_pwm0[] = { 48375540c1aSeric miao [0] = { 48475540c1aSeric miao .start = 0x40b00000, 48575540c1aSeric miao .end = 0x40b0000f, 48675540c1aSeric miao .flags = IORESOURCE_MEM, 48775540c1aSeric miao }, 48875540c1aSeric miao }; 48975540c1aSeric miao 49075540c1aSeric miao struct platform_device pxa25x_device_pwm0 = { 49175540c1aSeric miao .name = "pxa25x-pwm", 49275540c1aSeric miao .id = 0, 49375540c1aSeric miao .resource = pxa25x_resource_pwm0, 49475540c1aSeric miao .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0), 49575540c1aSeric miao }; 49675540c1aSeric miao 49775540c1aSeric miao static struct resource pxa25x_resource_pwm1[] = { 49875540c1aSeric miao [0] = { 49975540c1aSeric miao .start = 0x40c00000, 50075540c1aSeric miao .end = 0x40c0000f, 50175540c1aSeric miao .flags = IORESOURCE_MEM, 50275540c1aSeric miao }, 50375540c1aSeric miao }; 50475540c1aSeric miao 50575540c1aSeric miao struct platform_device pxa25x_device_pwm1 = { 50675540c1aSeric miao .name = "pxa25x-pwm", 50775540c1aSeric miao .id = 1, 50875540c1aSeric miao .resource = pxa25x_resource_pwm1, 50975540c1aSeric miao .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1), 51075540c1aSeric miao }; 51175540c1aSeric miao 5128f58de7cSeric miao static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32); 5138f58de7cSeric miao 5148f58de7cSeric miao static struct resource pxa25x_resource_ssp[] = { 5158f58de7cSeric miao [0] = { 5168f58de7cSeric miao .start = 0x41000000, 5178f58de7cSeric miao .end = 0x4100001f, 5188f58de7cSeric miao .flags = IORESOURCE_MEM, 5198f58de7cSeric miao }, 5208f58de7cSeric miao [1] = { 5218f58de7cSeric miao .start = IRQ_SSP, 5228f58de7cSeric miao .end = IRQ_SSP, 5238f58de7cSeric miao .flags = IORESOURCE_IRQ, 5248f58de7cSeric miao }, 5258f58de7cSeric miao [2] = { 5268f58de7cSeric miao /* DRCMR for RX */ 5278f58de7cSeric miao .start = 13, 5288f58de7cSeric miao .end = 13, 5298f58de7cSeric miao .flags = IORESOURCE_DMA, 5308f58de7cSeric miao }, 5318f58de7cSeric miao [3] = { 5328f58de7cSeric miao /* DRCMR for TX */ 5338f58de7cSeric miao .start = 14, 5348f58de7cSeric miao .end = 14, 5358f58de7cSeric miao .flags = IORESOURCE_DMA, 5368f58de7cSeric miao }, 5378f58de7cSeric miao }; 5388f58de7cSeric miao 5398f58de7cSeric miao struct platform_device pxa25x_device_ssp = { 5408f58de7cSeric miao .name = "pxa25x-ssp", 5418f58de7cSeric miao .id = 0, 5428f58de7cSeric miao .dev = { 5438f58de7cSeric miao .dma_mask = &pxa25x_ssp_dma_mask, 5448f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 5458f58de7cSeric miao }, 5468f58de7cSeric miao .resource = pxa25x_resource_ssp, 5478f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa25x_resource_ssp), 5488f58de7cSeric miao }; 5498f58de7cSeric miao 5508f58de7cSeric miao static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32); 5518f58de7cSeric miao 5528f58de7cSeric miao static struct resource pxa25x_resource_nssp[] = { 5538f58de7cSeric miao [0] = { 5548f58de7cSeric miao .start = 0x41400000, 5558f58de7cSeric miao .end = 0x4140002f, 5568f58de7cSeric miao .flags = IORESOURCE_MEM, 5578f58de7cSeric miao }, 5588f58de7cSeric miao [1] = { 5598f58de7cSeric miao .start = IRQ_NSSP, 5608f58de7cSeric miao .end = IRQ_NSSP, 5618f58de7cSeric miao .flags = IORESOURCE_IRQ, 5628f58de7cSeric miao }, 5638f58de7cSeric miao [2] = { 5648f58de7cSeric miao /* DRCMR for RX */ 5658f58de7cSeric miao .start = 15, 5668f58de7cSeric miao .end = 15, 5678f58de7cSeric miao .flags = IORESOURCE_DMA, 5688f58de7cSeric miao }, 5698f58de7cSeric miao [3] = { 5708f58de7cSeric miao /* DRCMR for TX */ 5718f58de7cSeric miao .start = 16, 5728f58de7cSeric miao .end = 16, 5738f58de7cSeric miao .flags = IORESOURCE_DMA, 5748f58de7cSeric miao }, 5758f58de7cSeric miao }; 5768f58de7cSeric miao 5778f58de7cSeric miao struct platform_device pxa25x_device_nssp = { 5788f58de7cSeric miao .name = "pxa25x-nssp", 5798f58de7cSeric miao .id = 1, 5808f58de7cSeric miao .dev = { 5818f58de7cSeric miao .dma_mask = &pxa25x_nssp_dma_mask, 5828f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 5838f58de7cSeric miao }, 5848f58de7cSeric miao .resource = pxa25x_resource_nssp, 5858f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa25x_resource_nssp), 5868f58de7cSeric miao }; 5878f58de7cSeric miao 5888f58de7cSeric miao static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32); 5898f58de7cSeric miao 5908f58de7cSeric miao static struct resource pxa25x_resource_assp[] = { 5918f58de7cSeric miao [0] = { 5928f58de7cSeric miao .start = 0x41500000, 5938f58de7cSeric miao .end = 0x4150002f, 5948f58de7cSeric miao .flags = IORESOURCE_MEM, 5958f58de7cSeric miao }, 5968f58de7cSeric miao [1] = { 5978f58de7cSeric miao .start = IRQ_ASSP, 5988f58de7cSeric miao .end = IRQ_ASSP, 5998f58de7cSeric miao .flags = IORESOURCE_IRQ, 6008f58de7cSeric miao }, 6018f58de7cSeric miao [2] = { 6028f58de7cSeric miao /* DRCMR for RX */ 6038f58de7cSeric miao .start = 23, 6048f58de7cSeric miao .end = 23, 6058f58de7cSeric miao .flags = IORESOURCE_DMA, 6068f58de7cSeric miao }, 6078f58de7cSeric miao [3] = { 6088f58de7cSeric miao /* DRCMR for TX */ 6098f58de7cSeric miao .start = 24, 6108f58de7cSeric miao .end = 24, 6118f58de7cSeric miao .flags = IORESOURCE_DMA, 6128f58de7cSeric miao }, 6138f58de7cSeric miao }; 6148f58de7cSeric miao 6158f58de7cSeric miao struct platform_device pxa25x_device_assp = { 6168f58de7cSeric miao /* ASSP is basically equivalent to NSSP */ 6178f58de7cSeric miao .name = "pxa25x-nssp", 6188f58de7cSeric miao .id = 2, 6198f58de7cSeric miao .dev = { 6208f58de7cSeric miao .dma_mask = &pxa25x_assp_dma_mask, 6218f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 6228f58de7cSeric miao }, 6238f58de7cSeric miao .resource = pxa25x_resource_assp, 6248f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa25x_resource_assp), 6258f58de7cSeric miao }; 6268f58de7cSeric miao #endif /* CONFIG_PXA25x */ 6278f58de7cSeric miao 6288f58de7cSeric miao #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 629a4553358SHaojian Zhuang static struct resource pxa27x_resource_camera[] = { 63037320980Seric miao [0] = { 631a4553358SHaojian Zhuang .start = 0x50000000, 632a4553358SHaojian Zhuang .end = 0x50000fff, 63337320980Seric miao .flags = IORESOURCE_MEM, 63437320980Seric miao }, 63537320980Seric miao [1] = { 636a4553358SHaojian Zhuang .start = IRQ_CAMERA, 637a4553358SHaojian Zhuang .end = IRQ_CAMERA, 63837320980Seric miao .flags = IORESOURCE_IRQ, 63937320980Seric miao }, 64037320980Seric miao }; 64137320980Seric miao 642a4553358SHaojian Zhuang static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32); 643a4553358SHaojian Zhuang 644a4553358SHaojian Zhuang static struct platform_device pxa27x_device_camera = { 645a4553358SHaojian Zhuang .name = "pxa27x-camera", 646a4553358SHaojian Zhuang .id = 0, /* This is used to put cameras on this interface */ 647a4553358SHaojian Zhuang .dev = { 648a4553358SHaojian Zhuang .dma_mask = &pxa27x_dma_mask_camera, 649a4553358SHaojian Zhuang .coherent_dma_mask = 0xffffffff, 650a4553358SHaojian Zhuang }, 651a4553358SHaojian Zhuang .num_resources = ARRAY_SIZE(pxa27x_resource_camera), 652a4553358SHaojian Zhuang .resource = pxa27x_resource_camera, 65337320980Seric miao }; 65437320980Seric miao 655a4553358SHaojian Zhuang void __init pxa_set_camera_info(struct pxacamera_platform_data *info) 65637320980Seric miao { 657a4553358SHaojian Zhuang pxa_register_device(&pxa27x_device_camera, info); 65837320980Seric miao } 65937320980Seric miao 660ec68e45bSeric miao static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32); 661ec68e45bSeric miao 662ec68e45bSeric miao static struct resource pxa27x_resource_ohci[] = { 663ec68e45bSeric miao [0] = { 664ec68e45bSeric miao .start = 0x4C000000, 665ec68e45bSeric miao .end = 0x4C00ff6f, 666ec68e45bSeric miao .flags = IORESOURCE_MEM, 667ec68e45bSeric miao }, 668ec68e45bSeric miao [1] = { 669ec68e45bSeric miao .start = IRQ_USBH1, 670ec68e45bSeric miao .end = IRQ_USBH1, 671ec68e45bSeric miao .flags = IORESOURCE_IRQ, 672ec68e45bSeric miao }, 673ec68e45bSeric miao }; 674ec68e45bSeric miao 675ec68e45bSeric miao struct platform_device pxa27x_device_ohci = { 676ec68e45bSeric miao .name = "pxa27x-ohci", 677ec68e45bSeric miao .id = -1, 678ec68e45bSeric miao .dev = { 679ec68e45bSeric miao .dma_mask = &pxa27x_ohci_dma_mask, 680ec68e45bSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 681ec68e45bSeric miao }, 682ec68e45bSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_ohci), 683ec68e45bSeric miao .resource = pxa27x_resource_ohci, 684ec68e45bSeric miao }; 685ec68e45bSeric miao 686ec68e45bSeric miao void __init pxa_set_ohci_info(struct pxaohci_platform_data *info) 687ec68e45bSeric miao { 688ec68e45bSeric miao pxa_register_device(&pxa27x_device_ohci, info); 689ec68e45bSeric miao } 690a4553358SHaojian Zhuang #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ 691a4553358SHaojian Zhuang 692a4553358SHaojian Zhuang #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) 693a4553358SHaojian Zhuang static struct resource pxa27x_resource_keypad[] = { 694a4553358SHaojian Zhuang [0] = { 695a4553358SHaojian Zhuang .start = 0x41500000, 696a4553358SHaojian Zhuang .end = 0x4150004c, 697a4553358SHaojian Zhuang .flags = IORESOURCE_MEM, 698a4553358SHaojian Zhuang }, 699a4553358SHaojian Zhuang [1] = { 700a4553358SHaojian Zhuang .start = IRQ_KEYPAD, 701a4553358SHaojian Zhuang .end = IRQ_KEYPAD, 702a4553358SHaojian Zhuang .flags = IORESOURCE_IRQ, 703a4553358SHaojian Zhuang }, 704a4553358SHaojian Zhuang }; 705a4553358SHaojian Zhuang 706a4553358SHaojian Zhuang struct platform_device pxa27x_device_keypad = { 707a4553358SHaojian Zhuang .name = "pxa27x-keypad", 708a4553358SHaojian Zhuang .id = -1, 709a4553358SHaojian Zhuang .resource = pxa27x_resource_keypad, 710a4553358SHaojian Zhuang .num_resources = ARRAY_SIZE(pxa27x_resource_keypad), 711a4553358SHaojian Zhuang }; 712a4553358SHaojian Zhuang 713a4553358SHaojian Zhuang void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info) 714a4553358SHaojian Zhuang { 715a4553358SHaojian Zhuang pxa_register_device(&pxa27x_device_keypad, info); 716a4553358SHaojian Zhuang } 717ec68e45bSeric miao 7188f58de7cSeric miao static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32); 7198f58de7cSeric miao 7208f58de7cSeric miao static struct resource pxa27x_resource_ssp1[] = { 7218f58de7cSeric miao [0] = { 7228f58de7cSeric miao .start = 0x41000000, 7238f58de7cSeric miao .end = 0x4100003f, 7248f58de7cSeric miao .flags = IORESOURCE_MEM, 7258f58de7cSeric miao }, 7268f58de7cSeric miao [1] = { 7278f58de7cSeric miao .start = IRQ_SSP, 7288f58de7cSeric miao .end = IRQ_SSP, 7298f58de7cSeric miao .flags = IORESOURCE_IRQ, 7308f58de7cSeric miao }, 7318f58de7cSeric miao [2] = { 7328f58de7cSeric miao /* DRCMR for RX */ 7338f58de7cSeric miao .start = 13, 7348f58de7cSeric miao .end = 13, 7358f58de7cSeric miao .flags = IORESOURCE_DMA, 7368f58de7cSeric miao }, 7378f58de7cSeric miao [3] = { 7388f58de7cSeric miao /* DRCMR for TX */ 7398f58de7cSeric miao .start = 14, 7408f58de7cSeric miao .end = 14, 7418f58de7cSeric miao .flags = IORESOURCE_DMA, 7428f58de7cSeric miao }, 7438f58de7cSeric miao }; 7448f58de7cSeric miao 7458f58de7cSeric miao struct platform_device pxa27x_device_ssp1 = { 7468f58de7cSeric miao .name = "pxa27x-ssp", 7478f58de7cSeric miao .id = 0, 7488f58de7cSeric miao .dev = { 7498f58de7cSeric miao .dma_mask = &pxa27x_ssp1_dma_mask, 7508f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 7518f58de7cSeric miao }, 7528f58de7cSeric miao .resource = pxa27x_resource_ssp1, 7538f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1), 7548f58de7cSeric miao }; 7558f58de7cSeric miao 7568f58de7cSeric miao static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32); 7578f58de7cSeric miao 7588f58de7cSeric miao static struct resource pxa27x_resource_ssp2[] = { 7598f58de7cSeric miao [0] = { 7608f58de7cSeric miao .start = 0x41700000, 7618f58de7cSeric miao .end = 0x4170003f, 7628f58de7cSeric miao .flags = IORESOURCE_MEM, 7638f58de7cSeric miao }, 7648f58de7cSeric miao [1] = { 7658f58de7cSeric miao .start = IRQ_SSP2, 7668f58de7cSeric miao .end = IRQ_SSP2, 7678f58de7cSeric miao .flags = IORESOURCE_IRQ, 7688f58de7cSeric miao }, 7698f58de7cSeric miao [2] = { 7708f58de7cSeric miao /* DRCMR for RX */ 7718f58de7cSeric miao .start = 15, 7728f58de7cSeric miao .end = 15, 7738f58de7cSeric miao .flags = IORESOURCE_DMA, 7748f58de7cSeric miao }, 7758f58de7cSeric miao [3] = { 7768f58de7cSeric miao /* DRCMR for TX */ 7778f58de7cSeric miao .start = 16, 7788f58de7cSeric miao .end = 16, 7798f58de7cSeric miao .flags = IORESOURCE_DMA, 7808f58de7cSeric miao }, 7818f58de7cSeric miao }; 7828f58de7cSeric miao 7838f58de7cSeric miao struct platform_device pxa27x_device_ssp2 = { 7848f58de7cSeric miao .name = "pxa27x-ssp", 7858f58de7cSeric miao .id = 1, 7868f58de7cSeric miao .dev = { 7878f58de7cSeric miao .dma_mask = &pxa27x_ssp2_dma_mask, 7888f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 7898f58de7cSeric miao }, 7908f58de7cSeric miao .resource = pxa27x_resource_ssp2, 7918f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2), 7928f58de7cSeric miao }; 7938f58de7cSeric miao 7948f58de7cSeric miao static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32); 7958f58de7cSeric miao 7968f58de7cSeric miao static struct resource pxa27x_resource_ssp3[] = { 7978f58de7cSeric miao [0] = { 7988f58de7cSeric miao .start = 0x41900000, 7998f58de7cSeric miao .end = 0x4190003f, 8008f58de7cSeric miao .flags = IORESOURCE_MEM, 8018f58de7cSeric miao }, 8028f58de7cSeric miao [1] = { 8038f58de7cSeric miao .start = IRQ_SSP3, 8048f58de7cSeric miao .end = IRQ_SSP3, 8058f58de7cSeric miao .flags = IORESOURCE_IRQ, 8068f58de7cSeric miao }, 8078f58de7cSeric miao [2] = { 8088f58de7cSeric miao /* DRCMR for RX */ 8098f58de7cSeric miao .start = 66, 8108f58de7cSeric miao .end = 66, 8118f58de7cSeric miao .flags = IORESOURCE_DMA, 8128f58de7cSeric miao }, 8138f58de7cSeric miao [3] = { 8148f58de7cSeric miao /* DRCMR for TX */ 8158f58de7cSeric miao .start = 67, 8168f58de7cSeric miao .end = 67, 8178f58de7cSeric miao .flags = IORESOURCE_DMA, 8188f58de7cSeric miao }, 8198f58de7cSeric miao }; 8208f58de7cSeric miao 8218f58de7cSeric miao struct platform_device pxa27x_device_ssp3 = { 8228f58de7cSeric miao .name = "pxa27x-ssp", 8238f58de7cSeric miao .id = 2, 8248f58de7cSeric miao .dev = { 8258f58de7cSeric miao .dma_mask = &pxa27x_ssp3_dma_mask, 8268f58de7cSeric miao .coherent_dma_mask = DMA_BIT_MASK(32), 8278f58de7cSeric miao }, 8288f58de7cSeric miao .resource = pxa27x_resource_ssp3, 8298f58de7cSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3), 8308f58de7cSeric miao }; 8313f3acefbSGuennadi Liakhovetski 83275540c1aSeric miao static struct resource pxa27x_resource_pwm0[] = { 83375540c1aSeric miao [0] = { 83475540c1aSeric miao .start = 0x40b00000, 83575540c1aSeric miao .end = 0x40b0001f, 83675540c1aSeric miao .flags = IORESOURCE_MEM, 83775540c1aSeric miao }, 83875540c1aSeric miao }; 83975540c1aSeric miao 84075540c1aSeric miao struct platform_device pxa27x_device_pwm0 = { 84175540c1aSeric miao .name = "pxa27x-pwm", 84275540c1aSeric miao .id = 0, 84375540c1aSeric miao .resource = pxa27x_resource_pwm0, 84475540c1aSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0), 84575540c1aSeric miao }; 84675540c1aSeric miao 84775540c1aSeric miao static struct resource pxa27x_resource_pwm1[] = { 84875540c1aSeric miao [0] = { 84975540c1aSeric miao .start = 0x40c00000, 85075540c1aSeric miao .end = 0x40c0001f, 85175540c1aSeric miao .flags = IORESOURCE_MEM, 85275540c1aSeric miao }, 85375540c1aSeric miao }; 85475540c1aSeric miao 85575540c1aSeric miao struct platform_device pxa27x_device_pwm1 = { 85675540c1aSeric miao .name = "pxa27x-pwm", 85775540c1aSeric miao .id = 1, 85875540c1aSeric miao .resource = pxa27x_resource_pwm1, 85975540c1aSeric miao .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1), 86075540c1aSeric miao }; 861a4553358SHaojian Zhuang #endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/ 8628f58de7cSeric miao 8638f58de7cSeric miao #ifdef CONFIG_PXA3xx 8648d33b055SBridge Wu static struct resource pxa3xx_resources_mci2[] = { 8658d33b055SBridge Wu [0] = { 8668d33b055SBridge Wu .start = 0x42000000, 8678d33b055SBridge Wu .end = 0x42000fff, 8688d33b055SBridge Wu .flags = IORESOURCE_MEM, 8698d33b055SBridge Wu }, 8708d33b055SBridge Wu [1] = { 8718d33b055SBridge Wu .start = IRQ_MMC2, 8728d33b055SBridge Wu .end = IRQ_MMC2, 8738d33b055SBridge Wu .flags = IORESOURCE_IRQ, 8748d33b055SBridge Wu }, 8758d33b055SBridge Wu [2] = { 8768d33b055SBridge Wu .start = 93, 8778d33b055SBridge Wu .end = 93, 8788d33b055SBridge Wu .flags = IORESOURCE_DMA, 8798d33b055SBridge Wu }, 8808d33b055SBridge Wu [3] = { 8818d33b055SBridge Wu .start = 94, 8828d33b055SBridge Wu .end = 94, 8838d33b055SBridge Wu .flags = IORESOURCE_DMA, 8848d33b055SBridge Wu }, 8858d33b055SBridge Wu }; 8868d33b055SBridge Wu 8878d33b055SBridge Wu struct platform_device pxa3xx_device_mci2 = { 8888d33b055SBridge Wu .name = "pxa2xx-mci", 8898d33b055SBridge Wu .id = 1, 8908d33b055SBridge Wu .dev = { 8918d33b055SBridge Wu .dma_mask = &pxamci_dmamask, 8928d33b055SBridge Wu .coherent_dma_mask = 0xffffffff, 8938d33b055SBridge Wu }, 8948d33b055SBridge Wu .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2), 8958d33b055SBridge Wu .resource = pxa3xx_resources_mci2, 8968d33b055SBridge Wu }; 8978d33b055SBridge Wu 8988d33b055SBridge Wu void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info) 8998d33b055SBridge Wu { 9008d33b055SBridge Wu pxa_register_device(&pxa3xx_device_mci2, info); 9018d33b055SBridge Wu } 9028d33b055SBridge Wu 9035a1f21b1SBridge Wu static struct resource pxa3xx_resources_mci3[] = { 9045a1f21b1SBridge Wu [0] = { 9055a1f21b1SBridge Wu .start = 0x42500000, 9065a1f21b1SBridge Wu .end = 0x42500fff, 9075a1f21b1SBridge Wu .flags = IORESOURCE_MEM, 9085a1f21b1SBridge Wu }, 9095a1f21b1SBridge Wu [1] = { 9105a1f21b1SBridge Wu .start = IRQ_MMC3, 9115a1f21b1SBridge Wu .end = IRQ_MMC3, 9125a1f21b1SBridge Wu .flags = IORESOURCE_IRQ, 9135a1f21b1SBridge Wu }, 9145a1f21b1SBridge Wu [2] = { 9155a1f21b1SBridge Wu .start = 100, 9165a1f21b1SBridge Wu .end = 100, 9175a1f21b1SBridge Wu .flags = IORESOURCE_DMA, 9185a1f21b1SBridge Wu }, 9195a1f21b1SBridge Wu [3] = { 9205a1f21b1SBridge Wu .start = 101, 9215a1f21b1SBridge Wu .end = 101, 9225a1f21b1SBridge Wu .flags = IORESOURCE_DMA, 9235a1f21b1SBridge Wu }, 9245a1f21b1SBridge Wu }; 9255a1f21b1SBridge Wu 9265a1f21b1SBridge Wu struct platform_device pxa3xx_device_mci3 = { 9275a1f21b1SBridge Wu .name = "pxa2xx-mci", 9285a1f21b1SBridge Wu .id = 2, 9295a1f21b1SBridge Wu .dev = { 9305a1f21b1SBridge Wu .dma_mask = &pxamci_dmamask, 9315a1f21b1SBridge Wu .coherent_dma_mask = 0xffffffff, 9325a1f21b1SBridge Wu }, 9335a1f21b1SBridge Wu .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3), 9345a1f21b1SBridge Wu .resource = pxa3xx_resources_mci3, 9355a1f21b1SBridge Wu }; 9365a1f21b1SBridge Wu 9375a1f21b1SBridge Wu void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info) 9385a1f21b1SBridge Wu { 9395a1f21b1SBridge Wu pxa_register_device(&pxa3xx_device_mci3, info); 9405a1f21b1SBridge Wu } 9415a1f21b1SBridge Wu 942a4553358SHaojian Zhuang static struct resource pxa3xx_resources_gcu[] = { 943a4553358SHaojian Zhuang { 944a4553358SHaojian Zhuang .start = 0x54000000, 945a4553358SHaojian Zhuang .end = 0x54000fff, 946a4553358SHaojian Zhuang .flags = IORESOURCE_MEM, 947a4553358SHaojian Zhuang }, 948a4553358SHaojian Zhuang { 949a4553358SHaojian Zhuang .start = IRQ_GCU, 950a4553358SHaojian Zhuang .end = IRQ_GCU, 951a4553358SHaojian Zhuang .flags = IORESOURCE_IRQ, 952a4553358SHaojian Zhuang }, 953a4553358SHaojian Zhuang }; 954a4553358SHaojian Zhuang 955a4553358SHaojian Zhuang static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32); 956a4553358SHaojian Zhuang 957a4553358SHaojian Zhuang struct platform_device pxa3xx_device_gcu = { 958a4553358SHaojian Zhuang .name = "pxa3xx-gcu", 959a4553358SHaojian Zhuang .id = -1, 960a4553358SHaojian Zhuang .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu), 961a4553358SHaojian Zhuang .resource = pxa3xx_resources_gcu, 962a4553358SHaojian Zhuang .dev = { 963a4553358SHaojian Zhuang .dma_mask = &pxa3xx_gcu_dmamask, 964a4553358SHaojian Zhuang .coherent_dma_mask = 0xffffffff, 965a4553358SHaojian Zhuang }, 966a4553358SHaojian Zhuang }; 967a4553358SHaojian Zhuang 968a4553358SHaojian Zhuang #endif /* CONFIG_PXA3xx */ 969a4553358SHaojian Zhuang 970a4553358SHaojian Zhuang #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) 971a4553358SHaojian Zhuang static struct resource pxa3xx_resources_i2c_power[] = { 972a4553358SHaojian Zhuang { 973a4553358SHaojian Zhuang .start = 0x40f500c0, 974a4553358SHaojian Zhuang .end = 0x40f500d3, 975a4553358SHaojian Zhuang .flags = IORESOURCE_MEM, 976a4553358SHaojian Zhuang }, { 977a4553358SHaojian Zhuang .start = IRQ_PWRI2C, 978a4553358SHaojian Zhuang .end = IRQ_PWRI2C, 979a4553358SHaojian Zhuang .flags = IORESOURCE_IRQ, 980a4553358SHaojian Zhuang }, 981a4553358SHaojian Zhuang }; 982a4553358SHaojian Zhuang 983a4553358SHaojian Zhuang struct platform_device pxa3xx_device_i2c_power = { 984a4553358SHaojian Zhuang .name = "pxa3xx-pwri2c", 985a4553358SHaojian Zhuang .id = 1, 986a4553358SHaojian Zhuang .resource = pxa3xx_resources_i2c_power, 987a4553358SHaojian Zhuang .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power), 988a4553358SHaojian Zhuang }; 989a4553358SHaojian Zhuang 9909ae819a8SEric Miao static struct resource pxa3xx_resources_nand[] = { 9919ae819a8SEric Miao [0] = { 9929ae819a8SEric Miao .start = 0x43100000, 9939ae819a8SEric Miao .end = 0x43100053, 9949ae819a8SEric Miao .flags = IORESOURCE_MEM, 9959ae819a8SEric Miao }, 9969ae819a8SEric Miao [1] = { 9979ae819a8SEric Miao .start = IRQ_NAND, 9989ae819a8SEric Miao .end = IRQ_NAND, 9999ae819a8SEric Miao .flags = IORESOURCE_IRQ, 10009ae819a8SEric Miao }, 10019ae819a8SEric Miao [2] = { 10029ae819a8SEric Miao /* DRCMR for Data DMA */ 10039ae819a8SEric Miao .start = 97, 10049ae819a8SEric Miao .end = 97, 10059ae819a8SEric Miao .flags = IORESOURCE_DMA, 10069ae819a8SEric Miao }, 10079ae819a8SEric Miao [3] = { 10089ae819a8SEric Miao /* DRCMR for Command DMA */ 10099ae819a8SEric Miao .start = 99, 10109ae819a8SEric Miao .end = 99, 10119ae819a8SEric Miao .flags = IORESOURCE_DMA, 10129ae819a8SEric Miao }, 10139ae819a8SEric Miao }; 10149ae819a8SEric Miao 10159ae819a8SEric Miao static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32); 10169ae819a8SEric Miao 10179ae819a8SEric Miao struct platform_device pxa3xx_device_nand = { 10189ae819a8SEric Miao .name = "pxa3xx-nand", 10199ae819a8SEric Miao .id = -1, 10209ae819a8SEric Miao .dev = { 10219ae819a8SEric Miao .dma_mask = &pxa3xx_nand_dma_mask, 10229ae819a8SEric Miao .coherent_dma_mask = DMA_BIT_MASK(32), 10239ae819a8SEric Miao }, 10249ae819a8SEric Miao .num_resources = ARRAY_SIZE(pxa3xx_resources_nand), 10259ae819a8SEric Miao .resource = pxa3xx_resources_nand, 10269ae819a8SEric Miao }; 10279ae819a8SEric Miao 10289ae819a8SEric Miao void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info) 10299ae819a8SEric Miao { 10309ae819a8SEric Miao pxa_register_device(&pxa3xx_device_nand, info); 10319ae819a8SEric Miao } 10321ff2c33eSDaniel Mack 1033a4553358SHaojian Zhuang static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32); 1034a4553358SHaojian Zhuang 1035a4553358SHaojian Zhuang static struct resource pxa3xx_resource_ssp4[] = { 1036a4553358SHaojian Zhuang [0] = { 1037a4553358SHaojian Zhuang .start = 0x41a00000, 1038a4553358SHaojian Zhuang .end = 0x41a0003f, 10391ff2c33eSDaniel Mack .flags = IORESOURCE_MEM, 10401ff2c33eSDaniel Mack }, 1041a4553358SHaojian Zhuang [1] = { 1042a4553358SHaojian Zhuang .start = IRQ_SSP4, 1043a4553358SHaojian Zhuang .end = IRQ_SSP4, 10441ff2c33eSDaniel Mack .flags = IORESOURCE_IRQ, 10451ff2c33eSDaniel Mack }, 1046a4553358SHaojian Zhuang [2] = { 1047a4553358SHaojian Zhuang /* DRCMR for RX */ 1048a4553358SHaojian Zhuang .start = 2, 1049a4553358SHaojian Zhuang .end = 2, 1050a4553358SHaojian Zhuang .flags = IORESOURCE_DMA, 1051a4553358SHaojian Zhuang }, 1052a4553358SHaojian Zhuang [3] = { 1053a4553358SHaojian Zhuang /* DRCMR for TX */ 1054a4553358SHaojian Zhuang .start = 3, 1055a4553358SHaojian Zhuang .end = 3, 1056a4553358SHaojian Zhuang .flags = IORESOURCE_DMA, 10571ff2c33eSDaniel Mack }, 10581ff2c33eSDaniel Mack }; 10591ff2c33eSDaniel Mack 1060a4553358SHaojian Zhuang struct platform_device pxa3xx_device_ssp4 = { 1061a4553358SHaojian Zhuang /* PXA3xx SSP is basically equivalent to PXA27x */ 1062a4553358SHaojian Zhuang .name = "pxa27x-ssp", 1063a4553358SHaojian Zhuang .id = 3, 1064a4553358SHaojian Zhuang .dev = { 1065a4553358SHaojian Zhuang .dma_mask = &pxa3xx_ssp4_dma_mask, 1066a4553358SHaojian Zhuang .coherent_dma_mask = DMA_BIT_MASK(32), 1067a4553358SHaojian Zhuang }, 1068a4553358SHaojian Zhuang .resource = pxa3xx_resource_ssp4, 1069a4553358SHaojian Zhuang .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4), 1070a4553358SHaojian Zhuang }; 1071a4553358SHaojian Zhuang #endif /* CONFIG_PXA3xx || CONFIG_PXA95x */ 1072e172274cSGuennadi Liakhovetski 1073157d2644SHaojian Zhuang struct resource pxa_resource_gpio[] = { 1074157d2644SHaojian Zhuang { 1075157d2644SHaojian Zhuang .start = 0x40e00000, 1076157d2644SHaojian Zhuang .end = 0x40e0ffff, 1077157d2644SHaojian Zhuang .flags = IORESOURCE_MEM, 1078157d2644SHaojian Zhuang }, { 1079157d2644SHaojian Zhuang .start = IRQ_GPIO0, 1080157d2644SHaojian Zhuang .end = IRQ_GPIO0, 1081157d2644SHaojian Zhuang .name = "gpio0", 1082157d2644SHaojian Zhuang .flags = IORESOURCE_IRQ, 1083157d2644SHaojian Zhuang }, { 1084157d2644SHaojian Zhuang .start = IRQ_GPIO1, 1085157d2644SHaojian Zhuang .end = IRQ_GPIO1, 1086157d2644SHaojian Zhuang .name = "gpio1", 1087157d2644SHaojian Zhuang .flags = IORESOURCE_IRQ, 1088157d2644SHaojian Zhuang }, { 1089157d2644SHaojian Zhuang .start = IRQ_GPIO_2_x, 1090157d2644SHaojian Zhuang .end = IRQ_GPIO_2_x, 1091157d2644SHaojian Zhuang .name = "gpio_mux", 1092157d2644SHaojian Zhuang .flags = IORESOURCE_IRQ, 1093157d2644SHaojian Zhuang }, 1094157d2644SHaojian Zhuang }; 1095157d2644SHaojian Zhuang 1096157d2644SHaojian Zhuang struct platform_device pxa_device_gpio = { 1097157d2644SHaojian Zhuang .name = "pxa-gpio", 1098157d2644SHaojian Zhuang .id = -1, 1099157d2644SHaojian Zhuang .num_resources = ARRAY_SIZE(pxa_resource_gpio), 1100157d2644SHaojian Zhuang .resource = pxa_resource_gpio, 1101157d2644SHaojian Zhuang }; 1102157d2644SHaojian Zhuang 1103e172274cSGuennadi Liakhovetski /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1. 1104e172274cSGuennadi Liakhovetski * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */ 1105e172274cSGuennadi Liakhovetski void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info) 1106e172274cSGuennadi Liakhovetski { 1107e172274cSGuennadi Liakhovetski struct platform_device *pd; 1108e172274cSGuennadi Liakhovetski 1109e172274cSGuennadi Liakhovetski pd = platform_device_alloc("pxa2xx-spi", id); 1110e172274cSGuennadi Liakhovetski if (pd == NULL) { 1111e172274cSGuennadi Liakhovetski printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n", 1112e172274cSGuennadi Liakhovetski id); 1113e172274cSGuennadi Liakhovetski return; 1114e172274cSGuennadi Liakhovetski } 1115e172274cSGuennadi Liakhovetski 1116e172274cSGuennadi Liakhovetski pd->dev.platform_data = info; 1117e172274cSGuennadi Liakhovetski platform_device_add(pd); 1118e172274cSGuennadi Liakhovetski } 1119