xref: /linux/arch/arm/mach-pxa/devices.c (revision 1da10c17afd1109ae22d529c3b16d9f6de3fdbec)
1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
28f58de7cSeric miao #include <linux/module.h>
38f58de7cSeric miao #include <linux/kernel.h>
48f58de7cSeric miao #include <linux/init.h>
58f58de7cSeric miao #include <linux/platform_device.h>
68f58de7cSeric miao #include <linux/dma-mapping.h>
7*1da10c17SRobert Jarzmik #include <linux/dmaengine.h>
88348c259SSebastian Andrzej Siewior #include <linux/spi/pxa2xx_spi.h>
9f15fc9b1SWolfram Sang #include <linux/platform_data/i2c-pxa.h>
108f58de7cSeric miao 
114c25c5d2SArnd Bergmann #include "udc.h"
12293b2da1SArnd Bergmann #include <linux/platform_data/usb-pxa3xx-ulpi.h>
13293b2da1SArnd Bergmann #include <linux/platform_data/video-pxafb.h>
14293b2da1SArnd Bergmann #include <linux/platform_data/mmc-pxamci.h>
15293b2da1SArnd Bergmann #include <linux/platform_data/irda-pxaficp.h>
164e611091SRob Herring #include <mach/irqs.h>
17293b2da1SArnd Bergmann #include <linux/platform_data/usb-ohci-pxa27x.h>
18293b2da1SArnd Bergmann #include <linux/platform_data/keypad-pxa27x.h>
19a71daaa1SMauro Carvalho Chehab #include <linux/platform_data/media/camera-pxa.h>
20a09e64fbSRussell King #include <mach/audio.h>
2175e874c6SEric Miao #include <mach/hardware.h>
224be0856fSRobert Jarzmik #include <linux/platform_data/mmp_dma.h>
23293b2da1SArnd Bergmann #include <linux/platform_data/mtd-nand-pxa3xx.h>
248f58de7cSeric miao 
258f58de7cSeric miao #include "devices.h"
26bc3a5959SPhilipp Zabel #include "generic.h"
278f58de7cSeric miao 
288f58de7cSeric miao void __init pxa_register_device(struct platform_device *dev, void *data)
298f58de7cSeric miao {
308f58de7cSeric miao 	int ret;
318f58de7cSeric miao 
328f58de7cSeric miao 	dev->dev.platform_data = data;
338f58de7cSeric miao 
348f58de7cSeric miao 	ret = platform_device_register(dev);
358f58de7cSeric miao 	if (ret)
368f58de7cSeric miao 		dev_err(&dev->dev, "unable to register device: %d\n", ret);
378f58de7cSeric miao }
388f58de7cSeric miao 
3909a5358dSEric Miao static struct resource pxa_resource_pmu = {
4009a5358dSEric Miao 	.start	= IRQ_PMU,
4109a5358dSEric Miao 	.end	= IRQ_PMU,
4209a5358dSEric Miao 	.flags	= IORESOURCE_IRQ,
4309a5358dSEric Miao };
4409a5358dSEric Miao 
4509a5358dSEric Miao struct platform_device pxa_device_pmu = {
46f9eff219SMark Rutland 	.name		= "xscale-pmu",
47df3d17e0SSudeep KarkadaNagesha 	.id		= -1,
4809a5358dSEric Miao 	.resource	= &pxa_resource_pmu,
4909a5358dSEric Miao 	.num_resources	= 1,
5009a5358dSEric Miao };
5109a5358dSEric Miao 
528f58de7cSeric miao static struct resource pxamci_resources[] = {
538f58de7cSeric miao 	[0] = {
548f58de7cSeric miao 		.start	= 0x41100000,
558f58de7cSeric miao 		.end	= 0x41100fff,
568f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
578f58de7cSeric miao 	},
588f58de7cSeric miao 	[1] = {
598f58de7cSeric miao 		.start	= IRQ_MMC,
608f58de7cSeric miao 		.end	= IRQ_MMC,
618f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
628f58de7cSeric miao 	},
638f58de7cSeric miao 	[2] = {
648f58de7cSeric miao 		.start	= 21,
658f58de7cSeric miao 		.end	= 21,
668f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
678f58de7cSeric miao 	},
688f58de7cSeric miao 	[3] = {
698f58de7cSeric miao 		.start	= 22,
708f58de7cSeric miao 		.end	= 22,
718f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
728f58de7cSeric miao 	},
738f58de7cSeric miao };
748f58de7cSeric miao 
758f58de7cSeric miao static u64 pxamci_dmamask = 0xffffffffUL;
768f58de7cSeric miao 
778f58de7cSeric miao struct platform_device pxa_device_mci = {
788f58de7cSeric miao 	.name		= "pxa2xx-mci",
79fafc9d3fSBridge Wu 	.id		= 0,
808f58de7cSeric miao 	.dev		= {
818f58de7cSeric miao 		.dma_mask = &pxamci_dmamask,
828f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
838f58de7cSeric miao 	},
848f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxamci_resources),
858f58de7cSeric miao 	.resource	= pxamci_resources,
868f58de7cSeric miao };
878f58de7cSeric miao 
888f58de7cSeric miao void __init pxa_set_mci_info(struct pxamci_platform_data *info)
898f58de7cSeric miao {
908f58de7cSeric miao 	pxa_register_device(&pxa_device_mci, info);
918f58de7cSeric miao }
928f58de7cSeric miao 
938f58de7cSeric miao 
941257629bSPhilipp Zabel static struct pxa2xx_udc_mach_info pxa_udc_info = {
951257629bSPhilipp Zabel 	.gpio_pullup = -1,
961257629bSPhilipp Zabel };
978f58de7cSeric miao 
988f58de7cSeric miao void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
998f58de7cSeric miao {
1008f58de7cSeric miao 	memcpy(&pxa_udc_info, info, sizeof *info);
1018f58de7cSeric miao }
1028f58de7cSeric miao 
1038f58de7cSeric miao static struct resource pxa2xx_udc_resources[] = {
1048f58de7cSeric miao 	[0] = {
1058f58de7cSeric miao 		.start	= 0x40600000,
1068f58de7cSeric miao 		.end	= 0x4060ffff,
1078f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1088f58de7cSeric miao 	},
1098f58de7cSeric miao 	[1] = {
1108f58de7cSeric miao 		.start	= IRQ_USB,
1118f58de7cSeric miao 		.end	= IRQ_USB,
1128f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1138f58de7cSeric miao 	},
1148f58de7cSeric miao };
1158f58de7cSeric miao 
1168f58de7cSeric miao static u64 udc_dma_mask = ~(u32)0;
1178f58de7cSeric miao 
1187a857620SPhilipp Zabel struct platform_device pxa25x_device_udc = {
1197a857620SPhilipp Zabel 	.name		= "pxa25x-udc",
1207a857620SPhilipp Zabel 	.id		= -1,
1217a857620SPhilipp Zabel 	.resource	= pxa2xx_udc_resources,
1227a857620SPhilipp Zabel 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
1237a857620SPhilipp Zabel 	.dev		=  {
1247a857620SPhilipp Zabel 		.platform_data	= &pxa_udc_info,
1257a857620SPhilipp Zabel 		.dma_mask	= &udc_dma_mask,
1267a857620SPhilipp Zabel 	}
1277a857620SPhilipp Zabel };
1287a857620SPhilipp Zabel 
1297a857620SPhilipp Zabel struct platform_device pxa27x_device_udc = {
1307a857620SPhilipp Zabel 	.name		= "pxa27x-udc",
1318f58de7cSeric miao 	.id		= -1,
1328f58de7cSeric miao 	.resource	= pxa2xx_udc_resources,
1338f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
1348f58de7cSeric miao 	.dev		=  {
1358f58de7cSeric miao 		.platform_data	= &pxa_udc_info,
1368f58de7cSeric miao 		.dma_mask	= &udc_dma_mask,
1378f58de7cSeric miao 	}
1388f58de7cSeric miao };
1398f58de7cSeric miao 
14069f22be7SIgor Grinberg #ifdef CONFIG_PXA3xx
14169f22be7SIgor Grinberg static struct resource pxa3xx_u2d_resources[] = {
14269f22be7SIgor Grinberg 	[0] = {
14369f22be7SIgor Grinberg 		.start	= 0x54100000,
14469f22be7SIgor Grinberg 		.end	= 0x54100fff,
14569f22be7SIgor Grinberg 		.flags	= IORESOURCE_MEM,
14669f22be7SIgor Grinberg 	},
14769f22be7SIgor Grinberg 	[1] = {
14869f22be7SIgor Grinberg 		.start	= IRQ_USB2,
14969f22be7SIgor Grinberg 		.end	= IRQ_USB2,
15069f22be7SIgor Grinberg 		.flags	= IORESOURCE_IRQ,
15169f22be7SIgor Grinberg 	},
15269f22be7SIgor Grinberg };
15369f22be7SIgor Grinberg 
15469f22be7SIgor Grinberg struct platform_device pxa3xx_device_u2d = {
15569f22be7SIgor Grinberg 	.name		= "pxa3xx-u2d",
15669f22be7SIgor Grinberg 	.id		= -1,
15769f22be7SIgor Grinberg 	.resource	= pxa3xx_u2d_resources,
15869f22be7SIgor Grinberg 	.num_resources	= ARRAY_SIZE(pxa3xx_u2d_resources),
15969f22be7SIgor Grinberg };
16069f22be7SIgor Grinberg 
16169f22be7SIgor Grinberg void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
16269f22be7SIgor Grinberg {
16369f22be7SIgor Grinberg 	pxa_register_device(&pxa3xx_device_u2d, info);
16469f22be7SIgor Grinberg }
16569f22be7SIgor Grinberg #endif /* CONFIG_PXA3xx */
16669f22be7SIgor Grinberg 
1678f58de7cSeric miao static struct resource pxafb_resources[] = {
1688f58de7cSeric miao 	[0] = {
1698f58de7cSeric miao 		.start	= 0x44000000,
1708f58de7cSeric miao 		.end	= 0x4400ffff,
1718f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
1728f58de7cSeric miao 	},
1738f58de7cSeric miao 	[1] = {
1748f58de7cSeric miao 		.start	= IRQ_LCD,
1758f58de7cSeric miao 		.end	= IRQ_LCD,
1768f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
1778f58de7cSeric miao 	},
1788f58de7cSeric miao };
1798f58de7cSeric miao 
1808f58de7cSeric miao static u64 fb_dma_mask = ~(u64)0;
1818f58de7cSeric miao 
1828f58de7cSeric miao struct platform_device pxa_device_fb = {
1838f58de7cSeric miao 	.name		= "pxa2xx-fb",
1848f58de7cSeric miao 	.id		= -1,
1858f58de7cSeric miao 	.dev		= {
1868f58de7cSeric miao 		.dma_mask	= &fb_dma_mask,
1878f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
1888f58de7cSeric miao 	},
1898f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxafb_resources),
1908f58de7cSeric miao 	.resource	= pxafb_resources,
1918f58de7cSeric miao };
1928f58de7cSeric miao 
1934321e1a1SRussell King - ARM Linux void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
1948f58de7cSeric miao {
1954321e1a1SRussell King - ARM Linux 	pxa_device_fb.dev.parent = parent;
1968f58de7cSeric miao 	pxa_register_device(&pxa_device_fb, info);
1978f58de7cSeric miao }
1988f58de7cSeric miao 
1998f58de7cSeric miao static struct resource pxa_resource_ffuart[] = {
2008f58de7cSeric miao 	{
20102f65262SEric Miao 		.start	= 0x40100000,
20202f65262SEric Miao 		.end	= 0x40100023,
2038f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2048f58de7cSeric miao 	}, {
2058f58de7cSeric miao 		.start	= IRQ_FFUART,
2068f58de7cSeric miao 		.end	= IRQ_FFUART,
2078f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2088f58de7cSeric miao 	}
2098f58de7cSeric miao };
2108f58de7cSeric miao 
2118f58de7cSeric miao struct platform_device pxa_device_ffuart = {
2128f58de7cSeric miao 	.name		= "pxa2xx-uart",
2138f58de7cSeric miao 	.id		= 0,
2148f58de7cSeric miao 	.resource	= pxa_resource_ffuart,
2158f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_ffuart),
2168f58de7cSeric miao };
2178f58de7cSeric miao 
218cc155c6fSRussell King void __init pxa_set_ffuart_info(void *info)
219cc155c6fSRussell King {
220cc155c6fSRussell King 	pxa_register_device(&pxa_device_ffuart, info);
221cc155c6fSRussell King }
222cc155c6fSRussell King 
2238f58de7cSeric miao static struct resource pxa_resource_btuart[] = {
2248f58de7cSeric miao 	{
22502f65262SEric Miao 		.start	= 0x40200000,
22602f65262SEric Miao 		.end	= 0x40200023,
2278f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2288f58de7cSeric miao 	}, {
2298f58de7cSeric miao 		.start	= IRQ_BTUART,
2308f58de7cSeric miao 		.end	= IRQ_BTUART,
2318f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2328f58de7cSeric miao 	}
2338f58de7cSeric miao };
2348f58de7cSeric miao 
2358f58de7cSeric miao struct platform_device pxa_device_btuart = {
2368f58de7cSeric miao 	.name		= "pxa2xx-uart",
2378f58de7cSeric miao 	.id		= 1,
2388f58de7cSeric miao 	.resource	= pxa_resource_btuart,
2398f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_btuart),
2408f58de7cSeric miao };
2418f58de7cSeric miao 
242cc155c6fSRussell King void __init pxa_set_btuart_info(void *info)
243cc155c6fSRussell King {
244cc155c6fSRussell King 	pxa_register_device(&pxa_device_btuart, info);
245cc155c6fSRussell King }
246cc155c6fSRussell King 
2478f58de7cSeric miao static struct resource pxa_resource_stuart[] = {
2488f58de7cSeric miao 	{
24902f65262SEric Miao 		.start	= 0x40700000,
25002f65262SEric Miao 		.end	= 0x40700023,
2518f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2528f58de7cSeric miao 	}, {
2538f58de7cSeric miao 		.start	= IRQ_STUART,
2548f58de7cSeric miao 		.end	= IRQ_STUART,
2558f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2568f58de7cSeric miao 	}
2578f58de7cSeric miao };
2588f58de7cSeric miao 
2598f58de7cSeric miao struct platform_device pxa_device_stuart = {
2608f58de7cSeric miao 	.name		= "pxa2xx-uart",
2618f58de7cSeric miao 	.id		= 2,
2628f58de7cSeric miao 	.resource	= pxa_resource_stuart,
2638f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_stuart),
2648f58de7cSeric miao };
2658f58de7cSeric miao 
266cc155c6fSRussell King void __init pxa_set_stuart_info(void *info)
267cc155c6fSRussell King {
268cc155c6fSRussell King 	pxa_register_device(&pxa_device_stuart, info);
269cc155c6fSRussell King }
270cc155c6fSRussell King 
2718f58de7cSeric miao static struct resource pxa_resource_hwuart[] = {
2728f58de7cSeric miao 	{
27302f65262SEric Miao 		.start	= 0x41600000,
27402f65262SEric Miao 		.end	= 0x4160002F,
2758f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
2768f58de7cSeric miao 	}, {
2778f58de7cSeric miao 		.start	= IRQ_HWUART,
2788f58de7cSeric miao 		.end	= IRQ_HWUART,
2798f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
2808f58de7cSeric miao 	}
2818f58de7cSeric miao };
2828f58de7cSeric miao 
2838f58de7cSeric miao struct platform_device pxa_device_hwuart = {
2848f58de7cSeric miao 	.name		= "pxa2xx-uart",
2858f58de7cSeric miao 	.id		= 3,
2868f58de7cSeric miao 	.resource	= pxa_resource_hwuart,
2878f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
2888f58de7cSeric miao };
2898f58de7cSeric miao 
290cc155c6fSRussell King void __init pxa_set_hwuart_info(void *info)
291cc155c6fSRussell King {
292cc155c6fSRussell King 	if (cpu_is_pxa255())
293cc155c6fSRussell King 		pxa_register_device(&pxa_device_hwuart, info);
294cc155c6fSRussell King 	else
295cc155c6fSRussell King 		pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
296cc155c6fSRussell King }
297cc155c6fSRussell King 
2988f58de7cSeric miao static struct resource pxai2c_resources[] = {
2998f58de7cSeric miao 	{
3008f58de7cSeric miao 		.start	= 0x40301680,
3018f58de7cSeric miao 		.end	= 0x403016a3,
3028f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3038f58de7cSeric miao 	}, {
3048f58de7cSeric miao 		.start	= IRQ_I2C,
3058f58de7cSeric miao 		.end	= IRQ_I2C,
3068f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3078f58de7cSeric miao 	},
3088f58de7cSeric miao };
3098f58de7cSeric miao 
3108f58de7cSeric miao struct platform_device pxa_device_i2c = {
3118f58de7cSeric miao 	.name		= "pxa2xx-i2c",
3128f58de7cSeric miao 	.id		= 0,
3138f58de7cSeric miao 	.resource	= pxai2c_resources,
3148f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2c_resources),
3158f58de7cSeric miao };
3168f58de7cSeric miao 
3178f58de7cSeric miao void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
3188f58de7cSeric miao {
3198f58de7cSeric miao 	pxa_register_device(&pxa_device_i2c, info);
3208f58de7cSeric miao }
3218f58de7cSeric miao 
32299464293SEric Miao #ifdef CONFIG_PXA27x
32399464293SEric Miao static struct resource pxa27x_resources_i2c_power[] = {
32499464293SEric Miao 	{
32599464293SEric Miao 		.start	= 0x40f00180,
32699464293SEric Miao 		.end	= 0x40f001a3,
32799464293SEric Miao 		.flags	= IORESOURCE_MEM,
32899464293SEric Miao 	}, {
32999464293SEric Miao 		.start	= IRQ_PWRI2C,
33099464293SEric Miao 		.end	= IRQ_PWRI2C,
33199464293SEric Miao 		.flags	= IORESOURCE_IRQ,
33299464293SEric Miao 	},
33399464293SEric Miao };
33499464293SEric Miao 
33599464293SEric Miao struct platform_device pxa27x_device_i2c_power = {
33699464293SEric Miao 	.name		= "pxa2xx-i2c",
33799464293SEric Miao 	.id		= 1,
33899464293SEric Miao 	.resource	= pxa27x_resources_i2c_power,
33999464293SEric Miao 	.num_resources	= ARRAY_SIZE(pxa27x_resources_i2c_power),
34099464293SEric Miao };
34199464293SEric Miao #endif
34299464293SEric Miao 
3438f58de7cSeric miao static struct resource pxai2s_resources[] = {
3448f58de7cSeric miao 	{
3458f58de7cSeric miao 		.start	= 0x40400000,
3468f58de7cSeric miao 		.end	= 0x40400083,
3478f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
3488f58de7cSeric miao 	}, {
3498f58de7cSeric miao 		.start	= IRQ_I2S,
3508f58de7cSeric miao 		.end	= IRQ_I2S,
3518f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
3528f58de7cSeric miao 	},
3538f58de7cSeric miao };
3548f58de7cSeric miao 
3558f58de7cSeric miao struct platform_device pxa_device_i2s = {
3568f58de7cSeric miao 	.name		= "pxa2xx-i2s",
3578f58de7cSeric miao 	.id		= -1,
3588f58de7cSeric miao 	.resource	= pxai2s_resources,
3598f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxai2s_resources),
3608f58de7cSeric miao };
3618f58de7cSeric miao 
362f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp1 = {
363f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
364f0fba2adSLiam Girdwood 	.id		= 0,
365f0fba2adSLiam Girdwood };
366f0fba2adSLiam Girdwood 
367f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp2= {
368f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
369f0fba2adSLiam Girdwood 	.id		= 1,
370f0fba2adSLiam Girdwood };
371f0fba2adSLiam Girdwood 
372f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp3 = {
373f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
374f0fba2adSLiam Girdwood 	.id		= 2,
375f0fba2adSLiam Girdwood };
376f0fba2adSLiam Girdwood 
377f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_ssp4 = {
378f0fba2adSLiam Girdwood 	.name		= "pxa-ssp-dai",
379f0fba2adSLiam Girdwood 	.id		= 3,
380f0fba2adSLiam Girdwood };
381f0fba2adSLiam Girdwood 
382f0fba2adSLiam Girdwood struct platform_device pxa_device_asoc_platform = {
383f0fba2adSLiam Girdwood 	.name		= "pxa-pcm-audio",
384f0fba2adSLiam Girdwood 	.id		= -1,
385f0fba2adSLiam Girdwood };
386f0fba2adSLiam Girdwood 
3878f58de7cSeric miao static u64 pxaficp_dmamask = ~(u32)0;
3888f58de7cSeric miao 
389121f3f9bSRob Herring static struct resource pxa_ir_resources[] = {
390121f3f9bSRob Herring 	[0] = {
391121f3f9bSRob Herring 		.start  = IRQ_STUART,
392121f3f9bSRob Herring 		.end    = IRQ_STUART,
393121f3f9bSRob Herring 		.flags  = IORESOURCE_IRQ,
394121f3f9bSRob Herring 	},
395121f3f9bSRob Herring 	[1] = {
396121f3f9bSRob Herring 		.start  = IRQ_ICP,
397121f3f9bSRob Herring 		.end    = IRQ_ICP,
398121f3f9bSRob Herring 		.flags  = IORESOURCE_IRQ,
399121f3f9bSRob Herring 	},
40048a629daSRobert Jarzmik 	[3] = {
40148a629daSRobert Jarzmik 		.start  = 0x40800000,
40248a629daSRobert Jarzmik 		.end	= 0x4080001b,
40348a629daSRobert Jarzmik 		.flags  = IORESOURCE_MEM,
40448a629daSRobert Jarzmik 	},
40548a629daSRobert Jarzmik 	[4] = {
40648a629daSRobert Jarzmik 		.start  = 0x40700000,
40748a629daSRobert Jarzmik 		.end	= 0x40700023,
40848a629daSRobert Jarzmik 		.flags  = IORESOURCE_MEM,
40948a629daSRobert Jarzmik 	},
41048a629daSRobert Jarzmik 	[5] = {
41148a629daSRobert Jarzmik 		.start  = 17,
41248a629daSRobert Jarzmik 		.end	= 17,
41348a629daSRobert Jarzmik 		.flags  = IORESOURCE_DMA,
41448a629daSRobert Jarzmik 	},
41548a629daSRobert Jarzmik 	[6] = {
41648a629daSRobert Jarzmik 		.start  = 18,
41748a629daSRobert Jarzmik 		.end	= 18,
41848a629daSRobert Jarzmik 		.flags  = IORESOURCE_DMA,
41948a629daSRobert Jarzmik 	},
420121f3f9bSRob Herring };
421121f3f9bSRob Herring 
4228f58de7cSeric miao struct platform_device pxa_device_ficp = {
4238f58de7cSeric miao 	.name		= "pxa2xx-ir",
4248f58de7cSeric miao 	.id		= -1,
425121f3f9bSRob Herring 	.num_resources	= ARRAY_SIZE(pxa_ir_resources),
426121f3f9bSRob Herring 	.resource	= pxa_ir_resources,
4278f58de7cSeric miao 	.dev		= {
4288f58de7cSeric miao 		.dma_mask = &pxaficp_dmamask,
4298f58de7cSeric miao 		.coherent_dma_mask = 0xffffffff,
4308f58de7cSeric miao 	},
4318f58de7cSeric miao };
4328f58de7cSeric miao 
4338f58de7cSeric miao void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
4348f58de7cSeric miao {
4358f58de7cSeric miao 	pxa_register_device(&pxa_device_ficp, info);
4368f58de7cSeric miao }
4378f58de7cSeric miao 
43872493146SRobert Jarzmik static struct resource pxa_rtc_resources[] = {
43972493146SRobert Jarzmik 	[0] = {
44072493146SRobert Jarzmik 		.start  = 0x40900000,
44172493146SRobert Jarzmik 		.end	= 0x40900000 + 0x3b,
44272493146SRobert Jarzmik 		.flags  = IORESOURCE_MEM,
44372493146SRobert Jarzmik 	},
44472493146SRobert Jarzmik 	[1] = {
44572493146SRobert Jarzmik 		.start  = IRQ_RTC1Hz,
44672493146SRobert Jarzmik 		.end    = IRQ_RTC1Hz,
4473888c090SHaojian Zhuang 		.name	= "rtc 1Hz",
44872493146SRobert Jarzmik 		.flags  = IORESOURCE_IRQ,
44972493146SRobert Jarzmik 	},
45072493146SRobert Jarzmik 	[2] = {
45172493146SRobert Jarzmik 		.start  = IRQ_RTCAlrm,
45272493146SRobert Jarzmik 		.end    = IRQ_RTCAlrm,
4533888c090SHaojian Zhuang 		.name	= "rtc alarm",
45472493146SRobert Jarzmik 		.flags  = IORESOURCE_IRQ,
45572493146SRobert Jarzmik 	},
45672493146SRobert Jarzmik };
45772493146SRobert Jarzmik 
45872493146SRobert Jarzmik struct platform_device pxa_device_rtc = {
45972493146SRobert Jarzmik 	.name		= "pxa-rtc",
46072493146SRobert Jarzmik 	.id		= -1,
46172493146SRobert Jarzmik 	.num_resources  = ARRAY_SIZE(pxa_rtc_resources),
46272493146SRobert Jarzmik 	.resource       = pxa_rtc_resources,
46372493146SRobert Jarzmik };
46472493146SRobert Jarzmik 
4653888c090SHaojian Zhuang struct platform_device sa1100_device_rtc = {
4663888c090SHaojian Zhuang 	.name		= "sa1100-rtc",
4673888c090SHaojian Zhuang 	.id		= -1,
4682c4fabecSRob Herring 	.num_resources  = ARRAY_SIZE(pxa_rtc_resources),
4692c4fabecSRob Herring 	.resource       = pxa_rtc_resources,
4703888c090SHaojian Zhuang };
4713888c090SHaojian Zhuang 
4729f19d638SMark Brown static struct resource pxa_ac97_resources[] = {
4739f19d638SMark Brown 	[0] = {
4749f19d638SMark Brown 		.start  = 0x40500000,
4759f19d638SMark Brown 		.end	= 0x40500000 + 0xfff,
4769f19d638SMark Brown 		.flags  = IORESOURCE_MEM,
4779f19d638SMark Brown 	},
4789f19d638SMark Brown 	[1] = {
4799f19d638SMark Brown 		.start  = IRQ_AC97,
4809f19d638SMark Brown 		.end    = IRQ_AC97,
4819f19d638SMark Brown 		.flags  = IORESOURCE_IRQ,
4829f19d638SMark Brown 	},
4839f19d638SMark Brown };
4849f19d638SMark Brown 
4859f19d638SMark Brown static u64 pxa_ac97_dmamask = 0xffffffffUL;
4869f19d638SMark Brown 
4879f19d638SMark Brown struct platform_device pxa_device_ac97 = {
4889f19d638SMark Brown 	.name           = "pxa2xx-ac97",
4899f19d638SMark Brown 	.id             = -1,
4909f19d638SMark Brown 	.dev            = {
4919f19d638SMark Brown 		.dma_mask = &pxa_ac97_dmamask,
4929f19d638SMark Brown 		.coherent_dma_mask = 0xffffffff,
4939f19d638SMark Brown 	},
4949f19d638SMark Brown 	.num_resources  = ARRAY_SIZE(pxa_ac97_resources),
4959f19d638SMark Brown 	.resource       = pxa_ac97_resources,
4969f19d638SMark Brown };
4979f19d638SMark Brown 
4989f19d638SMark Brown void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
4999f19d638SMark Brown {
5009f19d638SMark Brown 	pxa_register_device(&pxa_device_ac97, ops);
5019f19d638SMark Brown }
5029f19d638SMark Brown 
5038f58de7cSeric miao #ifdef CONFIG_PXA25x
5048f58de7cSeric miao 
50575540c1aSeric miao static struct resource pxa25x_resource_pwm0[] = {
50675540c1aSeric miao 	[0] = {
50775540c1aSeric miao 		.start	= 0x40b00000,
50875540c1aSeric miao 		.end	= 0x40b0000f,
50975540c1aSeric miao 		.flags	= IORESOURCE_MEM,
51075540c1aSeric miao 	},
51175540c1aSeric miao };
51275540c1aSeric miao 
51375540c1aSeric miao struct platform_device pxa25x_device_pwm0 = {
51475540c1aSeric miao 	.name		= "pxa25x-pwm",
51575540c1aSeric miao 	.id		= 0,
51675540c1aSeric miao 	.resource	= pxa25x_resource_pwm0,
51775540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm0),
51875540c1aSeric miao };
51975540c1aSeric miao 
52075540c1aSeric miao static struct resource pxa25x_resource_pwm1[] = {
52175540c1aSeric miao 	[0] = {
52275540c1aSeric miao 		.start	= 0x40c00000,
52375540c1aSeric miao 		.end	= 0x40c0000f,
52475540c1aSeric miao 		.flags	= IORESOURCE_MEM,
52575540c1aSeric miao 	},
52675540c1aSeric miao };
52775540c1aSeric miao 
52875540c1aSeric miao struct platform_device pxa25x_device_pwm1 = {
52975540c1aSeric miao 	.name		= "pxa25x-pwm",
53075540c1aSeric miao 	.id		= 1,
53175540c1aSeric miao 	.resource	= pxa25x_resource_pwm1,
53275540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_pwm1),
53375540c1aSeric miao };
53475540c1aSeric miao 
5358f58de7cSeric miao static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
5368f58de7cSeric miao 
5378f58de7cSeric miao static struct resource pxa25x_resource_ssp[] = {
5388f58de7cSeric miao 	[0] = {
5398f58de7cSeric miao 		.start	= 0x41000000,
5408f58de7cSeric miao 		.end	= 0x4100001f,
5418f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5428f58de7cSeric miao 	},
5438f58de7cSeric miao 	[1] = {
5448f58de7cSeric miao 		.start	= IRQ_SSP,
5458f58de7cSeric miao 		.end	= IRQ_SSP,
5468f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5478f58de7cSeric miao 	},
5488f58de7cSeric miao 	[2] = {
5498f58de7cSeric miao 		/* DRCMR for RX */
5508f58de7cSeric miao 		.start	= 13,
5518f58de7cSeric miao 		.end	= 13,
5528f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5538f58de7cSeric miao 	},
5548f58de7cSeric miao 	[3] = {
5558f58de7cSeric miao 		/* DRCMR for TX */
5568f58de7cSeric miao 		.start	= 14,
5578f58de7cSeric miao 		.end	= 14,
5588f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5598f58de7cSeric miao 	},
5608f58de7cSeric miao };
5618f58de7cSeric miao 
5628f58de7cSeric miao struct platform_device pxa25x_device_ssp = {
5638f58de7cSeric miao 	.name		= "pxa25x-ssp",
5648f58de7cSeric miao 	.id		= 0,
5658f58de7cSeric miao 	.dev		= {
5668f58de7cSeric miao 		.dma_mask = &pxa25x_ssp_dma_mask,
5678f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
5688f58de7cSeric miao 	},
5698f58de7cSeric miao 	.resource	= pxa25x_resource_ssp,
5708f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_ssp),
5718f58de7cSeric miao };
5728f58de7cSeric miao 
5738f58de7cSeric miao static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
5748f58de7cSeric miao 
5758f58de7cSeric miao static struct resource pxa25x_resource_nssp[] = {
5768f58de7cSeric miao 	[0] = {
5778f58de7cSeric miao 		.start	= 0x41400000,
5788f58de7cSeric miao 		.end	= 0x4140002f,
5798f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
5808f58de7cSeric miao 	},
5818f58de7cSeric miao 	[1] = {
5828f58de7cSeric miao 		.start	= IRQ_NSSP,
5838f58de7cSeric miao 		.end	= IRQ_NSSP,
5848f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
5858f58de7cSeric miao 	},
5868f58de7cSeric miao 	[2] = {
5878f58de7cSeric miao 		/* DRCMR for RX */
5888f58de7cSeric miao 		.start	= 15,
5898f58de7cSeric miao 		.end	= 15,
5908f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5918f58de7cSeric miao 	},
5928f58de7cSeric miao 	[3] = {
5938f58de7cSeric miao 		/* DRCMR for TX */
5948f58de7cSeric miao 		.start	= 16,
5958f58de7cSeric miao 		.end	= 16,
5968f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
5978f58de7cSeric miao 	},
5988f58de7cSeric miao };
5998f58de7cSeric miao 
6008f58de7cSeric miao struct platform_device pxa25x_device_nssp = {
6018f58de7cSeric miao 	.name		= "pxa25x-nssp",
6028f58de7cSeric miao 	.id		= 1,
6038f58de7cSeric miao 	.dev		= {
6048f58de7cSeric miao 		.dma_mask = &pxa25x_nssp_dma_mask,
6058f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
6068f58de7cSeric miao 	},
6078f58de7cSeric miao 	.resource	= pxa25x_resource_nssp,
6088f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_nssp),
6098f58de7cSeric miao };
6108f58de7cSeric miao 
6118f58de7cSeric miao static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
6128f58de7cSeric miao 
6138f58de7cSeric miao static struct resource pxa25x_resource_assp[] = {
6148f58de7cSeric miao 	[0] = {
6158f58de7cSeric miao 		.start	= 0x41500000,
6168f58de7cSeric miao 		.end	= 0x4150002f,
6178f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
6188f58de7cSeric miao 	},
6198f58de7cSeric miao 	[1] = {
6208f58de7cSeric miao 		.start	= IRQ_ASSP,
6218f58de7cSeric miao 		.end	= IRQ_ASSP,
6228f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
6238f58de7cSeric miao 	},
6248f58de7cSeric miao 	[2] = {
6258f58de7cSeric miao 		/* DRCMR for RX */
6268f58de7cSeric miao 		.start	= 23,
6278f58de7cSeric miao 		.end	= 23,
6288f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6298f58de7cSeric miao 	},
6308f58de7cSeric miao 	[3] = {
6318f58de7cSeric miao 		/* DRCMR for TX */
6328f58de7cSeric miao 		.start	= 24,
6338f58de7cSeric miao 		.end	= 24,
6348f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
6358f58de7cSeric miao 	},
6368f58de7cSeric miao };
6378f58de7cSeric miao 
6388f58de7cSeric miao struct platform_device pxa25x_device_assp = {
6398f58de7cSeric miao 	/* ASSP is basically equivalent to NSSP */
6408f58de7cSeric miao 	.name		= "pxa25x-nssp",
6418f58de7cSeric miao 	.id		= 2,
6428f58de7cSeric miao 	.dev		= {
6438f58de7cSeric miao 		.dma_mask = &pxa25x_assp_dma_mask,
6448f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
6458f58de7cSeric miao 	},
6468f58de7cSeric miao 	.resource	= pxa25x_resource_assp,
6478f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa25x_resource_assp),
6488f58de7cSeric miao };
6498f58de7cSeric miao #endif /* CONFIG_PXA25x */
6508f58de7cSeric miao 
6518f58de7cSeric miao #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
652a4553358SHaojian Zhuang static struct resource pxa27x_resource_camera[] = {
65337320980Seric miao 	[0] = {
654a4553358SHaojian Zhuang 		.start	= 0x50000000,
655a4553358SHaojian Zhuang 		.end	= 0x50000fff,
65637320980Seric miao 		.flags	= IORESOURCE_MEM,
65737320980Seric miao 	},
65837320980Seric miao 	[1] = {
659a4553358SHaojian Zhuang 		.start	= IRQ_CAMERA,
660a4553358SHaojian Zhuang 		.end	= IRQ_CAMERA,
66137320980Seric miao 		.flags	= IORESOURCE_IRQ,
66237320980Seric miao 	},
66337320980Seric miao };
66437320980Seric miao 
665a4553358SHaojian Zhuang static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
666a4553358SHaojian Zhuang 
667a4553358SHaojian Zhuang static struct platform_device pxa27x_device_camera = {
668a4553358SHaojian Zhuang 	.name		= "pxa27x-camera",
669a4553358SHaojian Zhuang 	.id		= 0, /* This is used to put cameras on this interface */
670a4553358SHaojian Zhuang 	.dev		= {
671a4553358SHaojian Zhuang 		.dma_mask      		= &pxa27x_dma_mask_camera,
672a4553358SHaojian Zhuang 		.coherent_dma_mask	= 0xffffffff,
673a4553358SHaojian Zhuang 	},
674a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa27x_resource_camera),
675a4553358SHaojian Zhuang 	.resource	= pxa27x_resource_camera,
67637320980Seric miao };
67737320980Seric miao 
678a4553358SHaojian Zhuang void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
67937320980Seric miao {
680a4553358SHaojian Zhuang 	pxa_register_device(&pxa27x_device_camera, info);
68137320980Seric miao }
68237320980Seric miao 
683ec68e45bSeric miao static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
684ec68e45bSeric miao 
685ec68e45bSeric miao static struct resource pxa27x_resource_ohci[] = {
686ec68e45bSeric miao 	[0] = {
687ec68e45bSeric miao 		.start  = 0x4C000000,
688ec68e45bSeric miao 		.end    = 0x4C00ff6f,
689ec68e45bSeric miao 		.flags  = IORESOURCE_MEM,
690ec68e45bSeric miao 	},
691ec68e45bSeric miao 	[1] = {
692ec68e45bSeric miao 		.start  = IRQ_USBH1,
693ec68e45bSeric miao 		.end    = IRQ_USBH1,
694ec68e45bSeric miao 		.flags  = IORESOURCE_IRQ,
695ec68e45bSeric miao 	},
696ec68e45bSeric miao };
697ec68e45bSeric miao 
698ec68e45bSeric miao struct platform_device pxa27x_device_ohci = {
699ec68e45bSeric miao 	.name		= "pxa27x-ohci",
700ec68e45bSeric miao 	.id		= -1,
701ec68e45bSeric miao 	.dev		= {
702ec68e45bSeric miao 		.dma_mask = &pxa27x_ohci_dma_mask,
703ec68e45bSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
704ec68e45bSeric miao 	},
705ec68e45bSeric miao 	.num_resources  = ARRAY_SIZE(pxa27x_resource_ohci),
706ec68e45bSeric miao 	.resource       = pxa27x_resource_ohci,
707ec68e45bSeric miao };
708ec68e45bSeric miao 
709ec68e45bSeric miao void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
710ec68e45bSeric miao {
711ec68e45bSeric miao 	pxa_register_device(&pxa27x_device_ohci, info);
712ec68e45bSeric miao }
713a4553358SHaojian Zhuang #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
714a4553358SHaojian Zhuang 
71549ea7fc0SHaojian Zhuang #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
716a4553358SHaojian Zhuang static struct resource pxa27x_resource_keypad[] = {
717a4553358SHaojian Zhuang 	[0] = {
718a4553358SHaojian Zhuang 		.start	= 0x41500000,
719a4553358SHaojian Zhuang 		.end	= 0x4150004c,
720a4553358SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
721a4553358SHaojian Zhuang 	},
722a4553358SHaojian Zhuang 	[1] = {
723a4553358SHaojian Zhuang 		.start	= IRQ_KEYPAD,
724a4553358SHaojian Zhuang 		.end	= IRQ_KEYPAD,
725a4553358SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
726a4553358SHaojian Zhuang 	},
727a4553358SHaojian Zhuang };
728a4553358SHaojian Zhuang 
729a4553358SHaojian Zhuang struct platform_device pxa27x_device_keypad = {
730a4553358SHaojian Zhuang 	.name		= "pxa27x-keypad",
731a4553358SHaojian Zhuang 	.id		= -1,
732a4553358SHaojian Zhuang 	.resource	= pxa27x_resource_keypad,
733a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa27x_resource_keypad),
734a4553358SHaojian Zhuang };
735a4553358SHaojian Zhuang 
736a4553358SHaojian Zhuang void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
737a4553358SHaojian Zhuang {
738a4553358SHaojian Zhuang 	pxa_register_device(&pxa27x_device_keypad, info);
739a4553358SHaojian Zhuang }
740ec68e45bSeric miao 
7418f58de7cSeric miao static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
7428f58de7cSeric miao 
7438f58de7cSeric miao static struct resource pxa27x_resource_ssp1[] = {
7448f58de7cSeric miao 	[0] = {
7458f58de7cSeric miao 		.start	= 0x41000000,
7468f58de7cSeric miao 		.end	= 0x4100003f,
7478f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
7488f58de7cSeric miao 	},
7498f58de7cSeric miao 	[1] = {
7508f58de7cSeric miao 		.start	= IRQ_SSP,
7518f58de7cSeric miao 		.end	= IRQ_SSP,
7528f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
7538f58de7cSeric miao 	},
7548f58de7cSeric miao 	[2] = {
7558f58de7cSeric miao 		/* DRCMR for RX */
7568f58de7cSeric miao 		.start	= 13,
7578f58de7cSeric miao 		.end	= 13,
7588f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7598f58de7cSeric miao 	},
7608f58de7cSeric miao 	[3] = {
7618f58de7cSeric miao 		/* DRCMR for TX */
7628f58de7cSeric miao 		.start	= 14,
7638f58de7cSeric miao 		.end	= 14,
7648f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7658f58de7cSeric miao 	},
7668f58de7cSeric miao };
7678f58de7cSeric miao 
7688f58de7cSeric miao struct platform_device pxa27x_device_ssp1 = {
7698f58de7cSeric miao 	.name		= "pxa27x-ssp",
7708f58de7cSeric miao 	.id		= 0,
7718f58de7cSeric miao 	.dev		= {
7728f58de7cSeric miao 		.dma_mask = &pxa27x_ssp1_dma_mask,
7738f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
7748f58de7cSeric miao 	},
7758f58de7cSeric miao 	.resource	= pxa27x_resource_ssp1,
7768f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
7778f58de7cSeric miao };
7788f58de7cSeric miao 
7798f58de7cSeric miao static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
7808f58de7cSeric miao 
7818f58de7cSeric miao static struct resource pxa27x_resource_ssp2[] = {
7828f58de7cSeric miao 	[0] = {
7838f58de7cSeric miao 		.start	= 0x41700000,
7848f58de7cSeric miao 		.end	= 0x4170003f,
7858f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
7868f58de7cSeric miao 	},
7878f58de7cSeric miao 	[1] = {
7888f58de7cSeric miao 		.start	= IRQ_SSP2,
7898f58de7cSeric miao 		.end	= IRQ_SSP2,
7908f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
7918f58de7cSeric miao 	},
7928f58de7cSeric miao 	[2] = {
7938f58de7cSeric miao 		/* DRCMR for RX */
7948f58de7cSeric miao 		.start	= 15,
7958f58de7cSeric miao 		.end	= 15,
7968f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
7978f58de7cSeric miao 	},
7988f58de7cSeric miao 	[3] = {
7998f58de7cSeric miao 		/* DRCMR for TX */
8008f58de7cSeric miao 		.start	= 16,
8018f58de7cSeric miao 		.end	= 16,
8028f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
8038f58de7cSeric miao 	},
8048f58de7cSeric miao };
8058f58de7cSeric miao 
8068f58de7cSeric miao struct platform_device pxa27x_device_ssp2 = {
8078f58de7cSeric miao 	.name		= "pxa27x-ssp",
8088f58de7cSeric miao 	.id		= 1,
8098f58de7cSeric miao 	.dev		= {
8108f58de7cSeric miao 		.dma_mask = &pxa27x_ssp2_dma_mask,
8118f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
8128f58de7cSeric miao 	},
8138f58de7cSeric miao 	.resource	= pxa27x_resource_ssp2,
8148f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
8158f58de7cSeric miao };
8168f58de7cSeric miao 
8178f58de7cSeric miao static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
8188f58de7cSeric miao 
8198f58de7cSeric miao static struct resource pxa27x_resource_ssp3[] = {
8208f58de7cSeric miao 	[0] = {
8218f58de7cSeric miao 		.start	= 0x41900000,
8228f58de7cSeric miao 		.end	= 0x4190003f,
8238f58de7cSeric miao 		.flags	= IORESOURCE_MEM,
8248f58de7cSeric miao 	},
8258f58de7cSeric miao 	[1] = {
8268f58de7cSeric miao 		.start	= IRQ_SSP3,
8278f58de7cSeric miao 		.end	= IRQ_SSP3,
8288f58de7cSeric miao 		.flags	= IORESOURCE_IRQ,
8298f58de7cSeric miao 	},
8308f58de7cSeric miao 	[2] = {
8318f58de7cSeric miao 		/* DRCMR for RX */
8328f58de7cSeric miao 		.start	= 66,
8338f58de7cSeric miao 		.end	= 66,
8348f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
8358f58de7cSeric miao 	},
8368f58de7cSeric miao 	[3] = {
8378f58de7cSeric miao 		/* DRCMR for TX */
8388f58de7cSeric miao 		.start	= 67,
8398f58de7cSeric miao 		.end	= 67,
8408f58de7cSeric miao 		.flags	= IORESOURCE_DMA,
8418f58de7cSeric miao 	},
8428f58de7cSeric miao };
8438f58de7cSeric miao 
8448f58de7cSeric miao struct platform_device pxa27x_device_ssp3 = {
8458f58de7cSeric miao 	.name		= "pxa27x-ssp",
8468f58de7cSeric miao 	.id		= 2,
8478f58de7cSeric miao 	.dev		= {
8488f58de7cSeric miao 		.dma_mask = &pxa27x_ssp3_dma_mask,
8498f58de7cSeric miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
8508f58de7cSeric miao 	},
8518f58de7cSeric miao 	.resource	= pxa27x_resource_ssp3,
8528f58de7cSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
8538f58de7cSeric miao };
8543f3acefbSGuennadi Liakhovetski 
85575540c1aSeric miao static struct resource pxa27x_resource_pwm0[] = {
85675540c1aSeric miao 	[0] = {
85775540c1aSeric miao 		.start	= 0x40b00000,
85875540c1aSeric miao 		.end	= 0x40b0001f,
85975540c1aSeric miao 		.flags	= IORESOURCE_MEM,
86075540c1aSeric miao 	},
86175540c1aSeric miao };
86275540c1aSeric miao 
86375540c1aSeric miao struct platform_device pxa27x_device_pwm0 = {
86475540c1aSeric miao 	.name		= "pxa27x-pwm",
86575540c1aSeric miao 	.id		= 0,
86675540c1aSeric miao 	.resource	= pxa27x_resource_pwm0,
86775540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm0),
86875540c1aSeric miao };
86975540c1aSeric miao 
87075540c1aSeric miao static struct resource pxa27x_resource_pwm1[] = {
87175540c1aSeric miao 	[0] = {
87275540c1aSeric miao 		.start	= 0x40c00000,
87375540c1aSeric miao 		.end	= 0x40c0001f,
87475540c1aSeric miao 		.flags	= IORESOURCE_MEM,
87575540c1aSeric miao 	},
87675540c1aSeric miao };
87775540c1aSeric miao 
87875540c1aSeric miao struct platform_device pxa27x_device_pwm1 = {
87975540c1aSeric miao 	.name		= "pxa27x-pwm",
88075540c1aSeric miao 	.id		= 1,
88175540c1aSeric miao 	.resource	= pxa27x_resource_pwm1,
88275540c1aSeric miao 	.num_resources	= ARRAY_SIZE(pxa27x_resource_pwm1),
88375540c1aSeric miao };
88449ea7fc0SHaojian Zhuang #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
8858f58de7cSeric miao 
8868f58de7cSeric miao #ifdef CONFIG_PXA3xx
8878d33b055SBridge Wu static struct resource pxa3xx_resources_mci2[] = {
8888d33b055SBridge Wu 	[0] = {
8898d33b055SBridge Wu 		.start	= 0x42000000,
8908d33b055SBridge Wu 		.end	= 0x42000fff,
8918d33b055SBridge Wu 		.flags	= IORESOURCE_MEM,
8928d33b055SBridge Wu 	},
8938d33b055SBridge Wu 	[1] = {
8948d33b055SBridge Wu 		.start	= IRQ_MMC2,
8958d33b055SBridge Wu 		.end	= IRQ_MMC2,
8968d33b055SBridge Wu 		.flags	= IORESOURCE_IRQ,
8978d33b055SBridge Wu 	},
8988d33b055SBridge Wu 	[2] = {
8998d33b055SBridge Wu 		.start	= 93,
9008d33b055SBridge Wu 		.end	= 93,
9018d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
9028d33b055SBridge Wu 	},
9038d33b055SBridge Wu 	[3] = {
9048d33b055SBridge Wu 		.start	= 94,
9058d33b055SBridge Wu 		.end	= 94,
9068d33b055SBridge Wu 		.flags	= IORESOURCE_DMA,
9078d33b055SBridge Wu 	},
9088d33b055SBridge Wu };
9098d33b055SBridge Wu 
9108d33b055SBridge Wu struct platform_device pxa3xx_device_mci2 = {
9118d33b055SBridge Wu 	.name		= "pxa2xx-mci",
9128d33b055SBridge Wu 	.id		= 1,
9138d33b055SBridge Wu 	.dev		= {
9148d33b055SBridge Wu 		.dma_mask = &pxamci_dmamask,
9158d33b055SBridge Wu 		.coherent_dma_mask =	0xffffffff,
9168d33b055SBridge Wu 	},
9178d33b055SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci2),
9188d33b055SBridge Wu 	.resource	= pxa3xx_resources_mci2,
9198d33b055SBridge Wu };
9208d33b055SBridge Wu 
9218d33b055SBridge Wu void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
9228d33b055SBridge Wu {
9238d33b055SBridge Wu 	pxa_register_device(&pxa3xx_device_mci2, info);
9248d33b055SBridge Wu }
9258d33b055SBridge Wu 
9265a1f21b1SBridge Wu static struct resource pxa3xx_resources_mci3[] = {
9275a1f21b1SBridge Wu 	[0] = {
9285a1f21b1SBridge Wu 		.start	= 0x42500000,
9295a1f21b1SBridge Wu 		.end	= 0x42500fff,
9305a1f21b1SBridge Wu 		.flags	= IORESOURCE_MEM,
9315a1f21b1SBridge Wu 	},
9325a1f21b1SBridge Wu 	[1] = {
9335a1f21b1SBridge Wu 		.start	= IRQ_MMC3,
9345a1f21b1SBridge Wu 		.end	= IRQ_MMC3,
9355a1f21b1SBridge Wu 		.flags	= IORESOURCE_IRQ,
9365a1f21b1SBridge Wu 	},
9375a1f21b1SBridge Wu 	[2] = {
9385a1f21b1SBridge Wu 		.start	= 100,
9395a1f21b1SBridge Wu 		.end	= 100,
9405a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
9415a1f21b1SBridge Wu 	},
9425a1f21b1SBridge Wu 	[3] = {
9435a1f21b1SBridge Wu 		.start	= 101,
9445a1f21b1SBridge Wu 		.end	= 101,
9455a1f21b1SBridge Wu 		.flags	= IORESOURCE_DMA,
9465a1f21b1SBridge Wu 	},
9475a1f21b1SBridge Wu };
9485a1f21b1SBridge Wu 
9495a1f21b1SBridge Wu struct platform_device pxa3xx_device_mci3 = {
9505a1f21b1SBridge Wu 	.name		= "pxa2xx-mci",
9515a1f21b1SBridge Wu 	.id		= 2,
9525a1f21b1SBridge Wu 	.dev		= {
9535a1f21b1SBridge Wu 		.dma_mask = &pxamci_dmamask,
9545a1f21b1SBridge Wu 		.coherent_dma_mask = 0xffffffff,
9555a1f21b1SBridge Wu 	},
9565a1f21b1SBridge Wu 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_mci3),
9575a1f21b1SBridge Wu 	.resource	= pxa3xx_resources_mci3,
9585a1f21b1SBridge Wu };
9595a1f21b1SBridge Wu 
9605a1f21b1SBridge Wu void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
9615a1f21b1SBridge Wu {
9625a1f21b1SBridge Wu 	pxa_register_device(&pxa3xx_device_mci3, info);
9635a1f21b1SBridge Wu }
9645a1f21b1SBridge Wu 
965a4553358SHaojian Zhuang static struct resource pxa3xx_resources_gcu[] = {
966a4553358SHaojian Zhuang 	{
967a4553358SHaojian Zhuang 		.start	= 0x54000000,
968a4553358SHaojian Zhuang 		.end	= 0x54000fff,
969a4553358SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
970a4553358SHaojian Zhuang 	},
971a4553358SHaojian Zhuang 	{
972a4553358SHaojian Zhuang 		.start	= IRQ_GCU,
973a4553358SHaojian Zhuang 		.end	= IRQ_GCU,
974a4553358SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
975a4553358SHaojian Zhuang 	},
976a4553358SHaojian Zhuang };
977a4553358SHaojian Zhuang 
978a4553358SHaojian Zhuang static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
979a4553358SHaojian Zhuang 
980a4553358SHaojian Zhuang struct platform_device pxa3xx_device_gcu = {
981a4553358SHaojian Zhuang 	.name		= "pxa3xx-gcu",
982a4553358SHaojian Zhuang 	.id		= -1,
983a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_gcu),
984a4553358SHaojian Zhuang 	.resource	= pxa3xx_resources_gcu,
985a4553358SHaojian Zhuang 	.dev		= {
986a4553358SHaojian Zhuang 		.dma_mask = &pxa3xx_gcu_dmamask,
987a4553358SHaojian Zhuang 		.coherent_dma_mask = 0xffffffff,
988a4553358SHaojian Zhuang 	},
989a4553358SHaojian Zhuang };
990a4553358SHaojian Zhuang 
991a4553358SHaojian Zhuang #endif /* CONFIG_PXA3xx */
992a4553358SHaojian Zhuang 
99349ea7fc0SHaojian Zhuang #if defined(CONFIG_PXA3xx)
994a4553358SHaojian Zhuang static struct resource pxa3xx_resources_i2c_power[] = {
995a4553358SHaojian Zhuang 	{
996a4553358SHaojian Zhuang 		.start  = 0x40f500c0,
997a4553358SHaojian Zhuang 		.end    = 0x40f500d3,
998a4553358SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
999a4553358SHaojian Zhuang 	}, {
1000a4553358SHaojian Zhuang 		.start	= IRQ_PWRI2C,
1001a4553358SHaojian Zhuang 		.end	= IRQ_PWRI2C,
1002a4553358SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1003a4553358SHaojian Zhuang 	},
1004a4553358SHaojian Zhuang };
1005a4553358SHaojian Zhuang 
1006a4553358SHaojian Zhuang struct platform_device pxa3xx_device_i2c_power = {
1007a4553358SHaojian Zhuang 	.name		= "pxa3xx-pwri2c",
1008a4553358SHaojian Zhuang 	.id		= 1,
1009a4553358SHaojian Zhuang 	.resource	= pxa3xx_resources_i2c_power,
1010a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_i2c_power),
1011a4553358SHaojian Zhuang };
1012a4553358SHaojian Zhuang 
10139ae819a8SEric Miao static struct resource pxa3xx_resources_nand[] = {
10149ae819a8SEric Miao 	[0] = {
10159ae819a8SEric Miao 		.start	= 0x43100000,
10169ae819a8SEric Miao 		.end	= 0x43100053,
10179ae819a8SEric Miao 		.flags	= IORESOURCE_MEM,
10189ae819a8SEric Miao 	},
10199ae819a8SEric Miao 	[1] = {
10209ae819a8SEric Miao 		.start	= IRQ_NAND,
10219ae819a8SEric Miao 		.end	= IRQ_NAND,
10229ae819a8SEric Miao 		.flags	= IORESOURCE_IRQ,
10239ae819a8SEric Miao 	},
10249ae819a8SEric Miao 	[2] = {
10259ae819a8SEric Miao 		/* DRCMR for Data DMA */
10269ae819a8SEric Miao 		.start	= 97,
10279ae819a8SEric Miao 		.end	= 97,
10289ae819a8SEric Miao 		.flags	= IORESOURCE_DMA,
10299ae819a8SEric Miao 	},
10309ae819a8SEric Miao 	[3] = {
10319ae819a8SEric Miao 		/* DRCMR for Command DMA */
10329ae819a8SEric Miao 		.start	= 99,
10339ae819a8SEric Miao 		.end	= 99,
10349ae819a8SEric Miao 		.flags	= IORESOURCE_DMA,
10359ae819a8SEric Miao 	},
10369ae819a8SEric Miao };
10379ae819a8SEric Miao 
10389ae819a8SEric Miao static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
10399ae819a8SEric Miao 
10409ae819a8SEric Miao struct platform_device pxa3xx_device_nand = {
10419ae819a8SEric Miao 	.name		= "pxa3xx-nand",
10429ae819a8SEric Miao 	.id		= -1,
10439ae819a8SEric Miao 	.dev		= {
10449ae819a8SEric Miao 		.dma_mask = &pxa3xx_nand_dma_mask,
10459ae819a8SEric Miao 		.coherent_dma_mask = DMA_BIT_MASK(32),
10469ae819a8SEric Miao 	},
10479ae819a8SEric Miao 	.num_resources	= ARRAY_SIZE(pxa3xx_resources_nand),
10489ae819a8SEric Miao 	.resource	= pxa3xx_resources_nand,
10499ae819a8SEric Miao };
10509ae819a8SEric Miao 
10519ae819a8SEric Miao void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
10529ae819a8SEric Miao {
10539ae819a8SEric Miao 	pxa_register_device(&pxa3xx_device_nand, info);
10549ae819a8SEric Miao }
10551ff2c33eSDaniel Mack 
1056a4553358SHaojian Zhuang static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
1057a4553358SHaojian Zhuang 
1058a4553358SHaojian Zhuang static struct resource pxa3xx_resource_ssp4[] = {
1059a4553358SHaojian Zhuang 	[0] = {
1060a4553358SHaojian Zhuang 		.start	= 0x41a00000,
1061a4553358SHaojian Zhuang 		.end	= 0x41a0003f,
10621ff2c33eSDaniel Mack 		.flags	= IORESOURCE_MEM,
10631ff2c33eSDaniel Mack 	},
1064a4553358SHaojian Zhuang 	[1] = {
1065a4553358SHaojian Zhuang 		.start	= IRQ_SSP4,
1066a4553358SHaojian Zhuang 		.end	= IRQ_SSP4,
10671ff2c33eSDaniel Mack 		.flags	= IORESOURCE_IRQ,
10681ff2c33eSDaniel Mack 	},
1069a4553358SHaojian Zhuang 	[2] = {
1070a4553358SHaojian Zhuang 		/* DRCMR for RX */
1071a4553358SHaojian Zhuang 		.start	= 2,
1072a4553358SHaojian Zhuang 		.end	= 2,
1073a4553358SHaojian Zhuang 		.flags	= IORESOURCE_DMA,
1074a4553358SHaojian Zhuang 	},
1075a4553358SHaojian Zhuang 	[3] = {
1076a4553358SHaojian Zhuang 		/* DRCMR for TX */
1077a4553358SHaojian Zhuang 		.start	= 3,
1078a4553358SHaojian Zhuang 		.end	= 3,
1079a4553358SHaojian Zhuang 		.flags	= IORESOURCE_DMA,
10801ff2c33eSDaniel Mack 	},
10811ff2c33eSDaniel Mack };
10821ff2c33eSDaniel Mack 
10830da0e227SDaniel Mack /*
10840da0e227SDaniel Mack  * PXA3xx SSP is basically equivalent to PXA27x.
10850da0e227SDaniel Mack  * However, we need to register the device by the correct name in order to
10860da0e227SDaniel Mack  * make the driver set the correct internal type, hence we provide specific
10870da0e227SDaniel Mack  * platform_devices for each of them.
10880da0e227SDaniel Mack  */
10890da0e227SDaniel Mack struct platform_device pxa3xx_device_ssp1 = {
10900da0e227SDaniel Mack 	.name		= "pxa3xx-ssp",
10910da0e227SDaniel Mack 	.id		= 0,
10920da0e227SDaniel Mack 	.dev		= {
10930da0e227SDaniel Mack 		.dma_mask = &pxa27x_ssp1_dma_mask,
10940da0e227SDaniel Mack 		.coherent_dma_mask = DMA_BIT_MASK(32),
10950da0e227SDaniel Mack 	},
10960da0e227SDaniel Mack 	.resource	= pxa27x_resource_ssp1,
10970da0e227SDaniel Mack 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
10980da0e227SDaniel Mack };
10990da0e227SDaniel Mack 
11000da0e227SDaniel Mack struct platform_device pxa3xx_device_ssp2 = {
11010da0e227SDaniel Mack 	.name		= "pxa3xx-ssp",
11020da0e227SDaniel Mack 	.id		= 1,
11030da0e227SDaniel Mack 	.dev		= {
11040da0e227SDaniel Mack 		.dma_mask = &pxa27x_ssp2_dma_mask,
11050da0e227SDaniel Mack 		.coherent_dma_mask = DMA_BIT_MASK(32),
11060da0e227SDaniel Mack 	},
11070da0e227SDaniel Mack 	.resource	= pxa27x_resource_ssp2,
11080da0e227SDaniel Mack 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
11090da0e227SDaniel Mack };
11100da0e227SDaniel Mack 
11110da0e227SDaniel Mack struct platform_device pxa3xx_device_ssp3 = {
11120da0e227SDaniel Mack 	.name		= "pxa3xx-ssp",
11130da0e227SDaniel Mack 	.id		= 2,
11140da0e227SDaniel Mack 	.dev		= {
11150da0e227SDaniel Mack 		.dma_mask = &pxa27x_ssp3_dma_mask,
11160da0e227SDaniel Mack 		.coherent_dma_mask = DMA_BIT_MASK(32),
11170da0e227SDaniel Mack 	},
11180da0e227SDaniel Mack 	.resource	= pxa27x_resource_ssp3,
11190da0e227SDaniel Mack 	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
11200da0e227SDaniel Mack };
11210da0e227SDaniel Mack 
1122a4553358SHaojian Zhuang struct platform_device pxa3xx_device_ssp4 = {
11230da0e227SDaniel Mack 	.name		= "pxa3xx-ssp",
1124a4553358SHaojian Zhuang 	.id		= 3,
1125a4553358SHaojian Zhuang 	.dev		= {
1126a4553358SHaojian Zhuang 		.dma_mask = &pxa3xx_ssp4_dma_mask,
1127a4553358SHaojian Zhuang 		.coherent_dma_mask = DMA_BIT_MASK(32),
1128a4553358SHaojian Zhuang 	},
1129a4553358SHaojian Zhuang 	.resource	= pxa3xx_resource_ssp4,
1130a4553358SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa3xx_resource_ssp4),
1131a4553358SHaojian Zhuang };
113249ea7fc0SHaojian Zhuang #endif /* CONFIG_PXA3xx */
1133e172274cSGuennadi Liakhovetski 
1134157d2644SHaojian Zhuang struct resource pxa_resource_gpio[] = {
1135157d2644SHaojian Zhuang 	{
1136157d2644SHaojian Zhuang 		.start	= 0x40e00000,
1137157d2644SHaojian Zhuang 		.end	= 0x40e0ffff,
1138157d2644SHaojian Zhuang 		.flags	= IORESOURCE_MEM,
1139157d2644SHaojian Zhuang 	}, {
1140157d2644SHaojian Zhuang 		.start	= IRQ_GPIO0,
1141157d2644SHaojian Zhuang 		.end	= IRQ_GPIO0,
1142157d2644SHaojian Zhuang 		.name	= "gpio0",
1143157d2644SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1144157d2644SHaojian Zhuang 	}, {
1145157d2644SHaojian Zhuang 		.start	= IRQ_GPIO1,
1146157d2644SHaojian Zhuang 		.end	= IRQ_GPIO1,
1147157d2644SHaojian Zhuang 		.name	= "gpio1",
1148157d2644SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1149157d2644SHaojian Zhuang 	}, {
1150157d2644SHaojian Zhuang 		.start	= IRQ_GPIO_2_x,
1151157d2644SHaojian Zhuang 		.end	= IRQ_GPIO_2_x,
1152157d2644SHaojian Zhuang 		.name	= "gpio_mux",
1153157d2644SHaojian Zhuang 		.flags	= IORESOURCE_IRQ,
1154157d2644SHaojian Zhuang 	},
1155157d2644SHaojian Zhuang };
1156157d2644SHaojian Zhuang 
11572cab0292SHaojian Zhuang struct platform_device pxa25x_device_gpio = {
11582cab0292SHaojian Zhuang #ifdef CONFIG_CPU_PXA26x
11592cab0292SHaojian Zhuang 	.name		= "pxa26x-gpio",
11602cab0292SHaojian Zhuang #else
11612cab0292SHaojian Zhuang 	.name		= "pxa25x-gpio",
11622cab0292SHaojian Zhuang #endif
11632cab0292SHaojian Zhuang 	.id		= -1,
11642cab0292SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa_resource_gpio),
11652cab0292SHaojian Zhuang 	.resource	= pxa_resource_gpio,
11662cab0292SHaojian Zhuang };
11672cab0292SHaojian Zhuang 
11682cab0292SHaojian Zhuang struct platform_device pxa27x_device_gpio = {
11692cab0292SHaojian Zhuang 	.name		= "pxa27x-gpio",
11702cab0292SHaojian Zhuang 	.id		= -1,
11712cab0292SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa_resource_gpio),
11722cab0292SHaojian Zhuang 	.resource	= pxa_resource_gpio,
11732cab0292SHaojian Zhuang };
11742cab0292SHaojian Zhuang 
11752cab0292SHaojian Zhuang struct platform_device pxa3xx_device_gpio = {
11762cab0292SHaojian Zhuang 	.name		= "pxa3xx-gpio",
11772cab0292SHaojian Zhuang 	.id		= -1,
11782cab0292SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa_resource_gpio),
11792cab0292SHaojian Zhuang 	.resource	= pxa_resource_gpio,
11802cab0292SHaojian Zhuang };
11812cab0292SHaojian Zhuang 
11822cab0292SHaojian Zhuang struct platform_device pxa93x_device_gpio = {
11832cab0292SHaojian Zhuang 	.name		= "pxa93x-gpio",
1184157d2644SHaojian Zhuang 	.id		= -1,
1185157d2644SHaojian Zhuang 	.num_resources	= ARRAY_SIZE(pxa_resource_gpio),
1186157d2644SHaojian Zhuang 	.resource	= pxa_resource_gpio,
1187157d2644SHaojian Zhuang };
1188157d2644SHaojian Zhuang 
1189e172274cSGuennadi Liakhovetski /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
1190e172274cSGuennadi Liakhovetski  * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
1191e172274cSGuennadi Liakhovetski void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
1192e172274cSGuennadi Liakhovetski {
1193e172274cSGuennadi Liakhovetski 	struct platform_device *pd;
1194e172274cSGuennadi Liakhovetski 
1195e172274cSGuennadi Liakhovetski 	pd = platform_device_alloc("pxa2xx-spi", id);
1196e172274cSGuennadi Liakhovetski 	if (pd == NULL) {
1197e172274cSGuennadi Liakhovetski 		printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
1198e172274cSGuennadi Liakhovetski 		       id);
1199e172274cSGuennadi Liakhovetski 		return;
1200e172274cSGuennadi Liakhovetski 	}
1201e172274cSGuennadi Liakhovetski 
1202e172274cSGuennadi Liakhovetski 	pd->dev.platform_data = info;
1203e172274cSGuennadi Liakhovetski 	platform_device_add(pd);
1204e172274cSGuennadi Liakhovetski }
12054be0856fSRobert Jarzmik 
12064be0856fSRobert Jarzmik static struct resource pxa_dma_resource[] = {
12074be0856fSRobert Jarzmik 	[0] = {
12084be0856fSRobert Jarzmik 		.start	= 0x40000000,
12094be0856fSRobert Jarzmik 		.end	= 0x4000ffff,
12104be0856fSRobert Jarzmik 		.flags	= IORESOURCE_MEM,
12114be0856fSRobert Jarzmik 	},
12124be0856fSRobert Jarzmik 	[1] = {
12134be0856fSRobert Jarzmik 		.start	= IRQ_DMA,
12144be0856fSRobert Jarzmik 		.end	= IRQ_DMA,
12154be0856fSRobert Jarzmik 		.flags	= IORESOURCE_IRQ,
12164be0856fSRobert Jarzmik 	},
12174be0856fSRobert Jarzmik };
12184be0856fSRobert Jarzmik 
12194be0856fSRobert Jarzmik static u64 pxadma_dmamask = 0xffffffffUL;
12204be0856fSRobert Jarzmik 
12214be0856fSRobert Jarzmik static struct platform_device pxa2xx_pxa_dma = {
12224be0856fSRobert Jarzmik 	.name		= "pxa-dma",
12234be0856fSRobert Jarzmik 	.id		= 0,
12244be0856fSRobert Jarzmik 	.dev		= {
12254be0856fSRobert Jarzmik 		.dma_mask = &pxadma_dmamask,
12264be0856fSRobert Jarzmik 		.coherent_dma_mask = 0xffffffff,
12274be0856fSRobert Jarzmik 	},
12284be0856fSRobert Jarzmik 	.num_resources	= ARRAY_SIZE(pxa_dma_resource),
12294be0856fSRobert Jarzmik 	.resource	= pxa_dma_resource,
12304be0856fSRobert Jarzmik };
12314be0856fSRobert Jarzmik 
1232*1da10c17SRobert Jarzmik void __init pxa2xx_set_dmac_info(struct mmp_dma_platdata *dma_pdata)
12334be0856fSRobert Jarzmik {
1234*1da10c17SRobert Jarzmik 	pxa_register_device(&pxa2xx_pxa_dma, dma_pdata);
12354be0856fSRobert Jarzmik }
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