xref: /linux/arch/arm/mach-orion5x/pci.c (revision 0d456bad36d42d16022be045c8a53ddbb59ee478) 
1 /*
2  * arch/arm/mach-orion5x/pci.c
3  *
4  * PCI and PCIe functions for Marvell Orion System On Chip
5  *
6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2.  This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/mbus.h>
17 #include <video/vga.h>
18 #include <asm/irq.h>
19 #include <asm/mach/pci.h>
20 #include <plat/pcie.h>
21 #include <plat/addr-map.h>
22 #include <mach/orion5x.h>
23 #include "common.h"
24 
25 /*****************************************************************************
26  * Orion has one PCIe controller and one PCI controller.
27  *
28  * Note1: The local PCIe bus number is '0'. The local PCI bus number
29  * follows the scanned PCIe bridged busses, if any.
30  *
31  * Note2: It is possible for PCI/PCIe agents to access many subsystem's
32  * space, by configuring BARs and Address Decode Windows, e.g. flashes on
33  * device bus, Orion registers, etc. However this code only enable the
34  * access to DDR banks.
35  ****************************************************************************/
36 
37 
38 /*****************************************************************************
39  * PCIe controller
40  ****************************************************************************/
41 #define PCIE_BASE	(ORION5X_PCIE_VIRT_BASE)
42 
43 void __init orion5x_pcie_id(u32 *dev, u32 *rev)
44 {
45 	*dev = orion_pcie_dev_id(PCIE_BASE);
46 	*rev = orion_pcie_rev(PCIE_BASE);
47 }
48 
49 static int pcie_valid_config(int bus, int dev)
50 {
51 	/*
52 	 * Don't go out when trying to access --
53 	 * 1. nonexisting device on local bus
54 	 * 2. where there's no device connected (no link)
55 	 */
56 	if (bus == 0 && dev == 0)
57 		return 1;
58 
59 	if (!orion_pcie_link_up(PCIE_BASE))
60 		return 0;
61 
62 	if (bus == 0 && dev != 1)
63 		return 0;
64 
65 	return 1;
66 }
67 
68 
69 /*
70  * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
71  * and then reading the PCIE_CONF_DATA register. Need to make sure these
72  * transactions are atomic.
73  */
74 static DEFINE_SPINLOCK(orion5x_pcie_lock);
75 
76 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
77 			int size, u32 *val)
78 {
79 	unsigned long flags;
80 	int ret;
81 
82 	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
83 		*val = 0xffffffff;
84 		return PCIBIOS_DEVICE_NOT_FOUND;
85 	}
86 
87 	spin_lock_irqsave(&orion5x_pcie_lock, flags);
88 	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
89 	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
90 
91 	return ret;
92 }
93 
94 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
95 			   int where, int size, u32 *val)
96 {
97 	int ret;
98 
99 	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
100 		*val = 0xffffffff;
101 		return PCIBIOS_DEVICE_NOT_FOUND;
102 	}
103 
104 	/*
105 	 * We only support access to the non-extended configuration
106 	 * space when using the WA access method (or we would have to
107 	 * sacrifice 256M of CPU virtual address space.)
108 	 */
109 	if (where >= 0x100) {
110 		*val = 0xffffffff;
111 		return PCIBIOS_DEVICE_NOT_FOUND;
112 	}
113 
114 	ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
115 				    bus, devfn, where, size, val);
116 
117 	return ret;
118 }
119 
120 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
121 			int where, int size, u32 val)
122 {
123 	unsigned long flags;
124 	int ret;
125 
126 	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
127 		return PCIBIOS_DEVICE_NOT_FOUND;
128 
129 	spin_lock_irqsave(&orion5x_pcie_lock, flags);
130 	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
131 	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
132 
133 	return ret;
134 }
135 
136 static struct pci_ops pcie_ops = {
137 	.read = pcie_rd_conf,
138 	.write = pcie_wr_conf,
139 };
140 
141 
142 static int __init pcie_setup(struct pci_sys_data *sys)
143 {
144 	struct resource *res;
145 	int dev;
146 
147 	/*
148 	 * Generic PCIe unit setup.
149 	 */
150 	orion_pcie_setup(PCIE_BASE);
151 
152 	/*
153 	 * Check whether to apply Orion-1/Orion-NAS PCIe config
154 	 * read transaction workaround.
155 	 */
156 	dev = orion_pcie_dev_id(PCIE_BASE);
157 	if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
158 		printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
159 				   "read transaction workaround\n");
160 		orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
161 					  ORION5X_PCIE_WA_SIZE);
162 		pcie_ops.read = pcie_rd_conf_wa;
163 	}
164 
165 	pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
166 
167 	/*
168 	 * Request resources.
169 	 */
170 	res = kzalloc(sizeof(struct resource), GFP_KERNEL);
171 	if (!res)
172 		panic("pcie_setup unable to alloc resources");
173 
174 	/*
175 	 * IORESOURCE_MEM
176 	 */
177 	res->name = "PCIe Memory Space";
178 	res->flags = IORESOURCE_MEM;
179 	res->start = ORION5X_PCIE_MEM_PHYS_BASE;
180 	res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
181 	if (request_resource(&iomem_resource, res))
182 		panic("Request PCIe Memory resource failed\n");
183 	pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
184 
185 	return 1;
186 }
187 
188 /*****************************************************************************
189  * PCI controller
190  ****************************************************************************/
191 #define ORION5X_PCI_REG(x)	(ORION5X_PCI_VIRT_BASE + (x))
192 #define PCI_MODE		ORION5X_PCI_REG(0xd00)
193 #define PCI_CMD			ORION5X_PCI_REG(0xc00)
194 #define PCI_P2P_CONF		ORION5X_PCI_REG(0x1d14)
195 #define PCI_CONF_ADDR		ORION5X_PCI_REG(0xc78)
196 #define PCI_CONF_DATA		ORION5X_PCI_REG(0xc7c)
197 
198 /*
199  * PCI_MODE bits
200  */
201 #define PCI_MODE_64BIT			(1 << 2)
202 #define PCI_MODE_PCIX			((1 << 4) | (1 << 5))
203 
204 /*
205  * PCI_CMD bits
206  */
207 #define PCI_CMD_HOST_REORDER		(1 << 29)
208 
209 /*
210  * PCI_P2P_CONF bits
211  */
212 #define PCI_P2P_BUS_OFFS		16
213 #define PCI_P2P_BUS_MASK		(0xff << PCI_P2P_BUS_OFFS)
214 #define PCI_P2P_DEV_OFFS		24
215 #define PCI_P2P_DEV_MASK		(0x1f << PCI_P2P_DEV_OFFS)
216 
217 /*
218  * PCI_CONF_ADDR bits
219  */
220 #define PCI_CONF_REG(reg)		((reg) & 0xfc)
221 #define PCI_CONF_FUNC(func)		(((func) & 0x3) << 8)
222 #define PCI_CONF_DEV(dev)		(((dev) & 0x1f) << 11)
223 #define PCI_CONF_BUS(bus)		(((bus) & 0xff) << 16)
224 #define PCI_CONF_ADDR_EN		(1 << 31)
225 
226 /*
227  * Internal configuration space
228  */
229 #define PCI_CONF_FUNC_STAT_CMD		0
230 #define PCI_CONF_REG_STAT_CMD		4
231 #define PCIX_STAT			0x64
232 #define PCIX_STAT_BUS_OFFS		8
233 #define PCIX_STAT_BUS_MASK		(0xff << PCIX_STAT_BUS_OFFS)
234 
235 /*
236  * PCI Address Decode Windows registers
237  */
238 #define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
239 				 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
240 				 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
241 				 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
242 #define PCI_BAR_REMAP_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
243 				 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
244 				 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
245 				 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
246 #define PCI_BAR_ENABLE		ORION5X_PCI_REG(0xc3c)
247 #define PCI_ADDR_DECODE_CTRL	ORION5X_PCI_REG(0xd3c)
248 
249 /*
250  * PCI configuration helpers for BAR settings
251  */
252 #define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
253 #define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
254 #define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)
255 
256 /*
257  * PCI config cycles are done by programming the PCI_CONF_ADDR register
258  * and then reading the PCI_CONF_DATA register. Need to make sure these
259  * transactions are atomic.
260  */
261 static DEFINE_SPINLOCK(orion5x_pci_lock);
262 
263 static int orion5x_pci_cardbus_mode;
264 
265 static int orion5x_pci_local_bus_nr(void)
266 {
267 	u32 conf = readl(PCI_P2P_CONF);
268 	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
269 }
270 
271 static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
272 					u32 where, u32 size, u32 *val)
273 {
274 	unsigned long flags;
275 	spin_lock_irqsave(&orion5x_pci_lock, flags);
276 
277 	writel(PCI_CONF_BUS(bus) |
278 		PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
279 		PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
280 
281 	*val = readl(PCI_CONF_DATA);
282 
283 	if (size == 1)
284 		*val = (*val >> (8*(where & 0x3))) & 0xff;
285 	else if (size == 2)
286 		*val = (*val >> (8*(where & 0x3))) & 0xffff;
287 
288 	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
289 
290 	return PCIBIOS_SUCCESSFUL;
291 }
292 
293 static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
294 					u32 where, u32 size, u32 val)
295 {
296 	unsigned long flags;
297 	int ret = PCIBIOS_SUCCESSFUL;
298 
299 	spin_lock_irqsave(&orion5x_pci_lock, flags);
300 
301 	writel(PCI_CONF_BUS(bus) |
302 		PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
303 		PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
304 
305 	if (size == 4) {
306 		__raw_writel(val, PCI_CONF_DATA);
307 	} else if (size == 2) {
308 		__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
309 	} else if (size == 1) {
310 		__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
311 	} else {
312 		ret = PCIBIOS_BAD_REGISTER_NUMBER;
313 	}
314 
315 	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
316 
317 	return ret;
318 }
319 
320 static int orion5x_pci_valid_config(int bus, u32 devfn)
321 {
322 	if (bus == orion5x_pci_local_bus_nr()) {
323 		/*
324 		 * Don't go out for local device
325 		 */
326 		if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
327 			return 0;
328 
329 		/*
330 		 * When the PCI signals are directly connected to a
331 		 * Cardbus slot, ignore all but device IDs 0 and 1.
332 		 */
333 		if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
334 			return 0;
335 	}
336 
337 	return 1;
338 }
339 
340 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
341 				int where, int size, u32 *val)
342 {
343 	if (!orion5x_pci_valid_config(bus->number, devfn)) {
344 		*val = 0xffffffff;
345 		return PCIBIOS_DEVICE_NOT_FOUND;
346 	}
347 
348 	return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
349 					PCI_FUNC(devfn), where, size, val);
350 }
351 
352 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
353 				int where, int size, u32 val)
354 {
355 	if (!orion5x_pci_valid_config(bus->number, devfn))
356 		return PCIBIOS_DEVICE_NOT_FOUND;
357 
358 	return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
359 					PCI_FUNC(devfn), where, size, val);
360 }
361 
362 static struct pci_ops pci_ops = {
363 	.read = orion5x_pci_rd_conf,
364 	.write = orion5x_pci_wr_conf,
365 };
366 
367 static void __init orion5x_pci_set_bus_nr(int nr)
368 {
369 	u32 p2p = readl(PCI_P2P_CONF);
370 
371 	if (readl(PCI_MODE) & PCI_MODE_PCIX) {
372 		/*
373 		 * PCI-X mode
374 		 */
375 		u32 pcix_status, bus, dev;
376 		bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
377 		dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
378 		orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
379 		pcix_status &= ~PCIX_STAT_BUS_MASK;
380 		pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
381 		orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
382 	} else {
383 		/*
384 		 * PCI Conventional mode
385 		 */
386 		p2p &= ~PCI_P2P_BUS_MASK;
387 		p2p |= (nr << PCI_P2P_BUS_OFFS);
388 		writel(p2p, PCI_P2P_CONF);
389 	}
390 }
391 
392 static void __init orion5x_pci_master_slave_enable(void)
393 {
394 	int bus_nr, func, reg;
395 	u32 val;
396 
397 	bus_nr = orion5x_pci_local_bus_nr();
398 	func = PCI_CONF_FUNC_STAT_CMD;
399 	reg = PCI_CONF_REG_STAT_CMD;
400 	orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
401 	val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
402 	orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
403 }
404 
405 static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
406 {
407 	u32 win_enable;
408 	int bus;
409 	int i;
410 
411 	/*
412 	 * First, disable windows.
413 	 */
414 	win_enable = 0xffffffff;
415 	writel(win_enable, PCI_BAR_ENABLE);
416 
417 	/*
418 	 * Setup windows for DDR banks.
419 	 */
420 	bus = orion5x_pci_local_bus_nr();
421 
422 	for (i = 0; i < dram->num_cs; i++) {
423 		struct mbus_dram_window *cs = dram->cs + i;
424 		u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
425 		u32 reg;
426 		u32 val;
427 
428 		/*
429 		 * Write DRAM bank base address register.
430 		 */
431 		reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
432 		orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
433 		val = (cs->base & 0xfffff000) | (val & 0xfff);
434 		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
435 
436 		/*
437 		 * Write DRAM bank size register.
438 		 */
439 		reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
440 		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
441 		writel((cs->size - 1) & 0xfffff000,
442 			PCI_BAR_SIZE_DDR_CS(cs->cs_index));
443 		writel(cs->base & 0xfffff000,
444 			PCI_BAR_REMAP_DDR_CS(cs->cs_index));
445 
446 		/*
447 		 * Enable decode window for this chip select.
448 		 */
449 		win_enable &= ~(1 << cs->cs_index);
450 	}
451 
452 	/*
453 	 * Re-enable decode windows.
454 	 */
455 	writel(win_enable, PCI_BAR_ENABLE);
456 
457 	/*
458 	 * Disable automatic update of address remapping when writing to BARs.
459 	 */
460 	orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
461 }
462 
463 static int __init pci_setup(struct pci_sys_data *sys)
464 {
465 	struct resource *res;
466 
467 	/*
468 	 * Point PCI unit MBUS decode windows to DRAM space.
469 	 */
470 	orion5x_setup_pci_wins(&orion_mbus_dram_info);
471 
472 	/*
473 	 * Master + Slave enable
474 	 */
475 	orion5x_pci_master_slave_enable();
476 
477 	/*
478 	 * Force ordering
479 	 */
480 	orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
481 
482 	pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
483 
484 	/*
485 	 * Request resources
486 	 */
487 	res = kzalloc(sizeof(struct resource), GFP_KERNEL);
488 	if (!res)
489 		panic("pci_setup unable to alloc resources");
490 
491 	/*
492 	 * IORESOURCE_MEM
493 	 */
494 	res->name = "PCI Memory Space";
495 	res->flags = IORESOURCE_MEM;
496 	res->start = ORION5X_PCI_MEM_PHYS_BASE;
497 	res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
498 	if (request_resource(&iomem_resource, res))
499 		panic("Request PCI Memory resource failed\n");
500 	pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
501 
502 	return 1;
503 }
504 
505 
506 /*****************************************************************************
507  * General PCIe + PCI
508  ****************************************************************************/
509 static void __devinit rc_pci_fixup(struct pci_dev *dev)
510 {
511 	/*
512 	 * Prevent enumeration of root complex.
513 	 */
514 	if (dev->bus->parent == NULL && dev->devfn == 0) {
515 		int i;
516 
517 		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
518 			dev->resource[i].start = 0;
519 			dev->resource[i].end   = 0;
520 			dev->resource[i].flags = 0;
521 		}
522 	}
523 }
524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
525 
526 static int orion5x_pci_disabled __initdata;
527 
528 void __init orion5x_pci_disable(void)
529 {
530 	orion5x_pci_disabled = 1;
531 }
532 
533 void __init orion5x_pci_set_cardbus_mode(void)
534 {
535 	orion5x_pci_cardbus_mode = 1;
536 }
537 
538 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
539 {
540 	int ret = 0;
541 
542 	vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
543 
544 	if (nr == 0) {
545 		orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
546 		ret = pcie_setup(sys);
547 	} else if (nr == 1 && !orion5x_pci_disabled) {
548 		orion5x_pci_set_bus_nr(sys->busnr);
549 		ret = pci_setup(sys);
550 	}
551 
552 	return ret;
553 }
554 
555 struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
556 {
557 	struct pci_bus *bus;
558 
559 	if (nr == 0) {
560 		bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
561 					&sys->resources);
562 	} else if (nr == 1 && !orion5x_pci_disabled) {
563 		bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys,
564 					&sys->resources);
565 	} else {
566 		bus = NULL;
567 		BUG();
568 	}
569 
570 	return bus;
571 }
572 
573 int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
574 {
575 	int bus = dev->bus->number;
576 
577 	/*
578 	 * PCIe endpoint?
579 	 */
580 	if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
581 		return IRQ_ORION5X_PCIE0_INT;
582 
583 	return -1;
584 }
585