1*c22c2c60SArnd Bergmann /* 2*c22c2c60SArnd Bergmann * IRQ definitions for Orion SoC 3*c22c2c60SArnd Bergmann * 4*c22c2c60SArnd Bergmann * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 5*c22c2c60SArnd Bergmann * 6*c22c2c60SArnd Bergmann * This file is licensed under the terms of the GNU General Public 7*c22c2c60SArnd Bergmann * License version 2. This program is licensed "as is" without any 8*c22c2c60SArnd Bergmann * warranty of any kind, whether express or implied. 9*c22c2c60SArnd Bergmann */ 10*c22c2c60SArnd Bergmann 11*c22c2c60SArnd Bergmann #ifndef __ASM_ARCH_IRQS_H 12*c22c2c60SArnd Bergmann #define __ASM_ARCH_IRQS_H 13*c22c2c60SArnd Bergmann 14*c22c2c60SArnd Bergmann /* 15*c22c2c60SArnd Bergmann * Orion Main Interrupt Controller 16*c22c2c60SArnd Bergmann */ 17*c22c2c60SArnd Bergmann #define IRQ_ORION5X_BRIDGE (1 + 0) 18*c22c2c60SArnd Bergmann #define IRQ_ORION5X_DOORBELL_H2C (1 + 1) 19*c22c2c60SArnd Bergmann #define IRQ_ORION5X_DOORBELL_C2H (1 + 2) 20*c22c2c60SArnd Bergmann #define IRQ_ORION5X_UART0 (1 + 3) 21*c22c2c60SArnd Bergmann #define IRQ_ORION5X_UART1 (1 + 4) 22*c22c2c60SArnd Bergmann #define IRQ_ORION5X_I2C (1 + 5) 23*c22c2c60SArnd Bergmann #define IRQ_ORION5X_GPIO_0_7 (1 + 6) 24*c22c2c60SArnd Bergmann #define IRQ_ORION5X_GPIO_8_15 (1 + 7) 25*c22c2c60SArnd Bergmann #define IRQ_ORION5X_GPIO_16_23 (1 + 8) 26*c22c2c60SArnd Bergmann #define IRQ_ORION5X_GPIO_24_31 (1 + 9) 27*c22c2c60SArnd Bergmann #define IRQ_ORION5X_PCIE0_ERR (1 + 10) 28*c22c2c60SArnd Bergmann #define IRQ_ORION5X_PCIE0_INT (1 + 11) 29*c22c2c60SArnd Bergmann #define IRQ_ORION5X_USB1_CTRL (1 + 12) 30*c22c2c60SArnd Bergmann #define IRQ_ORION5X_DEV_BUS_ERR (1 + 14) 31*c22c2c60SArnd Bergmann #define IRQ_ORION5X_PCI_ERR (1 + 15) 32*c22c2c60SArnd Bergmann #define IRQ_ORION5X_USB_BR_ERR (1 + 16) 33*c22c2c60SArnd Bergmann #define IRQ_ORION5X_USB0_CTRL (1 + 17) 34*c22c2c60SArnd Bergmann #define IRQ_ORION5X_ETH_RX (1 + 18) 35*c22c2c60SArnd Bergmann #define IRQ_ORION5X_ETH_TX (1 + 19) 36*c22c2c60SArnd Bergmann #define IRQ_ORION5X_ETH_MISC (1 + 20) 37*c22c2c60SArnd Bergmann #define IRQ_ORION5X_ETH_SUM (1 + 21) 38*c22c2c60SArnd Bergmann #define IRQ_ORION5X_ETH_ERR (1 + 22) 39*c22c2c60SArnd Bergmann #define IRQ_ORION5X_IDMA_ERR (1 + 23) 40*c22c2c60SArnd Bergmann #define IRQ_ORION5X_IDMA_0 (1 + 24) 41*c22c2c60SArnd Bergmann #define IRQ_ORION5X_IDMA_1 (1 + 25) 42*c22c2c60SArnd Bergmann #define IRQ_ORION5X_IDMA_2 (1 + 26) 43*c22c2c60SArnd Bergmann #define IRQ_ORION5X_IDMA_3 (1 + 27) 44*c22c2c60SArnd Bergmann #define IRQ_ORION5X_CESA (1 + 28) 45*c22c2c60SArnd Bergmann #define IRQ_ORION5X_SATA (1 + 29) 46*c22c2c60SArnd Bergmann #define IRQ_ORION5X_XOR0 (1 + 30) 47*c22c2c60SArnd Bergmann #define IRQ_ORION5X_XOR1 (1 + 31) 48*c22c2c60SArnd Bergmann 49*c22c2c60SArnd Bergmann /* 50*c22c2c60SArnd Bergmann * Orion General Purpose Pins 51*c22c2c60SArnd Bergmann */ 52*c22c2c60SArnd Bergmann #define IRQ_ORION5X_GPIO_START 33 53*c22c2c60SArnd Bergmann #define NR_GPIO_IRQS 32 54*c22c2c60SArnd Bergmann 55*c22c2c60SArnd Bergmann #define ORION5X_NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) 56*c22c2c60SArnd Bergmann 57*c22c2c60SArnd Bergmann 58*c22c2c60SArnd Bergmann #endif 59