1*0fdebc5eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2c22c2c60SArnd Bergmann /* 3c22c2c60SArnd Bergmann * IRQ definitions for Orion SoC 4c22c2c60SArnd Bergmann * 5c22c2c60SArnd Bergmann * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 6c22c2c60SArnd Bergmann */ 7c22c2c60SArnd Bergmann 8c22c2c60SArnd Bergmann #ifndef __ASM_ARCH_IRQS_H 9c22c2c60SArnd Bergmann #define __ASM_ARCH_IRQS_H 10c22c2c60SArnd Bergmann 11c22c2c60SArnd Bergmann /* 12c22c2c60SArnd Bergmann * Orion Main Interrupt Controller 13c22c2c60SArnd Bergmann */ 14c22c2c60SArnd Bergmann #define IRQ_ORION5X_BRIDGE (1 + 0) 15c22c2c60SArnd Bergmann #define IRQ_ORION5X_DOORBELL_H2C (1 + 1) 16c22c2c60SArnd Bergmann #define IRQ_ORION5X_DOORBELL_C2H (1 + 2) 17c22c2c60SArnd Bergmann #define IRQ_ORION5X_UART0 (1 + 3) 18c22c2c60SArnd Bergmann #define IRQ_ORION5X_UART1 (1 + 4) 19c22c2c60SArnd Bergmann #define IRQ_ORION5X_I2C (1 + 5) 20c22c2c60SArnd Bergmann #define IRQ_ORION5X_GPIO_0_7 (1 + 6) 21c22c2c60SArnd Bergmann #define IRQ_ORION5X_GPIO_8_15 (1 + 7) 22c22c2c60SArnd Bergmann #define IRQ_ORION5X_GPIO_16_23 (1 + 8) 23c22c2c60SArnd Bergmann #define IRQ_ORION5X_GPIO_24_31 (1 + 9) 24c22c2c60SArnd Bergmann #define IRQ_ORION5X_PCIE0_ERR (1 + 10) 25c22c2c60SArnd Bergmann #define IRQ_ORION5X_PCIE0_INT (1 + 11) 26c22c2c60SArnd Bergmann #define IRQ_ORION5X_USB1_CTRL (1 + 12) 27c22c2c60SArnd Bergmann #define IRQ_ORION5X_DEV_BUS_ERR (1 + 14) 28c22c2c60SArnd Bergmann #define IRQ_ORION5X_PCI_ERR (1 + 15) 29c22c2c60SArnd Bergmann #define IRQ_ORION5X_USB_BR_ERR (1 + 16) 30c22c2c60SArnd Bergmann #define IRQ_ORION5X_USB0_CTRL (1 + 17) 31c22c2c60SArnd Bergmann #define IRQ_ORION5X_ETH_RX (1 + 18) 32c22c2c60SArnd Bergmann #define IRQ_ORION5X_ETH_TX (1 + 19) 33c22c2c60SArnd Bergmann #define IRQ_ORION5X_ETH_MISC (1 + 20) 34c22c2c60SArnd Bergmann #define IRQ_ORION5X_ETH_SUM (1 + 21) 35c22c2c60SArnd Bergmann #define IRQ_ORION5X_ETH_ERR (1 + 22) 36c22c2c60SArnd Bergmann #define IRQ_ORION5X_IDMA_ERR (1 + 23) 37c22c2c60SArnd Bergmann #define IRQ_ORION5X_IDMA_0 (1 + 24) 38c22c2c60SArnd Bergmann #define IRQ_ORION5X_IDMA_1 (1 + 25) 39c22c2c60SArnd Bergmann #define IRQ_ORION5X_IDMA_2 (1 + 26) 40c22c2c60SArnd Bergmann #define IRQ_ORION5X_IDMA_3 (1 + 27) 41c22c2c60SArnd Bergmann #define IRQ_ORION5X_CESA (1 + 28) 42c22c2c60SArnd Bergmann #define IRQ_ORION5X_SATA (1 + 29) 43c22c2c60SArnd Bergmann #define IRQ_ORION5X_XOR0 (1 + 30) 44c22c2c60SArnd Bergmann #define IRQ_ORION5X_XOR1 (1 + 31) 45c22c2c60SArnd Bergmann 46c22c2c60SArnd Bergmann /* 47c22c2c60SArnd Bergmann * Orion General Purpose Pins 48c22c2c60SArnd Bergmann */ 49c22c2c60SArnd Bergmann #define IRQ_ORION5X_GPIO_START 33 50c22c2c60SArnd Bergmann #define NR_GPIO_IRQS 32 51c22c2c60SArnd Bergmann 52c22c2c60SArnd Bergmann #define ORION5X_NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) 53c22c2c60SArnd Bergmann 54c22c2c60SArnd Bergmann 55c22c2c60SArnd Bergmann #endif 56