xref: /linux/arch/arm/mach-orion5x/common.c (revision 95e9fd10f06cb5642028b6b851e32b8c8afb4571) 
1 /*
2  * arch/arm/mach-orion5x/common.c
3  *
4  * Core functions for Marvell Orion 5x SoCs
5  *
6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2.  This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/serial_8250.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/ata_platform.h>
20 #include <linux/delay.h>
21 #include <linux/clk-provider.h>
22 #include <net/dsa.h>
23 #include <asm/page.h>
24 #include <asm/setup.h>
25 #include <asm/system_misc.h>
26 #include <asm/timex.h>
27 #include <asm/mach/arch.h>
28 #include <asm/mach/map.h>
29 #include <asm/mach/time.h>
30 #include <mach/bridge-regs.h>
31 #include <mach/hardware.h>
32 #include <mach/orion5x.h>
33 #include <plat/orion_nand.h>
34 #include <plat/ehci-orion.h>
35 #include <plat/time.h>
36 #include <plat/common.h>
37 #include <plat/addr-map.h>
38 #include "common.h"
39 
40 /*****************************************************************************
41  * I/O Address Mapping
42  ****************************************************************************/
43 static struct map_desc orion5x_io_desc[] __initdata = {
44 	{
45 		.virtual	= ORION5X_REGS_VIRT_BASE,
46 		.pfn		= __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
47 		.length		= ORION5X_REGS_SIZE,
48 		.type		= MT_DEVICE,
49 	}, {
50 		.virtual	= ORION5X_PCIE_IO_VIRT_BASE,
51 		.pfn		= __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
52 		.length		= ORION5X_PCIE_IO_SIZE,
53 		.type		= MT_DEVICE,
54 	}, {
55 		.virtual	= ORION5X_PCI_IO_VIRT_BASE,
56 		.pfn		= __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
57 		.length		= ORION5X_PCI_IO_SIZE,
58 		.type		= MT_DEVICE,
59 	}, {
60 		.virtual	= ORION5X_PCIE_WA_VIRT_BASE,
61 		.pfn		= __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
62 		.length		= ORION5X_PCIE_WA_SIZE,
63 		.type		= MT_DEVICE,
64 	},
65 };
66 
67 void __init orion5x_map_io(void)
68 {
69 	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
70 }
71 
72 
73 /*****************************************************************************
74  * CLK tree
75  ****************************************************************************/
76 static struct clk *tclk;
77 
78 static void __init clk_init(void)
79 {
80 	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
81 				       orion5x_tclk);
82 
83 	orion_clkdev_init(tclk);
84 }
85 
86 /*****************************************************************************
87  * EHCI0
88  ****************************************************************************/
89 void __init orion5x_ehci0_init(void)
90 {
91 	orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
92 			EHCI_PHY_ORION);
93 }
94 
95 
96 /*****************************************************************************
97  * EHCI1
98  ****************************************************************************/
99 void __init orion5x_ehci1_init(void)
100 {
101 	orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
102 }
103 
104 
105 /*****************************************************************************
106  * GE00
107  ****************************************************************************/
108 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
109 {
110 	orion_ge00_init(eth_data,
111 			ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
112 			IRQ_ORION5X_ETH_ERR,
113 			MV643XX_TX_CSUM_DEFAULT_LIMIT);
114 }
115 
116 
117 /*****************************************************************************
118  * Ethernet switch
119  ****************************************************************************/
120 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
121 {
122 	orion_ge00_switch_init(d, irq);
123 }
124 
125 
126 /*****************************************************************************
127  * I2C
128  ****************************************************************************/
129 void __init orion5x_i2c_init(void)
130 {
131 	orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
132 
133 }
134 
135 
136 /*****************************************************************************
137  * SATA
138  ****************************************************************************/
139 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
140 {
141 	orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
142 }
143 
144 
145 /*****************************************************************************
146  * SPI
147  ****************************************************************************/
148 void __init orion5x_spi_init()
149 {
150 	orion_spi_init(SPI_PHYS_BASE);
151 }
152 
153 
154 /*****************************************************************************
155  * UART0
156  ****************************************************************************/
157 void __init orion5x_uart0_init(void)
158 {
159 	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
160 			 IRQ_ORION5X_UART0, tclk);
161 }
162 
163 /*****************************************************************************
164  * UART1
165  ****************************************************************************/
166 void __init orion5x_uart1_init(void)
167 {
168 	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
169 			 IRQ_ORION5X_UART1, tclk);
170 }
171 
172 /*****************************************************************************
173  * XOR engine
174  ****************************************************************************/
175 void __init orion5x_xor_init(void)
176 {
177 	orion_xor0_init(ORION5X_XOR_PHYS_BASE,
178 			ORION5X_XOR_PHYS_BASE + 0x200,
179 			IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
180 }
181 
182 /*****************************************************************************
183  * Cryptographic Engines and Security Accelerator (CESA)
184  ****************************************************************************/
185 static void __init orion5x_crypto_init(void)
186 {
187 	orion5x_setup_sram_win();
188 	orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
189 			  SZ_8K, IRQ_ORION5X_CESA);
190 }
191 
192 /*****************************************************************************
193  * Watchdog
194  ****************************************************************************/
195 void __init orion5x_wdt_init(void)
196 {
197 	orion_wdt_init();
198 }
199 
200 
201 /*****************************************************************************
202  * Time handling
203  ****************************************************************************/
204 void __init orion5x_init_early(void)
205 {
206 	orion_time_set_base(TIMER_VIRT_BASE);
207 }
208 
209 int orion5x_tclk;
210 
211 int __init orion5x_find_tclk(void)
212 {
213 	u32 dev, rev;
214 
215 	orion5x_pcie_id(&dev, &rev);
216 	if (dev == MV88F6183_DEV_ID &&
217 	    (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
218 		return 133333333;
219 
220 	return 166666667;
221 }
222 
223 static void __init orion5x_timer_init(void)
224 {
225 	orion5x_tclk = orion5x_find_tclk();
226 
227 	orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
228 			IRQ_ORION5X_BRIDGE, orion5x_tclk);
229 }
230 
231 struct sys_timer orion5x_timer = {
232 	.init = orion5x_timer_init,
233 };
234 
235 
236 /*****************************************************************************
237  * General
238  ****************************************************************************/
239 /*
240  * Identify device ID and rev from PCIe configuration header space '0'.
241  */
242 static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
243 {
244 	orion5x_pcie_id(dev, rev);
245 
246 	if (*dev == MV88F5281_DEV_ID) {
247 		if (*rev == MV88F5281_REV_D2) {
248 			*dev_name = "MV88F5281-D2";
249 		} else if (*rev == MV88F5281_REV_D1) {
250 			*dev_name = "MV88F5281-D1";
251 		} else if (*rev == MV88F5281_REV_D0) {
252 			*dev_name = "MV88F5281-D0";
253 		} else {
254 			*dev_name = "MV88F5281-Rev-Unsupported";
255 		}
256 	} else if (*dev == MV88F5182_DEV_ID) {
257 		if (*rev == MV88F5182_REV_A2) {
258 			*dev_name = "MV88F5182-A2";
259 		} else {
260 			*dev_name = "MV88F5182-Rev-Unsupported";
261 		}
262 	} else if (*dev == MV88F5181_DEV_ID) {
263 		if (*rev == MV88F5181_REV_B1) {
264 			*dev_name = "MV88F5181-Rev-B1";
265 		} else if (*rev == MV88F5181L_REV_A1) {
266 			*dev_name = "MV88F5181L-Rev-A1";
267 		} else {
268 			*dev_name = "MV88F5181(L)-Rev-Unsupported";
269 		}
270 	} else if (*dev == MV88F6183_DEV_ID) {
271 		if (*rev == MV88F6183_REV_B0) {
272 			*dev_name = "MV88F6183-Rev-B0";
273 		} else {
274 			*dev_name = "MV88F6183-Rev-Unsupported";
275 		}
276 	} else {
277 		*dev_name = "Device-Unknown";
278 	}
279 }
280 
281 void __init orion5x_init(void)
282 {
283 	char *dev_name;
284 	u32 dev, rev;
285 
286 	orion5x_id(&dev, &rev, &dev_name);
287 	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
288 
289 	/*
290 	 * Setup Orion address map
291 	 */
292 	orion5x_setup_cpu_mbus_bridge();
293 
294 	/* Setup root of clk tree */
295 	clk_init();
296 
297 	/*
298 	 * Don't issue "Wait for Interrupt" instruction if we are
299 	 * running on D0 5281 silicon.
300 	 */
301 	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
302 		printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
303 		disable_hlt();
304 	}
305 
306 	/*
307 	 * The 5082/5181l/5182/6082/6082l/6183 have crypto
308 	 * while 5180n/5181/5281 don't have crypto.
309 	 */
310 	if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
311 	    dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
312 		orion5x_crypto_init();
313 
314 	/*
315 	 * Register watchdog driver
316 	 */
317 	orion5x_wdt_init();
318 }
319 
320 void orion5x_restart(char mode, const char *cmd)
321 {
322 	/*
323 	 * Enable and issue soft reset
324 	 */
325 	orion5x_setbits(RSTOUTn_MASK, (1 << 2));
326 	orion5x_setbits(CPU_SOFT_RESET, 1);
327 	mdelay(200);
328 	orion5x_clrbits(CPU_SOFT_RESET, 1);
329 }
330 
331 /*
332  * Many orion-based systems have buggy bootloader implementations.
333  * This is a common fixup for bogus memory tags.
334  */
335 void __init tag_fixup_mem32(struct tag *t, char **from,
336 			    struct meminfo *meminfo)
337 {
338 	for (; t->hdr.size; t = tag_next(t))
339 		if (t->hdr.tag == ATAG_MEM &&
340 		    (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
341 		     t->u.mem.start & ~PAGE_MASK)) {
342 			printk(KERN_WARNING
343 			       "Clearing invalid memory bank %dKB@0x%08x\n",
344 			       t->u.mem.size / 1024, t->u.mem.start);
345 			t->hdr.tag = 0;
346 		}
347 }
348