xref: /linux/arch/arm/mach-orion5x/common.c (revision 3932b9ca55b0be314a36d3e84faff3e823c081f5) 
1 /*
2  * arch/arm/mach-orion5x/common.c
3  *
4  * Core functions for Marvell Orion 5x SoCs
5  *
6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2.  This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/serial_8250.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/ata_platform.h>
20 #include <linux/delay.h>
21 #include <linux/clk-provider.h>
22 #include <linux/cpu.h>
23 #include <net/dsa.h>
24 #include <asm/page.h>
25 #include <asm/setup.h>
26 #include <asm/system_misc.h>
27 #include <asm/mach/arch.h>
28 #include <asm/mach/map.h>
29 #include <asm/mach/time.h>
30 #include <mach/bridge-regs.h>
31 #include <mach/hardware.h>
32 #include <mach/orion5x.h>
33 #include <linux/platform_data/mtd-orion_nand.h>
34 #include <linux/platform_data/usb-ehci-orion.h>
35 #include <plat/time.h>
36 #include <plat/common.h>
37 #include "common.h"
38 
39 /*****************************************************************************
40  * I/O Address Mapping
41  ****************************************************************************/
42 static struct map_desc orion5x_io_desc[] __initdata = {
43 	{
44 		.virtual	= (unsigned long) ORION5X_REGS_VIRT_BASE,
45 		.pfn		= __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
46 		.length		= ORION5X_REGS_SIZE,
47 		.type		= MT_DEVICE,
48 	}, {
49 		.virtual	= (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
50 		.pfn		= __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
51 		.length		= ORION5X_PCIE_WA_SIZE,
52 		.type		= MT_DEVICE,
53 	},
54 };
55 
56 void __init orion5x_map_io(void)
57 {
58 	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
59 }
60 
61 
62 /*****************************************************************************
63  * CLK tree
64  ****************************************************************************/
65 static struct clk *tclk;
66 
67 void __init clk_init(void)
68 {
69 	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
70 				       orion5x_tclk);
71 
72 	orion_clkdev_init(tclk);
73 }
74 
75 /*****************************************************************************
76  * EHCI0
77  ****************************************************************************/
78 void __init orion5x_ehci0_init(void)
79 {
80 	orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
81 			EHCI_PHY_ORION);
82 }
83 
84 
85 /*****************************************************************************
86  * EHCI1
87  ****************************************************************************/
88 void __init orion5x_ehci1_init(void)
89 {
90 	orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
91 }
92 
93 
94 /*****************************************************************************
95  * GE00
96  ****************************************************************************/
97 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
98 {
99 	orion_ge00_init(eth_data,
100 			ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
101 			IRQ_ORION5X_ETH_ERR,
102 			MV643XX_TX_CSUM_DEFAULT_LIMIT);
103 }
104 
105 
106 /*****************************************************************************
107  * Ethernet switch
108  ****************************************************************************/
109 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
110 {
111 	orion_ge00_switch_init(d, irq);
112 }
113 
114 
115 /*****************************************************************************
116  * I2C
117  ****************************************************************************/
118 void __init orion5x_i2c_init(void)
119 {
120 	orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
121 
122 }
123 
124 
125 /*****************************************************************************
126  * SATA
127  ****************************************************************************/
128 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
129 {
130 	orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
131 }
132 
133 
134 /*****************************************************************************
135  * SPI
136  ****************************************************************************/
137 void __init orion5x_spi_init(void)
138 {
139 	orion_spi_init(SPI_PHYS_BASE);
140 }
141 
142 
143 /*****************************************************************************
144  * UART0
145  ****************************************************************************/
146 void __init orion5x_uart0_init(void)
147 {
148 	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
149 			 IRQ_ORION5X_UART0, tclk);
150 }
151 
152 /*****************************************************************************
153  * UART1
154  ****************************************************************************/
155 void __init orion5x_uart1_init(void)
156 {
157 	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
158 			 IRQ_ORION5X_UART1, tclk);
159 }
160 
161 /*****************************************************************************
162  * XOR engine
163  ****************************************************************************/
164 void __init orion5x_xor_init(void)
165 {
166 	orion_xor0_init(ORION5X_XOR_PHYS_BASE,
167 			ORION5X_XOR_PHYS_BASE + 0x200,
168 			IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
169 }
170 
171 /*****************************************************************************
172  * Cryptographic Engines and Security Accelerator (CESA)
173  ****************************************************************************/
174 static void __init orion5x_crypto_init(void)
175 {
176 	mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
177 				    ORION_MBUS_SRAM_ATTR,
178 				    ORION5X_SRAM_PHYS_BASE,
179 				    ORION5X_SRAM_SIZE);
180 	orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
181 			  SZ_8K, IRQ_ORION5X_CESA);
182 }
183 
184 /*****************************************************************************
185  * Watchdog
186  ****************************************************************************/
187 static void __init orion5x_wdt_init(void)
188 {
189 	orion_wdt_init();
190 }
191 
192 
193 /*****************************************************************************
194  * Time handling
195  ****************************************************************************/
196 void __init orion5x_init_early(void)
197 {
198 	u32 rev, dev;
199 	const char *mbus_soc_name;
200 
201 	orion_time_set_base(TIMER_VIRT_BASE);
202 
203 	/* Initialize the MBUS driver */
204 	orion5x_pcie_id(&dev, &rev);
205 	if (dev == MV88F5281_DEV_ID)
206 		mbus_soc_name = "marvell,orion5x-88f5281-mbus";
207 	else if (dev == MV88F5182_DEV_ID)
208 		mbus_soc_name = "marvell,orion5x-88f5182-mbus";
209 	else if (dev == MV88F5181_DEV_ID)
210 		mbus_soc_name = "marvell,orion5x-88f5181-mbus";
211 	else if (dev == MV88F6183_DEV_ID)
212 		mbus_soc_name = "marvell,orion5x-88f6183-mbus";
213 	else
214 		mbus_soc_name = NULL;
215 	mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
216 			ORION5X_BRIDGE_WINS_SZ,
217 			ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
218 }
219 
220 void orion5x_setup_wins(void)
221 {
222 	/*
223 	 * The PCIe windows will no longer be statically allocated
224 	 * here once Orion5x is migrated to the pci-mvebu driver.
225 	 */
226 	mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
227 					  ORION_MBUS_PCIE_IO_ATTR,
228 					  ORION5X_PCIE_IO_PHYS_BASE,
229 					  ORION5X_PCIE_IO_SIZE,
230 					  ORION5X_PCIE_IO_BUS_BASE);
231 	mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
232 				    ORION_MBUS_PCIE_MEM_ATTR,
233 				    ORION5X_PCIE_MEM_PHYS_BASE,
234 				    ORION5X_PCIE_MEM_SIZE);
235 	mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
236 					  ORION_MBUS_PCI_IO_ATTR,
237 					  ORION5X_PCI_IO_PHYS_BASE,
238 					  ORION5X_PCI_IO_SIZE,
239 					  ORION5X_PCI_IO_BUS_BASE);
240 	mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
241 				    ORION_MBUS_PCI_MEM_ATTR,
242 				    ORION5X_PCI_MEM_PHYS_BASE,
243 				    ORION5X_PCI_MEM_SIZE);
244 }
245 
246 int orion5x_tclk;
247 
248 static int __init orion5x_find_tclk(void)
249 {
250 	u32 dev, rev;
251 
252 	orion5x_pcie_id(&dev, &rev);
253 	if (dev == MV88F6183_DEV_ID &&
254 	    (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
255 		return 133333333;
256 
257 	return 166666667;
258 }
259 
260 void __init orion5x_timer_init(void)
261 {
262 	orion5x_tclk = orion5x_find_tclk();
263 
264 	orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
265 			IRQ_ORION5X_BRIDGE, orion5x_tclk);
266 }
267 
268 
269 /*****************************************************************************
270  * General
271  ****************************************************************************/
272 /*
273  * Identify device ID and rev from PCIe configuration header space '0'.
274  */
275 void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
276 {
277 	orion5x_pcie_id(dev, rev);
278 
279 	if (*dev == MV88F5281_DEV_ID) {
280 		if (*rev == MV88F5281_REV_D2) {
281 			*dev_name = "MV88F5281-D2";
282 		} else if (*rev == MV88F5281_REV_D1) {
283 			*dev_name = "MV88F5281-D1";
284 		} else if (*rev == MV88F5281_REV_D0) {
285 			*dev_name = "MV88F5281-D0";
286 		} else {
287 			*dev_name = "MV88F5281-Rev-Unsupported";
288 		}
289 	} else if (*dev == MV88F5182_DEV_ID) {
290 		if (*rev == MV88F5182_REV_A2) {
291 			*dev_name = "MV88F5182-A2";
292 		} else {
293 			*dev_name = "MV88F5182-Rev-Unsupported";
294 		}
295 	} else if (*dev == MV88F5181_DEV_ID) {
296 		if (*rev == MV88F5181_REV_B1) {
297 			*dev_name = "MV88F5181-Rev-B1";
298 		} else if (*rev == MV88F5181L_REV_A1) {
299 			*dev_name = "MV88F5181L-Rev-A1";
300 		} else {
301 			*dev_name = "MV88F5181(L)-Rev-Unsupported";
302 		}
303 	} else if (*dev == MV88F6183_DEV_ID) {
304 		if (*rev == MV88F6183_REV_B0) {
305 			*dev_name = "MV88F6183-Rev-B0";
306 		} else {
307 			*dev_name = "MV88F6183-Rev-Unsupported";
308 		}
309 	} else {
310 		*dev_name = "Device-Unknown";
311 	}
312 }
313 
314 void __init orion5x_init(void)
315 {
316 	char *dev_name;
317 	u32 dev, rev;
318 
319 	orion5x_id(&dev, &rev, &dev_name);
320 	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
321 
322 	/*
323 	 * Setup Orion address map
324 	 */
325 	orion5x_setup_wins();
326 
327 	/* Setup root of clk tree */
328 	clk_init();
329 
330 	/*
331 	 * Don't issue "Wait for Interrupt" instruction if we are
332 	 * running on D0 5281 silicon.
333 	 */
334 	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
335 		printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
336 		cpu_idle_poll_ctrl(true);
337 	}
338 
339 	/*
340 	 * The 5082/5181l/5182/6082/6082l/6183 have crypto
341 	 * while 5180n/5181/5281 don't have crypto.
342 	 */
343 	if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
344 	    dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
345 		orion5x_crypto_init();
346 
347 	/*
348 	 * Register watchdog driver
349 	 */
350 	orion5x_wdt_init();
351 }
352 
353 void orion5x_restart(enum reboot_mode mode, const char *cmd)
354 {
355 	/*
356 	 * Enable and issue soft reset
357 	 */
358 	orion5x_setbits(RSTOUTn_MASK, (1 << 2));
359 	orion5x_setbits(CPU_SOFT_RESET, 1);
360 	mdelay(200);
361 	orion5x_clrbits(CPU_SOFT_RESET, 1);
362 }
363 
364 /*
365  * Many orion-based systems have buggy bootloader implementations.
366  * This is a common fixup for bogus memory tags.
367  */
368 void __init tag_fixup_mem32(struct tag *t, char **from)
369 {
370 	for (; t->hdr.size; t = tag_next(t))
371 		if (t->hdr.tag == ATAG_MEM &&
372 		    (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
373 		     t->u.mem.start & ~PAGE_MASK)) {
374 			printk(KERN_WARNING
375 			       "Clearing invalid memory bank %dKB@0x%08x\n",
376 			       t->u.mem.size / 1024, t->u.mem.start);
377 			t->hdr.tag = 0;
378 		}
379 }
380