1 /* 2 * OMAP Voltage Controller (VC) interface 3 * 4 * Copyright (C) 2011 Texas Instruments, Inc. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 #include <linux/kernel.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <linux/bug.h> 14 #include <linux/io.h> 15 16 #include <asm/div64.h> 17 18 #include "iomap.h" 19 #include "soc.h" 20 #include "voltage.h" 21 #include "vc.h" 22 #include "prm-regbits-34xx.h" 23 #include "prm-regbits-44xx.h" 24 #include "prm44xx.h" 25 #include "pm.h" 26 #include "scrm44xx.h" 27 #include "control.h" 28 29 #define OMAP4430_VDD_IVA_I2C_DISABLE BIT(14) 30 #define OMAP4430_VDD_MPU_I2C_DISABLE BIT(13) 31 #define OMAP4430_VDD_CORE_I2C_DISABLE BIT(12) 32 #define OMAP4430_VDD_IVA_PRESENCE BIT(9) 33 #define OMAP4430_VDD_MPU_PRESENCE BIT(8) 34 #define OMAP4430_AUTO_CTRL_VDD_IVA(x) ((x) << 4) 35 #define OMAP4430_AUTO_CTRL_VDD_MPU(x) ((x) << 2) 36 #define OMAP4430_AUTO_CTRL_VDD_CORE(x) ((x) << 0) 37 #define OMAP4430_AUTO_CTRL_VDD_RET 2 38 39 #define OMAP4430_VDD_I2C_DISABLE_MASK \ 40 (OMAP4430_VDD_IVA_I2C_DISABLE | \ 41 OMAP4430_VDD_MPU_I2C_DISABLE | \ 42 OMAP4430_VDD_CORE_I2C_DISABLE) 43 44 #define OMAP4_VDD_DEFAULT_VAL \ 45 (OMAP4430_VDD_I2C_DISABLE_MASK | \ 46 OMAP4430_VDD_IVA_PRESENCE | OMAP4430_VDD_MPU_PRESENCE | \ 47 OMAP4430_AUTO_CTRL_VDD_IVA(OMAP4430_AUTO_CTRL_VDD_RET) | \ 48 OMAP4430_AUTO_CTRL_VDD_MPU(OMAP4430_AUTO_CTRL_VDD_RET) | \ 49 OMAP4430_AUTO_CTRL_VDD_CORE(OMAP4430_AUTO_CTRL_VDD_RET)) 50 51 #define OMAP4_VDD_RET_VAL \ 52 (OMAP4_VDD_DEFAULT_VAL & ~OMAP4430_VDD_I2C_DISABLE_MASK) 53 54 /** 55 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield 56 * @sa: bit for slave address 57 * @rav: bit for voltage configuration register 58 * @rac: bit for command configuration register 59 * @racen: enable bit for RAC 60 * @cmd: bit for command value set selection 61 * 62 * Channel configuration bits, common for OMAP3+ 63 * OMAP3 register: PRM_VC_CH_CONF 64 * OMAP4 register: PRM_VC_CFG_CHANNEL 65 * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG 66 */ 67 struct omap_vc_channel_cfg { 68 u8 sa; 69 u8 rav; 70 u8 rac; 71 u8 racen; 72 u8 cmd; 73 }; 74 75 static struct omap_vc_channel_cfg vc_default_channel_cfg = { 76 .sa = BIT(0), 77 .rav = BIT(1), 78 .rac = BIT(2), 79 .racen = BIT(3), 80 .cmd = BIT(4), 81 }; 82 83 /* 84 * On OMAP3+, all VC channels have the above default bitfield 85 * configuration, except the OMAP4 MPU channel. This appears 86 * to be a freak accident as every other VC channel has the 87 * default configuration, thus creating a mutant channel config. 88 */ 89 static struct omap_vc_channel_cfg vc_mutant_channel_cfg = { 90 .sa = BIT(0), 91 .rav = BIT(2), 92 .rac = BIT(3), 93 .racen = BIT(4), 94 .cmd = BIT(1), 95 }; 96 97 static struct omap_vc_channel_cfg *vc_cfg_bits; 98 99 /* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */ 100 static u32 sr_i2c_pcb_length = 63; 101 #define CFG_CHANNEL_MASK 0x1f 102 103 /** 104 * omap_vc_config_channel - configure VC channel to PMIC mappings 105 * @voltdm: pointer to voltagdomain defining the desired VC channel 106 * 107 * Configures the VC channel to PMIC mappings for the following 108 * PMIC settings 109 * - i2c slave address (SA) 110 * - voltage configuration address (RAV) 111 * - command configuration address (RAC) and enable bit (RACEN) 112 * - command values for ON, ONLP, RET and OFF (CMD) 113 * 114 * This function currently only allows flexible configuration of the 115 * non-default channel. Starting with OMAP4, there are more than 2 116 * channels, with one defined as the default (on OMAP4, it's MPU.) 117 * Only the non-default channel can be configured. 118 */ 119 static int omap_vc_config_channel(struct voltagedomain *voltdm) 120 { 121 struct omap_vc_channel *vc = voltdm->vc; 122 123 /* 124 * For default channel, the only configurable bit is RACEN. 125 * All others must stay at zero (see function comment above.) 126 */ 127 if (vc->flags & OMAP_VC_CHANNEL_DEFAULT) 128 vc->cfg_channel &= vc_cfg_bits->racen; 129 130 voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift, 131 vc->cfg_channel << vc->cfg_channel_sa_shift, 132 vc->cfg_channel_reg); 133 134 return 0; 135 } 136 137 /* Voltage scale and accessory APIs */ 138 int omap_vc_pre_scale(struct voltagedomain *voltdm, 139 unsigned long target_volt, 140 u8 *target_vsel, u8 *current_vsel) 141 { 142 struct omap_vc_channel *vc = voltdm->vc; 143 u32 vc_cmdval; 144 145 /* Check if sufficient pmic info is available for this vdd */ 146 if (!voltdm->pmic) { 147 pr_err("%s: Insufficient pmic info to scale the vdd_%s\n", 148 __func__, voltdm->name); 149 return -EINVAL; 150 } 151 152 if (!voltdm->pmic->uv_to_vsel) { 153 pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n", 154 __func__, voltdm->name); 155 return -ENODATA; 156 } 157 158 if (!voltdm->read || !voltdm->write) { 159 pr_err("%s: No read/write API for accessing vdd_%s regs\n", 160 __func__, voltdm->name); 161 return -EINVAL; 162 } 163 164 *target_vsel = voltdm->pmic->uv_to_vsel(target_volt); 165 *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt); 166 167 /* Setting the ON voltage to the new target voltage */ 168 vc_cmdval = voltdm->read(vc->cmdval_reg); 169 vc_cmdval &= ~vc->common->cmd_on_mask; 170 vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift); 171 voltdm->write(vc_cmdval, vc->cmdval_reg); 172 173 voltdm->vc_param->on = target_volt; 174 175 omap_vp_update_errorgain(voltdm, target_volt); 176 177 return 0; 178 } 179 180 void omap_vc_post_scale(struct voltagedomain *voltdm, 181 unsigned long target_volt, 182 u8 target_vsel, u8 current_vsel) 183 { 184 u32 smps_steps = 0, smps_delay = 0; 185 186 smps_steps = abs(target_vsel - current_vsel); 187 /* SMPS slew rate / step size. 2us added as buffer. */ 188 smps_delay = ((smps_steps * voltdm->pmic->step_size) / 189 voltdm->pmic->slew_rate) + 2; 190 udelay(smps_delay); 191 } 192 193 /* vc_bypass_scale - VC bypass method of voltage scaling */ 194 int omap_vc_bypass_scale(struct voltagedomain *voltdm, 195 unsigned long target_volt) 196 { 197 struct omap_vc_channel *vc = voltdm->vc; 198 u32 loop_cnt = 0, retries_cnt = 0; 199 u32 vc_valid, vc_bypass_val_reg, vc_bypass_value; 200 u8 target_vsel, current_vsel; 201 int ret; 202 203 ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel); 204 if (ret) 205 return ret; 206 207 vc_valid = vc->common->valid; 208 vc_bypass_val_reg = vc->common->bypass_val_reg; 209 vc_bypass_value = (target_vsel << vc->common->data_shift) | 210 (vc->volt_reg_addr << vc->common->regaddr_shift) | 211 (vc->i2c_slave_addr << vc->common->slaveaddr_shift); 212 213 voltdm->write(vc_bypass_value, vc_bypass_val_reg); 214 voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg); 215 216 vc_bypass_value = voltdm->read(vc_bypass_val_reg); 217 /* 218 * Loop till the bypass command is acknowledged from the SMPS. 219 * NOTE: This is legacy code. The loop count and retry count needs 220 * to be revisited. 221 */ 222 while (!(vc_bypass_value & vc_valid)) { 223 loop_cnt++; 224 225 if (retries_cnt > 10) { 226 pr_warn("%s: Retry count exceeded\n", __func__); 227 return -ETIMEDOUT; 228 } 229 230 if (loop_cnt > 50) { 231 retries_cnt++; 232 loop_cnt = 0; 233 udelay(10); 234 } 235 vc_bypass_value = voltdm->read(vc_bypass_val_reg); 236 } 237 238 omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel); 239 return 0; 240 } 241 242 /* Convert microsecond value to number of 32kHz clock cycles */ 243 static inline u32 omap_usec_to_32k(u32 usec) 244 { 245 return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL); 246 } 247 248 struct omap3_vc_timings { 249 u32 voltsetup1; 250 u32 voltsetup2; 251 }; 252 253 struct omap3_vc { 254 struct voltagedomain *vd; 255 u32 voltctrl; 256 u32 voltsetup1; 257 u32 voltsetup2; 258 struct omap3_vc_timings timings[2]; 259 }; 260 static struct omap3_vc vc; 261 262 void omap3_vc_set_pmic_signaling(int core_next_state) 263 { 264 struct voltagedomain *vd = vc.vd; 265 struct omap3_vc_timings *c = vc.timings; 266 u32 voltctrl, voltsetup1, voltsetup2; 267 268 voltctrl = vc.voltctrl; 269 voltsetup1 = vc.voltsetup1; 270 voltsetup2 = vc.voltsetup2; 271 272 switch (core_next_state) { 273 case PWRDM_POWER_OFF: 274 voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET | 275 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); 276 voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF; 277 if (voltctrl & OMAP3430_PRM_VOLTCTRL_SEL_OFF) 278 voltsetup2 = c->voltsetup2; 279 else 280 voltsetup1 = c->voltsetup1; 281 break; 282 case PWRDM_POWER_RET: 283 default: 284 c++; 285 voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF | 286 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); 287 voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET; 288 voltsetup1 = c->voltsetup1; 289 break; 290 } 291 292 if (voltctrl != vc.voltctrl) { 293 vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET); 294 vc.voltctrl = voltctrl; 295 } 296 if (voltsetup1 != vc.voltsetup1) { 297 vd->write(c->voltsetup1, 298 OMAP3_PRM_VOLTSETUP1_OFFSET); 299 vc.voltsetup1 = voltsetup1; 300 } 301 if (voltsetup2 != vc.voltsetup2) { 302 vd->write(c->voltsetup2, 303 OMAP3_PRM_VOLTSETUP2_OFFSET); 304 vc.voltsetup2 = voltsetup2; 305 } 306 } 307 308 void omap4_vc_set_pmic_signaling(int core_next_state) 309 { 310 struct voltagedomain *vd = vc.vd; 311 u32 val; 312 313 if (!vd) 314 return; 315 316 switch (core_next_state) { 317 case PWRDM_POWER_RET: 318 val = OMAP4_VDD_RET_VAL; 319 break; 320 default: 321 val = OMAP4_VDD_DEFAULT_VAL; 322 break; 323 } 324 325 vd->write(val, OMAP4_PRM_VOLTCTRL_OFFSET); 326 } 327 328 /* 329 * Configure signal polarity for sys_clkreq and sys_off_mode pins 330 * as the default values are wrong and can cause the system to hang 331 * if any twl4030 scripts are loaded. 332 */ 333 static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm) 334 { 335 u32 val; 336 337 if (vc.vd) 338 return; 339 340 vc.vd = voltdm; 341 342 val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET); 343 if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) || 344 (val & OMAP3430_PRM_POLCTRL_OFFMODE_POL)) { 345 val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL; 346 val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL; 347 pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n", 348 val); 349 voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET); 350 } 351 352 /* 353 * By default let's use I2C4 signaling for retention idle 354 * and sys_off_mode pin signaling for off idle. This way we 355 * have sys_clk_req pin go down for retention and both 356 * sys_clk_req and sys_off_mode pins will go down for off 357 * idle. And we can also scale voltages to zero for off-idle. 358 * Note that no actual voltage scaling during off-idle will 359 * happen unless the board specific twl4030 PMIC scripts are 360 * loaded. See also omap_vc_i2c_init for comments regarding 361 * erratum i531. 362 */ 363 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); 364 if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { 365 val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF; 366 pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n", 367 val); 368 voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET); 369 } 370 vc.voltctrl = val; 371 372 omap3_vc_set_pmic_signaling(PWRDM_POWER_ON); 373 } 374 375 static void omap3_init_voltsetup1(struct voltagedomain *voltdm, 376 struct omap3_vc_timings *c, u32 idle) 377 { 378 unsigned long val; 379 380 val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate; 381 val *= voltdm->sys_clk.rate / 8 / 1000000 + 1; 382 val <<= __ffs(voltdm->vfsm->voltsetup_mask); 383 c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask; 384 c->voltsetup1 |= val; 385 } 386 387 /** 388 * omap3_set_i2c_timings - sets i2c sleep timings for a channel 389 * @voltdm: channel to configure 390 * @off_mode: select whether retention or off mode values used 391 * 392 * Calculates and sets up voltage controller to use I2C based 393 * voltage scaling for sleep modes. This can be used for either off mode 394 * or retention. Off mode has additionally an option to use sys_off_mode 395 * pad, which uses a global signal to program the whole power IC to 396 * off-mode. 397 * 398 * Note that pmic is not controlling the voltage scaling during 399 * retention signaled over I2C4, so we can keep voltsetup2 as 0. 400 * And the oscillator is not shut off over I2C4, so no need to 401 * set clksetup. 402 */ 403 static void omap3_set_i2c_timings(struct voltagedomain *voltdm) 404 { 405 struct omap3_vc_timings *c = vc.timings; 406 407 /* Configure PRWDM_POWER_OFF over I2C4 */ 408 omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->off); 409 c++; 410 /* Configure PRWDM_POWER_RET over I2C4 */ 411 omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->ret); 412 } 413 414 /** 415 * omap3_set_off_timings - sets off-mode timings for a channel 416 * @voltdm: channel to configure 417 * 418 * Calculates and sets up off-mode timings for a channel. Off-mode 419 * can use either I2C based voltage scaling, or alternatively 420 * sys_off_mode pad can be used to send a global command to power IC.n, 421 * sys_off_mode has the additional benefit that voltages can be 422 * scaled to zero volt level with TWL4030 / TWL5030, I2C can only 423 * scale to 600mV. 424 * 425 * Note that omap is not controlling the voltage scaling during 426 * off idle signaled by sys_off_mode, so we can keep voltsetup1 427 * as 0. 428 */ 429 static void omap3_set_off_timings(struct voltagedomain *voltdm) 430 { 431 struct omap3_vc_timings *c = vc.timings; 432 u32 tstart, tshut, clksetup, voltoffset; 433 434 if (c->voltsetup2) 435 return; 436 437 omap_pm_get_oscillator(&tstart, &tshut); 438 if (tstart == ULONG_MAX) { 439 pr_debug("PM: oscillator start-up time not initialized, using 10ms\n"); 440 clksetup = omap_usec_to_32k(10000); 441 } else { 442 clksetup = omap_usec_to_32k(tstart); 443 } 444 445 /* 446 * For twl4030 errata 27, we need to allow minimum ~488.32 us wait to 447 * switch from HFCLKIN to internal oscillator. That means timings 448 * have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And 449 * that means we can calculate the value based on the oscillator 450 * start-up time since voltoffset2 = clksetup - voltoffset. 451 */ 452 voltoffset = omap_usec_to_32k(488); 453 c->voltsetup2 = clksetup - voltoffset; 454 voltdm->write(clksetup, OMAP3_PRM_CLKSETUP_OFFSET); 455 voltdm->write(voltoffset, OMAP3_PRM_VOLTOFFSET_OFFSET); 456 } 457 458 static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) 459 { 460 omap3_vc_init_pmic_signaling(voltdm); 461 omap3_set_off_timings(voltdm); 462 omap3_set_i2c_timings(voltdm); 463 } 464 465 /** 466 * omap4_calc_volt_ramp - calculates voltage ramping delays on omap4 467 * @voltdm: channel to calculate values for 468 * @voltage_diff: voltage difference in microvolts 469 * 470 * Calculates voltage ramp prescaler + counter values for a voltage 471 * difference on omap4. Returns a field value suitable for writing to 472 * VOLTSETUP register for a channel in following format: 473 * bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference. 474 */ 475 static u32 omap4_calc_volt_ramp(struct voltagedomain *voltdm, u32 voltage_diff) 476 { 477 u32 prescaler; 478 u32 cycles; 479 u32 time; 480 481 time = voltage_diff / voltdm->pmic->slew_rate; 482 483 cycles = voltdm->sys_clk.rate / 1000 * time / 1000; 484 485 cycles /= 64; 486 prescaler = 0; 487 488 /* shift to next prescaler until no overflow */ 489 490 /* scale for div 256 = 64 * 4 */ 491 if (cycles > 63) { 492 cycles /= 4; 493 prescaler++; 494 } 495 496 /* scale for div 512 = 256 * 2 */ 497 if (cycles > 63) { 498 cycles /= 2; 499 prescaler++; 500 } 501 502 /* scale for div 2048 = 512 * 4 */ 503 if (cycles > 63) { 504 cycles /= 4; 505 prescaler++; 506 } 507 508 /* check for overflow => invalid ramp time */ 509 if (cycles > 63) { 510 pr_warn("%s: invalid setuptime for vdd_%s\n", __func__, 511 voltdm->name); 512 return 0; 513 } 514 515 cycles++; 516 517 return (prescaler << OMAP4430_RAMP_UP_PRESCAL_SHIFT) | 518 (cycles << OMAP4430_RAMP_UP_COUNT_SHIFT); 519 } 520 521 /** 522 * omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield 523 * @usec: microseconds 524 * @shift: number of bits to shift left 525 * @mask: bitfield mask 526 * 527 * Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is 528 * shifted to requested position, and checked agains the mask value. 529 * If larger, forced to the max value of the field (i.e. the mask itself.) 530 * Returns the SCRM bitfield value. 531 */ 532 static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask) 533 { 534 u32 val; 535 536 val = omap_usec_to_32k(usec) << shift; 537 538 /* Check for overflow, if yes, force to max value */ 539 if (val > mask) 540 val = mask; 541 542 return val; 543 } 544 545 /** 546 * omap4_set_timings - set voltage ramp timings for a channel 547 * @voltdm: channel to configure 548 * @off_mode: whether off-mode values are used 549 * 550 * Calculates and sets the voltage ramp up / down values for a channel. 551 */ 552 static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode) 553 { 554 u32 val; 555 u32 ramp; 556 int offset; 557 u32 tstart, tshut; 558 559 if (off_mode) { 560 ramp = omap4_calc_volt_ramp(voltdm, 561 voltdm->vc_param->on - voltdm->vc_param->off); 562 offset = voltdm->vfsm->voltsetup_off_reg; 563 } else { 564 ramp = omap4_calc_volt_ramp(voltdm, 565 voltdm->vc_param->on - voltdm->vc_param->ret); 566 offset = voltdm->vfsm->voltsetup_reg; 567 } 568 569 if (!ramp) 570 return; 571 572 val = voltdm->read(offset); 573 574 val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT; 575 576 val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT; 577 578 voltdm->write(val, offset); 579 580 omap_pm_get_oscillator(&tstart, &tshut); 581 582 val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT, 583 OMAP4_SETUPTIME_MASK); 584 val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT, 585 OMAP4_DOWNTIME_MASK); 586 587 writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME); 588 } 589 590 static void __init omap4_vc_init_pmic_signaling(struct voltagedomain *voltdm) 591 { 592 if (vc.vd) 593 return; 594 595 vc.vd = voltdm; 596 voltdm->write(OMAP4_VDD_DEFAULT_VAL, OMAP4_PRM_VOLTCTRL_OFFSET); 597 } 598 599 /* OMAP4 specific voltage init functions */ 600 static void __init omap4_vc_init_channel(struct voltagedomain *voltdm) 601 { 602 omap4_vc_init_pmic_signaling(voltdm); 603 omap4_set_timings(voltdm, true); 604 omap4_set_timings(voltdm, false); 605 } 606 607 struct i2c_init_data { 608 u8 loadbits; 609 u8 load; 610 u8 hsscll_38_4; 611 u8 hsscll_26; 612 u8 hsscll_19_2; 613 u8 hsscll_16_8; 614 u8 hsscll_12; 615 }; 616 617 static const struct i2c_init_data omap4_i2c_timing_data[] __initconst = { 618 { 619 .load = 50, 620 .loadbits = 0x3, 621 .hsscll_38_4 = 13, 622 .hsscll_26 = 11, 623 .hsscll_19_2 = 9, 624 .hsscll_16_8 = 9, 625 .hsscll_12 = 8, 626 }, 627 { 628 .load = 25, 629 .loadbits = 0x2, 630 .hsscll_38_4 = 13, 631 .hsscll_26 = 11, 632 .hsscll_19_2 = 9, 633 .hsscll_16_8 = 9, 634 .hsscll_12 = 8, 635 }, 636 { 637 .load = 12, 638 .loadbits = 0x1, 639 .hsscll_38_4 = 11, 640 .hsscll_26 = 10, 641 .hsscll_19_2 = 9, 642 .hsscll_16_8 = 9, 643 .hsscll_12 = 8, 644 }, 645 { 646 .load = 0, 647 .loadbits = 0x0, 648 .hsscll_38_4 = 12, 649 .hsscll_26 = 10, 650 .hsscll_19_2 = 9, 651 .hsscll_16_8 = 8, 652 .hsscll_12 = 8, 653 }, 654 }; 655 656 /** 657 * omap4_vc_i2c_timing_init - sets up board I2C timing parameters 658 * @voltdm: voltagedomain pointer to get data from 659 * 660 * Use PMIC + board supplied settings for calculating the total I2C 661 * channel capacitance and set the timing parameters based on this. 662 * Pre-calculated values are provided in data tables, as it is not 663 * too straightforward to calculate these runtime. 664 */ 665 static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm) 666 { 667 u32 capacitance; 668 u32 val; 669 u16 hsscll; 670 const struct i2c_init_data *i2c_data; 671 672 if (!voltdm->pmic->i2c_high_speed) { 673 pr_info("%s: using bootloader low-speed timings\n", __func__); 674 return; 675 } 676 677 /* PCB trace capacitance, 0.125pF / mm => mm / 8 */ 678 capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8); 679 680 /* OMAP pad capacitance */ 681 capacitance += 4; 682 683 /* PMIC pad capacitance */ 684 capacitance += voltdm->pmic->i2c_pad_load; 685 686 /* Search for capacitance match in the table */ 687 i2c_data = omap4_i2c_timing_data; 688 689 while (i2c_data->load > capacitance) 690 i2c_data++; 691 692 /* Select proper values based on sysclk frequency */ 693 switch (voltdm->sys_clk.rate) { 694 case 38400000: 695 hsscll = i2c_data->hsscll_38_4; 696 break; 697 case 26000000: 698 hsscll = i2c_data->hsscll_26; 699 break; 700 case 19200000: 701 hsscll = i2c_data->hsscll_19_2; 702 break; 703 case 16800000: 704 hsscll = i2c_data->hsscll_16_8; 705 break; 706 case 12000000: 707 hsscll = i2c_data->hsscll_12; 708 break; 709 default: 710 pr_warn("%s: unsupported sysclk rate: %d!\n", __func__, 711 voltdm->sys_clk.rate); 712 return; 713 } 714 715 /* Loadbits define pull setup for the I2C channels */ 716 val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29; 717 718 /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */ 719 writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP + 720 OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2)); 721 722 /* HSSCLH can always be zero */ 723 val = hsscll << OMAP4430_HSSCLL_SHIFT; 724 val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT); 725 726 /* Write setup times to I2C config register */ 727 voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); 728 } 729 730 731 732 /** 733 * omap_vc_i2c_init - initialize I2C interface to PMIC 734 * @voltdm: voltage domain containing VC data 735 * 736 * Use PMIC supplied settings for I2C high-speed mode and 737 * master code (if set) and program the VC I2C configuration 738 * register. 739 * 740 * The VC I2C configuration is common to all VC channels, 741 * so this function only configures I2C for the first VC 742 * channel registers. All other VC channels will use the 743 * same configuration. 744 */ 745 static void __init omap_vc_i2c_init(struct voltagedomain *voltdm) 746 { 747 struct omap_vc_channel *vc = voltdm->vc; 748 static bool initialized; 749 static bool i2c_high_speed; 750 u8 mcode; 751 752 if (initialized) { 753 if (voltdm->pmic->i2c_high_speed != i2c_high_speed) 754 pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).\n", 755 __func__, voltdm->name, i2c_high_speed); 756 return; 757 } 758 759 /* 760 * Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around 761 * erratum i531 "Extra Power Consumed When Repeated Start Operation 762 * Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)". 763 * Otherwise I2C4 eventually leads into about 23mW extra power being 764 * consumed even during off idle using VMODE. 765 */ 766 i2c_high_speed = voltdm->pmic->i2c_high_speed; 767 if (i2c_high_speed) 768 voltdm->rmw(vc->common->i2c_cfg_clear_mask, 769 vc->common->i2c_cfg_hsen_mask, 770 vc->common->i2c_cfg_reg); 771 772 mcode = voltdm->pmic->i2c_mcode; 773 if (mcode) 774 voltdm->rmw(vc->common->i2c_mcode_mask, 775 mcode << __ffs(vc->common->i2c_mcode_mask), 776 vc->common->i2c_cfg_reg); 777 778 if (cpu_is_omap44xx()) 779 omap4_vc_i2c_timing_init(voltdm); 780 781 initialized = true; 782 } 783 784 /** 785 * omap_vc_calc_vsel - calculate vsel value for a channel 786 * @voltdm: channel to calculate value for 787 * @uvolt: microvolt value to convert to vsel 788 * 789 * Converts a microvolt value to vsel value for the used PMIC. 790 * This checks whether the microvolt value is out of bounds, and 791 * adjusts the value accordingly. If unsupported value detected, 792 * warning is thrown. 793 */ 794 static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt) 795 { 796 if (voltdm->pmic->vddmin > uvolt) 797 uvolt = voltdm->pmic->vddmin; 798 if (voltdm->pmic->vddmax < uvolt) { 799 WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n", 800 __func__, uvolt, voltdm->pmic->vddmax); 801 /* Lets try maximum value anyway */ 802 uvolt = voltdm->pmic->vddmax; 803 } 804 805 return voltdm->pmic->uv_to_vsel(uvolt); 806 } 807 808 #ifdef CONFIG_PM 809 /** 810 * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB 811 * @mm: length of the PCB trace in millimetres 812 * 813 * Sets the PCB trace length for the I2C channel. By default uses 63mm. 814 * This is needed for properly calculating the capacitance value for 815 * the PCB trace, and for setting the SR I2C channel timing parameters. 816 */ 817 void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm) 818 { 819 sr_i2c_pcb_length = mm; 820 } 821 #endif 822 823 void __init omap_vc_init_channel(struct voltagedomain *voltdm) 824 { 825 struct omap_vc_channel *vc = voltdm->vc; 826 u8 on_vsel, onlp_vsel, ret_vsel, off_vsel; 827 u32 val; 828 829 if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { 830 pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name); 831 return; 832 } 833 834 if (!voltdm->read || !voltdm->write) { 835 pr_err("%s: No read/write API for accessing vdd_%s regs\n", 836 __func__, voltdm->name); 837 return; 838 } 839 840 vc->cfg_channel = 0; 841 if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT) 842 vc_cfg_bits = &vc_mutant_channel_cfg; 843 else 844 vc_cfg_bits = &vc_default_channel_cfg; 845 846 /* get PMIC/board specific settings */ 847 vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr; 848 vc->volt_reg_addr = voltdm->pmic->volt_reg_addr; 849 vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr; 850 851 /* Configure the i2c slave address for this VC */ 852 voltdm->rmw(vc->smps_sa_mask, 853 vc->i2c_slave_addr << __ffs(vc->smps_sa_mask), 854 vc->smps_sa_reg); 855 vc->cfg_channel |= vc_cfg_bits->sa; 856 857 /* 858 * Configure the PMIC register addresses. 859 */ 860 voltdm->rmw(vc->smps_volra_mask, 861 vc->volt_reg_addr << __ffs(vc->smps_volra_mask), 862 vc->smps_volra_reg); 863 vc->cfg_channel |= vc_cfg_bits->rav; 864 865 if (vc->cmd_reg_addr) { 866 voltdm->rmw(vc->smps_cmdra_mask, 867 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask), 868 vc->smps_cmdra_reg); 869 vc->cfg_channel |= vc_cfg_bits->rac; 870 } 871 872 if (vc->cmd_reg_addr == vc->volt_reg_addr) 873 vc->cfg_channel |= vc_cfg_bits->racen; 874 875 /* Set up the on, inactive, retention and off voltage */ 876 on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on); 877 onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp); 878 ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret); 879 off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off); 880 881 val = ((on_vsel << vc->common->cmd_on_shift) | 882 (onlp_vsel << vc->common->cmd_onlp_shift) | 883 (ret_vsel << vc->common->cmd_ret_shift) | 884 (off_vsel << vc->common->cmd_off_shift)); 885 voltdm->write(val, vc->cmdval_reg); 886 vc->cfg_channel |= vc_cfg_bits->cmd; 887 888 /* Channel configuration */ 889 omap_vc_config_channel(voltdm); 890 891 omap_vc_i2c_init(voltdm); 892 893 if (cpu_is_omap34xx()) 894 omap3_vc_init_channel(voltdm); 895 else if (cpu_is_omap44xx()) 896 omap4_vc_init_channel(voltdm); 897 } 898 899