1 /* 2 * linux/arch/arm/mach-omap2/timer.c 3 * 4 * OMAP2 GP timer support. 5 * 6 * Copyright (C) 2009 Nokia Corporation 7 * 8 * Update to use new clocksource/clockevent layers 9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 10 * Copyright (C) 2007 MontaVista Software, Inc. 11 * 12 * Original driver: 13 * Copyright (C) 2005 Nokia Corporation 14 * Author: Paul Mundt <paul.mundt@nokia.com> 15 * Juha Yrjölä <juha.yrjola@nokia.com> 16 * OMAP Dual-mode timer framework support by Timo Teras 17 * 18 * Some parts based off of TI's 24xx code: 19 * 20 * Copyright (C) 2004-2009 Texas Instruments, Inc. 21 * 22 * Roughly modelled after the OMAP1 MPU timer code. 23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 24 * 25 * This file is subject to the terms and conditions of the GNU General Public 26 * License. See the file "COPYING" in the main directory of this archive 27 * for more details. 28 */ 29 #include <linux/init.h> 30 #include <linux/time.h> 31 #include <linux/interrupt.h> 32 #include <linux/err.h> 33 #include <linux/clk.h> 34 #include <linux/delay.h> 35 #include <linux/irq.h> 36 #include <linux/clocksource.h> 37 #include <linux/clockchips.h> 38 #include <linux/slab.h> 39 #include <linux/of.h> 40 #include <linux/of_address.h> 41 #include <linux/of_irq.h> 42 #include <linux/platform_device.h> 43 #include <linux/platform_data/dmtimer-omap.h> 44 #include <linux/sched_clock.h> 45 46 #include <asm/mach/time.h> 47 #include <asm/smp_twd.h> 48 49 #include "omap_hwmod.h" 50 #include "omap_device.h" 51 #include <plat/counter-32k.h> 52 #include <plat/dmtimer.h> 53 #include "omap-pm.h" 54 55 #include "soc.h" 56 #include "common.h" 57 #include "control.h" 58 #include "powerdomain.h" 59 #include "omap-secure.h" 60 61 #define REALTIME_COUNTER_BASE 0x48243200 62 #define INCREMENTER_NUMERATOR_OFFSET 0x10 63 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 64 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 65 66 /* Clockevent code */ 67 68 static struct omap_dm_timer clkev; 69 static struct clock_event_device clockevent_gpt; 70 71 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 72 static unsigned long arch_timer_freq; 73 74 void set_cntfreq(void) 75 { 76 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); 77 } 78 #endif 79 80 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 81 { 82 struct clock_event_device *evt = &clockevent_gpt; 83 84 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); 85 86 evt->event_handler(evt); 87 return IRQ_HANDLED; 88 } 89 90 static struct irqaction omap2_gp_timer_irq = { 91 .name = "gp_timer", 92 .flags = IRQF_TIMER | IRQF_IRQPOLL, 93 .handler = omap2_gp_timer_interrupt, 94 }; 95 96 static int omap2_gp_timer_set_next_event(unsigned long cycles, 97 struct clock_event_device *evt) 98 { 99 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 100 0xffffffff - cycles, OMAP_TIMER_POSTED); 101 102 return 0; 103 } 104 105 static int omap2_gp_timer_shutdown(struct clock_event_device *evt) 106 { 107 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); 108 return 0; 109 } 110 111 static int omap2_gp_timer_set_periodic(struct clock_event_device *evt) 112 { 113 u32 period; 114 115 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); 116 117 period = clkev.rate / HZ; 118 period -= 1; 119 /* Looks like we need to first set the load value separately */ 120 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period, 121 OMAP_TIMER_POSTED); 122 __omap_dm_timer_load_start(&clkev, 123 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 124 0xffffffff - period, OMAP_TIMER_POSTED); 125 return 0; 126 } 127 128 static struct clock_event_device clockevent_gpt = { 129 .features = CLOCK_EVT_FEAT_PERIODIC | 130 CLOCK_EVT_FEAT_ONESHOT, 131 .rating = 300, 132 .set_next_event = omap2_gp_timer_set_next_event, 133 .set_state_shutdown = omap2_gp_timer_shutdown, 134 .set_state_periodic = omap2_gp_timer_set_periodic, 135 .set_state_oneshot = omap2_gp_timer_shutdown, 136 .tick_resume = omap2_gp_timer_shutdown, 137 }; 138 139 static struct property device_disabled = { 140 .name = "status", 141 .length = sizeof("disabled"), 142 .value = "disabled", 143 }; 144 145 static const struct of_device_id omap_timer_match[] __initconst = { 146 { .compatible = "ti,omap2420-timer", }, 147 { .compatible = "ti,omap3430-timer", }, 148 { .compatible = "ti,omap4430-timer", }, 149 { .compatible = "ti,omap5430-timer", }, 150 { .compatible = "ti,dm814-timer", }, 151 { .compatible = "ti,dm816-timer", }, 152 { .compatible = "ti,am335x-timer", }, 153 { .compatible = "ti,am335x-timer-1ms", }, 154 { } 155 }; 156 157 /** 158 * omap_get_timer_dt - get a timer using device-tree 159 * @match - device-tree match structure for matching a device type 160 * @property - optional timer property to match 161 * 162 * Helper function to get a timer during early boot using device-tree for use 163 * as kernel system timer. Optionally, the property argument can be used to 164 * select a timer with a specific property. Once a timer is found then mark 165 * the timer node in device-tree as disabled, to prevent the kernel from 166 * registering this timer as a platform device and so no one else can use it. 167 */ 168 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match, 169 const char *property) 170 { 171 struct device_node *np; 172 173 for_each_matching_node(np, match) { 174 if (!of_device_is_available(np)) 175 continue; 176 177 if (property && !of_get_property(np, property, NULL)) 178 continue; 179 180 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || 181 of_get_property(np, "ti,timer-dsp", NULL) || 182 of_get_property(np, "ti,timer-pwm", NULL) || 183 of_get_property(np, "ti,timer-secure", NULL))) 184 continue; 185 186 if (!of_device_is_compatible(np, "ti,omap-counter32k")) 187 of_add_property(np, &device_disabled); 188 return np; 189 } 190 191 return NULL; 192 } 193 194 /** 195 * omap_dmtimer_init - initialisation function when device tree is used 196 * 197 * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure" 198 * cannot be used by the kernel as they are reserved. Therefore, to prevent the 199 * kernel registering these devices remove them dynamically from the device 200 * tree on boot. 201 */ 202 static void __init omap_dmtimer_init(void) 203 { 204 struct device_node *np; 205 206 if (!cpu_is_omap34xx() && !soc_is_dra7xx()) 207 return; 208 209 /* If we are a secure device, remove any secure timer nodes */ 210 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { 211 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); 212 of_node_put(np); 213 } 214 } 215 216 /** 217 * omap_dm_timer_get_errata - get errata flags for a timer 218 * 219 * Get the timer errata flags that are specific to the OMAP device being used. 220 */ 221 static u32 __init omap_dm_timer_get_errata(void) 222 { 223 if (cpu_is_omap24xx()) 224 return 0; 225 226 return OMAP_TIMER_ERRATA_I103_I767; 227 } 228 229 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, 230 const char *fck_source, 231 const char *property, 232 const char **timer_name, 233 int posted) 234 { 235 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 236 const char *oh_name = NULL; 237 struct device_node *np; 238 struct omap_hwmod *oh; 239 struct resource irq, mem; 240 struct clk *src; 241 int r = 0; 242 243 if (of_have_populated_dt()) { 244 np = omap_get_timer_dt(omap_timer_match, property); 245 if (!np) 246 return -ENODEV; 247 248 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 249 if (!oh_name) 250 return -ENODEV; 251 252 timer->irq = irq_of_parse_and_map(np, 0); 253 if (!timer->irq) 254 return -ENXIO; 255 256 timer->io_base = of_iomap(np, 0); 257 258 of_node_put(np); 259 } else { 260 if (omap_dm_timer_reserve_systimer(timer->id)) 261 return -ENODEV; 262 263 sprintf(name, "timer%d", timer->id); 264 oh_name = name; 265 } 266 267 oh = omap_hwmod_lookup(oh_name); 268 if (!oh) 269 return -ENODEV; 270 271 *timer_name = oh->name; 272 273 if (!of_have_populated_dt()) { 274 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, 275 &irq); 276 if (r) 277 return -ENXIO; 278 timer->irq = irq.start; 279 280 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, 281 &mem); 282 if (r) 283 return -ENXIO; 284 285 /* Static mapping, never released */ 286 timer->io_base = ioremap(mem.start, mem.end - mem.start); 287 } 288 289 if (!timer->io_base) 290 return -ENXIO; 291 292 omap_hwmod_setup_one(oh_name); 293 294 /* After the dmtimer is using hwmod these clocks won't be needed */ 295 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); 296 if (IS_ERR(timer->fclk)) 297 return PTR_ERR(timer->fclk); 298 299 src = clk_get(NULL, fck_source); 300 if (IS_ERR(src)) 301 return PTR_ERR(src); 302 303 WARN(clk_set_parent(timer->fclk, src) < 0, 304 "Cannot set timer parent clock, no PLL clock driver?"); 305 306 clk_put(src); 307 308 omap_hwmod_enable(oh); 309 __omap_dm_timer_init_regs(timer); 310 311 if (posted) 312 __omap_dm_timer_enable_posted(timer); 313 314 /* Check that the intended posted configuration matches the actual */ 315 if (posted != timer->posted) 316 return -EINVAL; 317 318 timer->rate = clk_get_rate(timer->fclk); 319 timer->reserved = 1; 320 321 return r; 322 } 323 324 #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) 325 void tick_broadcast(const struct cpumask *mask) 326 { 327 } 328 #endif 329 330 static void __init omap2_gp_clockevent_init(int gptimer_id, 331 const char *fck_source, 332 const char *property) 333 { 334 int res; 335 336 clkev.id = gptimer_id; 337 clkev.errata = omap_dm_timer_get_errata(); 338 339 /* 340 * For clock-event timers we never read the timer counter and 341 * so we are not impacted by errata i103 and i767. Therefore, 342 * we can safely ignore this errata for clock-event timers. 343 */ 344 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); 345 346 res = omap_dm_timer_init_one(&clkev, fck_source, property, 347 &clockevent_gpt.name, OMAP_TIMER_POSTED); 348 BUG_ON(res); 349 350 omap2_gp_timer_irq.dev_id = &clkev; 351 setup_irq(clkev.irq, &omap2_gp_timer_irq); 352 353 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); 354 355 clockevent_gpt.cpumask = cpu_possible_mask; 356 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); 357 clockevents_config_and_register(&clockevent_gpt, clkev.rate, 358 3, /* Timer internal resynch latency */ 359 0xffffffff); 360 361 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, 362 clkev.rate); 363 } 364 365 /* Clocksource code */ 366 static struct omap_dm_timer clksrc; 367 static bool use_gptimer_clksrc __initdata; 368 369 /* 370 * clocksource 371 */ 372 static u64 clocksource_read_cycles(struct clocksource *cs) 373 { 374 return (u64)__omap_dm_timer_read_counter(&clksrc, 375 OMAP_TIMER_NONPOSTED); 376 } 377 378 static struct clocksource clocksource_gpt = { 379 .rating = 300, 380 .read = clocksource_read_cycles, 381 .mask = CLOCKSOURCE_MASK(32), 382 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 383 }; 384 385 static u64 notrace dmtimer_read_sched_clock(void) 386 { 387 if (clksrc.reserved) 388 return __omap_dm_timer_read_counter(&clksrc, 389 OMAP_TIMER_NONPOSTED); 390 391 return 0; 392 } 393 394 static const struct of_device_id omap_counter_match[] __initconst = { 395 { .compatible = "ti,omap-counter32k", }, 396 { } 397 }; 398 399 /* Setup free-running counter for clocksource */ 400 static int __init __maybe_unused omap2_sync32k_clocksource_init(void) 401 { 402 int ret; 403 struct device_node *np = NULL; 404 struct omap_hwmod *oh; 405 const char *oh_name = "counter_32k"; 406 407 /* 408 * If device-tree is present, then search the DT blob 409 * to see if the 32kHz counter is supported. 410 */ 411 if (of_have_populated_dt()) { 412 np = omap_get_timer_dt(omap_counter_match, NULL); 413 if (!np) 414 return -ENODEV; 415 416 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 417 if (!oh_name) 418 return -ENODEV; 419 } 420 421 /* 422 * First check hwmod data is available for sync32k counter 423 */ 424 oh = omap_hwmod_lookup(oh_name); 425 if (!oh || oh->slaves_cnt == 0) 426 return -ENODEV; 427 428 omap_hwmod_setup_one(oh_name); 429 430 ret = omap_hwmod_enable(oh); 431 if (ret) { 432 pr_warn("%s: failed to enable counter_32k module (%d)\n", 433 __func__, ret); 434 return ret; 435 } 436 437 if (!of_have_populated_dt()) { 438 void __iomem *vbase; 439 440 vbase = omap_hwmod_get_mpu_rt_va(oh); 441 442 ret = omap_init_clocksource_32k(vbase); 443 if (ret) { 444 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", 445 __func__, ret); 446 omap_hwmod_idle(oh); 447 } 448 } 449 return ret; 450 } 451 452 static void __init omap2_gptimer_clocksource_init(int gptimer_id, 453 const char *fck_source, 454 const char *property) 455 { 456 int res; 457 458 clksrc.id = gptimer_id; 459 clksrc.errata = omap_dm_timer_get_errata(); 460 461 res = omap_dm_timer_init_one(&clksrc, fck_source, property, 462 &clocksource_gpt.name, 463 OMAP_TIMER_NONPOSTED); 464 BUG_ON(res); 465 466 __omap_dm_timer_load_start(&clksrc, 467 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 468 OMAP_TIMER_NONPOSTED); 469 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate); 470 471 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 472 pr_err("Could not register clocksource %s\n", 473 clocksource_gpt.name); 474 else 475 pr_info("OMAP clocksource: %s at %lu Hz\n", 476 clocksource_gpt.name, clksrc.rate); 477 } 478 479 static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src, 480 const char *clkev_prop, int clksrc_nr, const char *clksrc_src, 481 const char *clksrc_prop, bool gptimer) 482 { 483 omap_clk_init(); 484 omap_dmtimer_init(); 485 omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop); 486 487 /* Enable the use of clocksource="gp_timer" kernel parameter */ 488 if (use_gptimer_clksrc || gptimer) 489 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src, 490 clksrc_prop); 491 else 492 omap2_sync32k_clocksource_init(); 493 } 494 495 void __init omap_init_time(void) 496 { 497 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", 498 2, "timer_sys_ck", NULL, false); 499 500 clocksource_probe(); 501 } 502 503 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) 504 void __init omap3_secure_sync32k_timer_init(void) 505 { 506 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure", 507 2, "timer_sys_ck", NULL, false); 508 509 clocksource_probe(); 510 } 511 #endif /* CONFIG_ARCH_OMAP3 */ 512 513 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \ 514 defined(CONFIG_SOC_AM43XX) 515 void __init omap3_gptimer_timer_init(void) 516 { 517 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL, 518 1, "timer_sys_ck", "ti,timer-alwon", true); 519 if (of_have_populated_dt()) 520 clocksource_probe(); 521 } 522 #endif 523 524 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 525 defined(CONFIG_SOC_DRA7XX) 526 static void __init omap4_sync32k_timer_init(void) 527 { 528 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", 529 2, "sys_clkin_ck", NULL, false); 530 } 531 532 void __init omap4_local_timer_init(void) 533 { 534 omap4_sync32k_timer_init(); 535 clocksource_probe(); 536 } 537 #endif 538 539 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) 540 541 /* 542 * The realtime counter also called master counter, is a free-running 543 * counter, which is related to real time. It produces the count used 544 * by the CPU local timer peripherals in the MPU cluster. The timer counts 545 * at a rate of 6.144 MHz. Because the device operates on different clocks 546 * in different power modes, the master counter shifts operation between 547 * clocks, adjusting the increment per clock in hardware accordingly to 548 * maintain a constant count rate. 549 */ 550 static void __init realtime_counter_init(void) 551 { 552 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 553 void __iomem *base; 554 static struct clk *sys_clk; 555 unsigned long rate; 556 unsigned int reg; 557 unsigned long long num, den; 558 559 base = ioremap(REALTIME_COUNTER_BASE, SZ_32); 560 if (!base) { 561 pr_err("%s: ioremap failed\n", __func__); 562 return; 563 } 564 sys_clk = clk_get(NULL, "sys_clkin"); 565 if (IS_ERR(sys_clk)) { 566 pr_err("%s: failed to get system clock handle\n", __func__); 567 iounmap(base); 568 return; 569 } 570 571 rate = clk_get_rate(sys_clk); 572 573 if (soc_is_dra7xx()) { 574 /* 575 * Errata i856 says the 32.768KHz crystal does not start at 576 * power on, so the CPU falls back to an emulated 32KHz clock 577 * based on sysclk / 610 instead. This causes the master counter 578 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 579 * (OR sysclk * 75 / 244) 580 * 581 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions. 582 * Of course any board built without a populated 32.768KHz 583 * crystal would also need this fix even if the CPU is fixed 584 * later. 585 * 586 * Either case can be detected by using the two speedselect bits 587 * If they are not 0, then the 32.768KHz clock driving the 588 * coarse counter that corrects the fine counter every time it 589 * ticks is actually rate/610 rather than 32.768KHz and we 590 * should compensate to avoid the 570ppm (at 20MHz, much worse 591 * at other rates) too fast system time. 592 */ 593 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); 594 if (reg & DRA7_SPEEDSELECT_MASK) { 595 num = 75; 596 den = 244; 597 goto sysclk1_based; 598 } 599 } 600 601 /* Numerator/denumerator values refer TRM Realtime Counter section */ 602 switch (rate) { 603 case 12000000: 604 num = 64; 605 den = 125; 606 break; 607 case 13000000: 608 num = 768; 609 den = 1625; 610 break; 611 case 19200000: 612 num = 8; 613 den = 25; 614 break; 615 case 20000000: 616 num = 192; 617 den = 625; 618 break; 619 case 26000000: 620 num = 384; 621 den = 1625; 622 break; 623 case 27000000: 624 num = 256; 625 den = 1125; 626 break; 627 case 38400000: 628 default: 629 /* Program it for 38.4 MHz */ 630 num = 4; 631 den = 25; 632 break; 633 } 634 635 sysclk1_based: 636 /* Program numerator and denumerator registers */ 637 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & 638 NUMERATOR_DENUMERATOR_MASK; 639 reg |= num; 640 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET); 641 642 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & 643 NUMERATOR_DENUMERATOR_MASK; 644 reg |= den; 645 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); 646 647 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den); 648 set_cntfreq(); 649 650 iounmap(base); 651 #endif 652 } 653 654 void __init omap5_realtime_timer_init(void) 655 { 656 omap4_sync32k_timer_init(); 657 realtime_counter_init(); 658 659 clocksource_probe(); 660 } 661 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ 662 663 /** 664 * omap_timer_init - build and register timer device with an 665 * associated timer hwmod 666 * @oh: timer hwmod pointer to be used to build timer device 667 * @user: parameter that can be passed from calling hwmod API 668 * 669 * Called by omap_hwmod_for_each_by_class to register each of the timer 670 * devices present in the system. The number of timer devices is known 671 * by parsing through the hwmod database for a given class name. At the 672 * end of function call memory is allocated for timer device and it is 673 * registered to the framework ready to be proved by the driver. 674 */ 675 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) 676 { 677 int id; 678 int ret = 0; 679 char *name = "omap_timer"; 680 struct dmtimer_platform_data *pdata; 681 struct platform_device *pdev; 682 struct omap_timer_capability_dev_attr *timer_dev_attr; 683 684 pr_debug("%s: %s\n", __func__, oh->name); 685 686 /* on secure device, do not register secure timer */ 687 timer_dev_attr = oh->dev_attr; 688 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) 689 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) 690 return ret; 691 692 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 693 if (!pdata) { 694 pr_err("%s: No memory for [%s]\n", __func__, oh->name); 695 return -ENOMEM; 696 } 697 698 /* 699 * Extract the IDs from name field in hwmod database 700 * and use the same for constructing ids' for the 701 * timer devices. In a way, we are avoiding usage of 702 * static variable witin the function to do the same. 703 * CAUTION: We have to be careful and make sure the 704 * name in hwmod database does not change in which case 705 * we might either make corresponding change here or 706 * switch back static variable mechanism. 707 */ 708 sscanf(oh->name, "timer%2d", &id); 709 710 if (timer_dev_attr) 711 pdata->timer_capability = timer_dev_attr->timer_capability; 712 713 pdata->timer_errata = omap_dm_timer_get_errata(); 714 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; 715 716 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata)); 717 718 if (IS_ERR(pdev)) { 719 pr_err("%s: Can't build omap_device for %s: %s.\n", 720 __func__, name, oh->name); 721 ret = -EINVAL; 722 } 723 724 kfree(pdata); 725 726 return ret; 727 } 728 729 /** 730 * omap2_dm_timer_init - top level regular device initialization 731 * 732 * Uses dedicated hwmod api to parse through hwmod database for 733 * given class name and then build and register the timer device. 734 */ 735 static int __init omap2_dm_timer_init(void) 736 { 737 int ret; 738 739 /* If dtb is there, the devices will be created dynamically */ 740 if (of_have_populated_dt()) 741 return -ENODEV; 742 743 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); 744 if (unlikely(ret)) { 745 pr_err("%s: device registration failed.\n", __func__); 746 return -EINVAL; 747 } 748 749 return 0; 750 } 751 omap_arch_initcall(omap2_dm_timer_init); 752 753 /** 754 * omap2_override_clocksource - clocksource override with user configuration 755 * 756 * Allows user to override default clocksource, using kernel parameter 757 * clocksource="gp_timer" (For all OMAP2PLUS architectures) 758 * 759 * Note that, here we are using same standard kernel parameter "clocksource=", 760 * and not introducing any OMAP specific interface. 761 */ 762 static int __init omap2_override_clocksource(char *str) 763 { 764 if (!str) 765 return 0; 766 /* 767 * For OMAP architecture, we only have two options 768 * - sync_32k (default) 769 * - gp_timer (sys_clk based) 770 */ 771 if (!strcmp(str, "gp_timer")) 772 use_gptimer_clksrc = true; 773 774 return 0; 775 } 776 early_param("clocksource", omap2_override_clocksource); 777