1 /* 2 * linux/arch/arm/mach-omap2/timer.c 3 * 4 * OMAP2 GP timer support. 5 * 6 * Copyright (C) 2009 Nokia Corporation 7 * 8 * Update to use new clocksource/clockevent layers 9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 10 * Copyright (C) 2007 MontaVista Software, Inc. 11 * 12 * Original driver: 13 * Copyright (C) 2005 Nokia Corporation 14 * Author: Paul Mundt <paul.mundt@nokia.com> 15 * Juha Yrjölä <juha.yrjola@nokia.com> 16 * OMAP Dual-mode timer framework support by Timo Teras 17 * 18 * Some parts based off of TI's 24xx code: 19 * 20 * Copyright (C) 2004-2009 Texas Instruments, Inc. 21 * 22 * Roughly modelled after the OMAP1 MPU timer code. 23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 24 * 25 * This file is subject to the terms and conditions of the GNU General Public 26 * License. See the file "COPYING" in the main directory of this archive 27 * for more details. 28 */ 29 #include <linux/init.h> 30 #include <linux/time.h> 31 #include <linux/interrupt.h> 32 #include <linux/err.h> 33 #include <linux/clk.h> 34 #include <linux/delay.h> 35 #include <linux/irq.h> 36 #include <linux/clocksource.h> 37 #include <linux/clockchips.h> 38 #include <linux/slab.h> 39 40 #include <asm/mach/time.h> 41 #include <plat/dmtimer.h> 42 #include <asm/smp_twd.h> 43 #include <asm/sched_clock.h> 44 #include "common.h" 45 #include <plat/omap_hwmod.h> 46 #include <plat/omap_device.h> 47 #include <plat/omap-pm.h> 48 49 #include "powerdomain.h" 50 51 /* Parent clocks, eventually these will come from the clock framework */ 52 53 #define OMAP2_MPU_SOURCE "sys_ck" 54 #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE 55 #define OMAP4_MPU_SOURCE "sys_clkin_ck" 56 #define OMAP2_32K_SOURCE "func_32k_ck" 57 #define OMAP3_32K_SOURCE "omap_32k_fck" 58 #define OMAP4_32K_SOURCE "sys_32k_ck" 59 60 #ifdef CONFIG_OMAP_32K_TIMER 61 #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE 62 #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE 63 #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE 64 #define OMAP3_SECURE_TIMER 12 65 #else 66 #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE 67 #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE 68 #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE 69 #define OMAP3_SECURE_TIMER 1 70 #endif 71 72 /* Clockevent code */ 73 74 static struct omap_dm_timer clkev; 75 static struct clock_event_device clockevent_gpt; 76 77 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 78 { 79 struct clock_event_device *evt = &clockevent_gpt; 80 81 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); 82 83 evt->event_handler(evt); 84 return IRQ_HANDLED; 85 } 86 87 static struct irqaction omap2_gp_timer_irq = { 88 .name = "gp_timer", 89 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 90 .handler = omap2_gp_timer_interrupt, 91 }; 92 93 static int omap2_gp_timer_set_next_event(unsigned long cycles, 94 struct clock_event_device *evt) 95 { 96 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 97 0xffffffff - cycles, 1); 98 99 return 0; 100 } 101 102 static void omap2_gp_timer_set_mode(enum clock_event_mode mode, 103 struct clock_event_device *evt) 104 { 105 u32 period; 106 107 __omap_dm_timer_stop(&clkev, 1, clkev.rate); 108 109 switch (mode) { 110 case CLOCK_EVT_MODE_PERIODIC: 111 period = clkev.rate / HZ; 112 period -= 1; 113 /* Looks like we need to first set the load value separately */ 114 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 115 0xffffffff - period, 1); 116 __omap_dm_timer_load_start(&clkev, 117 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 118 0xffffffff - period, 1); 119 break; 120 case CLOCK_EVT_MODE_ONESHOT: 121 break; 122 case CLOCK_EVT_MODE_UNUSED: 123 case CLOCK_EVT_MODE_SHUTDOWN: 124 case CLOCK_EVT_MODE_RESUME: 125 break; 126 } 127 } 128 129 static struct clock_event_device clockevent_gpt = { 130 .name = "gp_timer", 131 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 132 .shift = 32, 133 .set_next_event = omap2_gp_timer_set_next_event, 134 .set_mode = omap2_gp_timer_set_mode, 135 }; 136 137 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, 138 int gptimer_id, 139 const char *fck_source) 140 { 141 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 142 struct omap_hwmod *oh; 143 struct resource irq_rsrc, mem_rsrc; 144 size_t size; 145 int res = 0; 146 int r; 147 148 sprintf(name, "timer%d", gptimer_id); 149 omap_hwmod_setup_one(name); 150 oh = omap_hwmod_lookup(name); 151 if (!oh) 152 return -ENODEV; 153 154 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc); 155 if (r) 156 return -ENXIO; 157 timer->irq = irq_rsrc.start; 158 159 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc); 160 if (r) 161 return -ENXIO; 162 timer->phys_base = mem_rsrc.start; 163 size = mem_rsrc.end - mem_rsrc.start; 164 165 /* Static mapping, never released */ 166 timer->io_base = ioremap(timer->phys_base, size); 167 if (!timer->io_base) 168 return -ENXIO; 169 170 /* After the dmtimer is using hwmod these clocks won't be needed */ 171 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); 172 if (IS_ERR(timer->fclk)) 173 return -ENODEV; 174 175 omap_hwmod_enable(oh); 176 177 if (omap_dm_timer_reserve_systimer(gptimer_id)) 178 return -ENODEV; 179 180 if (gptimer_id != 12) { 181 struct clk *src; 182 183 src = clk_get(NULL, fck_source); 184 if (IS_ERR(src)) { 185 res = -EINVAL; 186 } else { 187 res = __omap_dm_timer_set_source(timer->fclk, src); 188 if (IS_ERR_VALUE(res)) 189 pr_warning("%s: timer%i cannot set source\n", 190 __func__, gptimer_id); 191 clk_put(src); 192 } 193 } 194 __omap_dm_timer_init_regs(timer); 195 __omap_dm_timer_reset(timer, 1, 1); 196 timer->posted = 1; 197 198 timer->rate = clk_get_rate(timer->fclk); 199 200 timer->reserved = 1; 201 202 return res; 203 } 204 205 static void __init omap2_gp_clockevent_init(int gptimer_id, 206 const char *fck_source) 207 { 208 int res; 209 210 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source); 211 BUG_ON(res); 212 213 omap2_gp_timer_irq.dev_id = (void *)&clkev; 214 setup_irq(clkev.irq, &omap2_gp_timer_irq); 215 216 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); 217 218 clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, 219 clockevent_gpt.shift); 220 clockevent_gpt.max_delta_ns = 221 clockevent_delta2ns(0xffffffff, &clockevent_gpt); 222 clockevent_gpt.min_delta_ns = 223 clockevent_delta2ns(3, &clockevent_gpt); 224 /* Timer internal resynch latency. */ 225 226 clockevent_gpt.cpumask = cpumask_of(0); 227 clockevents_register_device(&clockevent_gpt); 228 229 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", 230 gptimer_id, clkev.rate); 231 } 232 233 /* Clocksource code */ 234 static struct omap_dm_timer clksrc; 235 static bool use_gptimer_clksrc; 236 237 /* 238 * clocksource 239 */ 240 static cycle_t clocksource_read_cycles(struct clocksource *cs) 241 { 242 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1); 243 } 244 245 static struct clocksource clocksource_gpt = { 246 .name = "gp_timer", 247 .rating = 300, 248 .read = clocksource_read_cycles, 249 .mask = CLOCKSOURCE_MASK(32), 250 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 251 }; 252 253 static u32 notrace dmtimer_read_sched_clock(void) 254 { 255 if (clksrc.reserved) 256 return __omap_dm_timer_read_counter(&clksrc, 1); 257 258 return 0; 259 } 260 261 /* Setup free-running counter for clocksource */ 262 static int __init omap2_sync32k_clocksource_init(void) 263 { 264 int ret; 265 struct omap_hwmod *oh; 266 void __iomem *vbase; 267 const char *oh_name = "counter_32k"; 268 269 /* 270 * First check hwmod data is available for sync32k counter 271 */ 272 oh = omap_hwmod_lookup(oh_name); 273 if (!oh || oh->slaves_cnt == 0) 274 return -ENODEV; 275 276 omap_hwmod_setup_one(oh_name); 277 278 vbase = omap_hwmod_get_mpu_rt_va(oh); 279 if (!vbase) { 280 pr_warn("%s: failed to get counter_32k resource\n", __func__); 281 return -ENXIO; 282 } 283 284 ret = omap_hwmod_enable(oh); 285 if (ret) { 286 pr_warn("%s: failed to enable counter_32k module (%d)\n", 287 __func__, ret); 288 return ret; 289 } 290 291 ret = omap_init_clocksource_32k(vbase); 292 if (ret) { 293 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", 294 __func__, ret); 295 omap_hwmod_idle(oh); 296 } 297 298 return ret; 299 } 300 301 static void __init omap2_gptimer_clocksource_init(int gptimer_id, 302 const char *fck_source) 303 { 304 int res; 305 306 res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source); 307 BUG_ON(res); 308 309 __omap_dm_timer_load_start(&clksrc, 310 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1); 311 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); 312 313 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 314 pr_err("Could not register clocksource %s\n", 315 clocksource_gpt.name); 316 else 317 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", 318 gptimer_id, clksrc.rate); 319 } 320 321 static void __init omap2_clocksource_init(int gptimer_id, 322 const char *fck_source) 323 { 324 /* 325 * First give preference to kernel parameter configuration 326 * by user (clocksource="gp_timer"). 327 * 328 * In case of missing kernel parameter for clocksource, 329 * first check for availability for 32k-sync timer, in case 330 * of failure in finding 32k_counter module or registering 331 * it as clocksource, execution will fallback to gp-timer. 332 */ 333 if (use_gptimer_clksrc == true) 334 omap2_gptimer_clocksource_init(gptimer_id, fck_source); 335 else if (omap2_sync32k_clocksource_init()) 336 /* Fall back to gp-timer code */ 337 omap2_gptimer_clocksource_init(gptimer_id, fck_source); 338 } 339 340 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ 341 clksrc_nr, clksrc_src) \ 342 static void __init omap##name##_timer_init(void) \ 343 { \ 344 omap2_gp_clockevent_init((clkev_nr), clkev_src); \ 345 omap2_clocksource_init((clksrc_nr), clksrc_src); \ 346 } 347 348 #define OMAP_SYS_TIMER(name) \ 349 struct sys_timer omap##name##_timer = { \ 350 .init = omap##name##_timer_init, \ 351 }; 352 353 #ifdef CONFIG_ARCH_OMAP2 354 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE) 355 OMAP_SYS_TIMER(2) 356 #endif 357 358 #ifdef CONFIG_ARCH_OMAP3 359 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE) 360 OMAP_SYS_TIMER(3) 361 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, 362 2, OMAP3_MPU_SOURCE) 363 OMAP_SYS_TIMER(3_secure) 364 #endif 365 366 #ifdef CONFIG_SOC_AM33XX 367 OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE) 368 OMAP_SYS_TIMER(3_am33xx) 369 #endif 370 371 #ifdef CONFIG_ARCH_OMAP4 372 #ifdef CONFIG_LOCAL_TIMERS 373 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 374 OMAP44XX_LOCAL_TWD_BASE, 375 OMAP44XX_IRQ_LOCALTIMER); 376 #endif 377 378 static void __init omap4_timer_init(void) 379 { 380 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); 381 omap2_clocksource_init(2, OMAP4_MPU_SOURCE); 382 #ifdef CONFIG_LOCAL_TIMERS 383 /* Local timers are not supprted on OMAP4430 ES1.0 */ 384 if (omap_rev() != OMAP4430_REV_ES1_0) { 385 int err; 386 387 err = twd_local_timer_register(&twd_local_timer); 388 if (err) 389 pr_err("twd_local_timer_register failed %d\n", err); 390 } 391 #endif 392 } 393 OMAP_SYS_TIMER(4) 394 #endif 395 396 #ifdef CONFIG_SOC_OMAP5 397 OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE) 398 OMAP_SYS_TIMER(5) 399 #endif 400 401 /** 402 * omap_timer_init - build and register timer device with an 403 * associated timer hwmod 404 * @oh: timer hwmod pointer to be used to build timer device 405 * @user: parameter that can be passed from calling hwmod API 406 * 407 * Called by omap_hwmod_for_each_by_class to register each of the timer 408 * devices present in the system. The number of timer devices is known 409 * by parsing through the hwmod database for a given class name. At the 410 * end of function call memory is allocated for timer device and it is 411 * registered to the framework ready to be proved by the driver. 412 */ 413 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) 414 { 415 int id; 416 int ret = 0; 417 char *name = "omap_timer"; 418 struct dmtimer_platform_data *pdata; 419 struct platform_device *pdev; 420 struct omap_timer_capability_dev_attr *timer_dev_attr; 421 422 pr_debug("%s: %s\n", __func__, oh->name); 423 424 /* on secure device, do not register secure timer */ 425 timer_dev_attr = oh->dev_attr; 426 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) 427 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) 428 return ret; 429 430 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 431 if (!pdata) { 432 pr_err("%s: No memory for [%s]\n", __func__, oh->name); 433 return -ENOMEM; 434 } 435 436 /* 437 * Extract the IDs from name field in hwmod database 438 * and use the same for constructing ids' for the 439 * timer devices. In a way, we are avoiding usage of 440 * static variable witin the function to do the same. 441 * CAUTION: We have to be careful and make sure the 442 * name in hwmod database does not change in which case 443 * we might either make corresponding change here or 444 * switch back static variable mechanism. 445 */ 446 sscanf(oh->name, "timer%2d", &id); 447 448 if (timer_dev_attr) 449 pdata->timer_capability = timer_dev_attr->timer_capability; 450 451 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), 452 NULL, 0, 0); 453 454 if (IS_ERR(pdev)) { 455 pr_err("%s: Can't build omap_device for %s: %s.\n", 456 __func__, name, oh->name); 457 ret = -EINVAL; 458 } 459 460 kfree(pdata); 461 462 return ret; 463 } 464 465 /** 466 * omap2_dm_timer_init - top level regular device initialization 467 * 468 * Uses dedicated hwmod api to parse through hwmod database for 469 * given class name and then build and register the timer device. 470 */ 471 static int __init omap2_dm_timer_init(void) 472 { 473 int ret; 474 475 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); 476 if (unlikely(ret)) { 477 pr_err("%s: device registration failed.\n", __func__); 478 return -EINVAL; 479 } 480 481 return 0; 482 } 483 arch_initcall(omap2_dm_timer_init); 484 485 /** 486 * omap2_override_clocksource - clocksource override with user configuration 487 * 488 * Allows user to override default clocksource, using kernel parameter 489 * clocksource="gp_timer" (For all OMAP2PLUS architectures) 490 * 491 * Note that, here we are using same standard kernel parameter "clocksource=", 492 * and not introducing any OMAP specific interface. 493 */ 494 static int __init omap2_override_clocksource(char *str) 495 { 496 if (!str) 497 return 0; 498 /* 499 * For OMAP architecture, we only have two options 500 * - sync_32k (default) 501 * - gp_timer (sys_clk based) 502 */ 503 if (!strcmp(str, "gp_timer")) 504 use_gptimer_clksrc = true; 505 506 return 0; 507 } 508 early_param("clocksource", omap2_override_clocksource); 509