1 /* 2 * linux/arch/arm/mach-omap2/timer.c 3 * 4 * OMAP2 GP timer support. 5 * 6 * Copyright (C) 2009 Nokia Corporation 7 * 8 * Update to use new clocksource/clockevent layers 9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 10 * Copyright (C) 2007 MontaVista Software, Inc. 11 * 12 * Original driver: 13 * Copyright (C) 2005 Nokia Corporation 14 * Author: Paul Mundt <paul.mundt@nokia.com> 15 * Juha Yrjölä <juha.yrjola@nokia.com> 16 * OMAP Dual-mode timer framework support by Timo Teras 17 * 18 * Some parts based off of TI's 24xx code: 19 * 20 * Copyright (C) 2004-2009 Texas Instruments, Inc. 21 * 22 * Roughly modelled after the OMAP1 MPU timer code. 23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 24 * 25 * This file is subject to the terms and conditions of the GNU General Public 26 * License. See the file "COPYING" in the main directory of this archive 27 * for more details. 28 */ 29 #include <linux/init.h> 30 #include <linux/time.h> 31 #include <linux/interrupt.h> 32 #include <linux/err.h> 33 #include <linux/clk.h> 34 #include <linux/delay.h> 35 #include <linux/irq.h> 36 #include <linux/clocksource.h> 37 #include <linux/clockchips.h> 38 #include <linux/slab.h> 39 #include <linux/of.h> 40 #include <linux/of_address.h> 41 #include <linux/of_irq.h> 42 #include <linux/platform_device.h> 43 #include <linux/platform_data/dmtimer-omap.h> 44 #include <linux/sched_clock.h> 45 46 #include <asm/mach/time.h> 47 #include <asm/smp_twd.h> 48 49 #include "omap_hwmod.h" 50 #include "omap_device.h" 51 #include <plat/counter-32k.h> 52 #include <plat/dmtimer.h> 53 #include "omap-pm.h" 54 55 #include "soc.h" 56 #include "common.h" 57 #include "control.h" 58 #include "powerdomain.h" 59 #include "omap-secure.h" 60 61 #define REALTIME_COUNTER_BASE 0x48243200 62 #define INCREMENTER_NUMERATOR_OFFSET 0x10 63 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 64 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 65 66 /* Clockevent code */ 67 68 static struct omap_dm_timer clkev; 69 static struct clock_event_device clockevent_gpt; 70 71 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 72 static unsigned long arch_timer_freq; 73 74 void set_cntfreq(void) 75 { 76 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); 77 } 78 #endif 79 80 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 81 { 82 struct clock_event_device *evt = &clockevent_gpt; 83 84 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); 85 86 evt->event_handler(evt); 87 return IRQ_HANDLED; 88 } 89 90 static struct irqaction omap2_gp_timer_irq = { 91 .name = "gp_timer", 92 .flags = IRQF_TIMER | IRQF_IRQPOLL, 93 .handler = omap2_gp_timer_interrupt, 94 }; 95 96 static int omap2_gp_timer_set_next_event(unsigned long cycles, 97 struct clock_event_device *evt) 98 { 99 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 100 0xffffffff - cycles, OMAP_TIMER_POSTED); 101 102 return 0; 103 } 104 105 static int omap2_gp_timer_shutdown(struct clock_event_device *evt) 106 { 107 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); 108 return 0; 109 } 110 111 static int omap2_gp_timer_set_periodic(struct clock_event_device *evt) 112 { 113 u32 period; 114 115 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); 116 117 period = clkev.rate / HZ; 118 period -= 1; 119 /* Looks like we need to first set the load value separately */ 120 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period, 121 OMAP_TIMER_POSTED); 122 __omap_dm_timer_load_start(&clkev, 123 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 124 0xffffffff - period, OMAP_TIMER_POSTED); 125 return 0; 126 } 127 128 static struct clock_event_device clockevent_gpt = { 129 .features = CLOCK_EVT_FEAT_PERIODIC | 130 CLOCK_EVT_FEAT_ONESHOT, 131 .rating = 300, 132 .set_next_event = omap2_gp_timer_set_next_event, 133 .set_state_shutdown = omap2_gp_timer_shutdown, 134 .set_state_periodic = omap2_gp_timer_set_periodic, 135 .set_state_oneshot = omap2_gp_timer_shutdown, 136 .tick_resume = omap2_gp_timer_shutdown, 137 }; 138 139 static struct property device_disabled = { 140 .name = "status", 141 .length = sizeof("disabled"), 142 .value = "disabled", 143 }; 144 145 static const struct of_device_id omap_timer_match[] __initconst = { 146 { .compatible = "ti,omap2420-timer", }, 147 { .compatible = "ti,omap3430-timer", }, 148 { .compatible = "ti,omap4430-timer", }, 149 { .compatible = "ti,omap5430-timer", }, 150 { .compatible = "ti,dm814-timer", }, 151 { .compatible = "ti,dm816-timer", }, 152 { .compatible = "ti,am335x-timer", }, 153 { .compatible = "ti,am335x-timer-1ms", }, 154 { } 155 }; 156 157 /** 158 * omap_get_timer_dt - get a timer using device-tree 159 * @match - device-tree match structure for matching a device type 160 * @property - optional timer property to match 161 * 162 * Helper function to get a timer during early boot using device-tree for use 163 * as kernel system timer. Optionally, the property argument can be used to 164 * select a timer with a specific property. Once a timer is found then mark 165 * the timer node in device-tree as disabled, to prevent the kernel from 166 * registering this timer as a platform device and so no one else can use it. 167 */ 168 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match, 169 const char *property) 170 { 171 struct device_node *np; 172 173 for_each_matching_node(np, match) { 174 if (!of_device_is_available(np)) 175 continue; 176 177 if (property && !of_get_property(np, property, NULL)) 178 continue; 179 180 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || 181 of_get_property(np, "ti,timer-dsp", NULL) || 182 of_get_property(np, "ti,timer-pwm", NULL) || 183 of_get_property(np, "ti,timer-secure", NULL))) 184 continue; 185 186 of_add_property(np, &device_disabled); 187 return np; 188 } 189 190 return NULL; 191 } 192 193 /** 194 * omap_dmtimer_init - initialisation function when device tree is used 195 * 196 * For secure OMAP3 devices, timers with device type "timer-secure" cannot 197 * be used by the kernel as they are reserved. Therefore, to prevent the 198 * kernel registering these devices remove them dynamically from the device 199 * tree on boot. 200 */ 201 static void __init omap_dmtimer_init(void) 202 { 203 struct device_node *np; 204 205 if (!cpu_is_omap34xx()) 206 return; 207 208 /* If we are a secure device, remove any secure timer nodes */ 209 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { 210 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); 211 of_node_put(np); 212 } 213 } 214 215 /** 216 * omap_dm_timer_get_errata - get errata flags for a timer 217 * 218 * Get the timer errata flags that are specific to the OMAP device being used. 219 */ 220 static u32 __init omap_dm_timer_get_errata(void) 221 { 222 if (cpu_is_omap24xx()) 223 return 0; 224 225 return OMAP_TIMER_ERRATA_I103_I767; 226 } 227 228 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, 229 const char *fck_source, 230 const char *property, 231 const char **timer_name, 232 int posted) 233 { 234 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 235 const char *oh_name = NULL; 236 struct device_node *np; 237 struct omap_hwmod *oh; 238 struct resource irq, mem; 239 struct clk *src; 240 int r = 0; 241 242 if (of_have_populated_dt()) { 243 np = omap_get_timer_dt(omap_timer_match, property); 244 if (!np) 245 return -ENODEV; 246 247 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 248 if (!oh_name) 249 return -ENODEV; 250 251 timer->irq = irq_of_parse_and_map(np, 0); 252 if (!timer->irq) 253 return -ENXIO; 254 255 timer->io_base = of_iomap(np, 0); 256 257 of_node_put(np); 258 } else { 259 if (omap_dm_timer_reserve_systimer(timer->id)) 260 return -ENODEV; 261 262 sprintf(name, "timer%d", timer->id); 263 oh_name = name; 264 } 265 266 oh = omap_hwmod_lookup(oh_name); 267 if (!oh) 268 return -ENODEV; 269 270 *timer_name = oh->name; 271 272 if (!of_have_populated_dt()) { 273 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, 274 &irq); 275 if (r) 276 return -ENXIO; 277 timer->irq = irq.start; 278 279 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, 280 &mem); 281 if (r) 282 return -ENXIO; 283 284 /* Static mapping, never released */ 285 timer->io_base = ioremap(mem.start, mem.end - mem.start); 286 } 287 288 if (!timer->io_base) 289 return -ENXIO; 290 291 /* After the dmtimer is using hwmod these clocks won't be needed */ 292 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); 293 if (IS_ERR(timer->fclk)) 294 return PTR_ERR(timer->fclk); 295 296 src = clk_get(NULL, fck_source); 297 if (IS_ERR(src)) 298 return PTR_ERR(src); 299 300 WARN(clk_set_parent(timer->fclk, src) < 0, 301 "Cannot set timer parent clock, no PLL clock driver?"); 302 303 clk_put(src); 304 305 omap_hwmod_setup_one(oh_name); 306 omap_hwmod_enable(oh); 307 __omap_dm_timer_init_regs(timer); 308 309 if (posted) 310 __omap_dm_timer_enable_posted(timer); 311 312 /* Check that the intended posted configuration matches the actual */ 313 if (posted != timer->posted) 314 return -EINVAL; 315 316 timer->rate = clk_get_rate(timer->fclk); 317 timer->reserved = 1; 318 319 return r; 320 } 321 322 static void __init omap2_gp_clockevent_init(int gptimer_id, 323 const char *fck_source, 324 const char *property) 325 { 326 int res; 327 328 clkev.id = gptimer_id; 329 clkev.errata = omap_dm_timer_get_errata(); 330 331 /* 332 * For clock-event timers we never read the timer counter and 333 * so we are not impacted by errata i103 and i767. Therefore, 334 * we can safely ignore this errata for clock-event timers. 335 */ 336 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); 337 338 res = omap_dm_timer_init_one(&clkev, fck_source, property, 339 &clockevent_gpt.name, OMAP_TIMER_POSTED); 340 BUG_ON(res); 341 342 omap2_gp_timer_irq.dev_id = &clkev; 343 setup_irq(clkev.irq, &omap2_gp_timer_irq); 344 345 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); 346 347 clockevent_gpt.cpumask = cpu_possible_mask; 348 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); 349 clockevents_config_and_register(&clockevent_gpt, clkev.rate, 350 3, /* Timer internal resynch latency */ 351 0xffffffff); 352 353 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, 354 clkev.rate); 355 } 356 357 /* Clocksource code */ 358 static struct omap_dm_timer clksrc; 359 static bool use_gptimer_clksrc __initdata; 360 361 /* 362 * clocksource 363 */ 364 static cycle_t clocksource_read_cycles(struct clocksource *cs) 365 { 366 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 367 OMAP_TIMER_NONPOSTED); 368 } 369 370 static struct clocksource clocksource_gpt = { 371 .rating = 300, 372 .read = clocksource_read_cycles, 373 .mask = CLOCKSOURCE_MASK(32), 374 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 375 }; 376 377 static u64 notrace dmtimer_read_sched_clock(void) 378 { 379 if (clksrc.reserved) 380 return __omap_dm_timer_read_counter(&clksrc, 381 OMAP_TIMER_NONPOSTED); 382 383 return 0; 384 } 385 386 static const struct of_device_id omap_counter_match[] __initconst = { 387 { .compatible = "ti,omap-counter32k", }, 388 { } 389 }; 390 391 /* Setup free-running counter for clocksource */ 392 static int __init __maybe_unused omap2_sync32k_clocksource_init(void) 393 { 394 int ret; 395 struct device_node *np = NULL; 396 struct omap_hwmod *oh; 397 void __iomem *vbase; 398 const char *oh_name = "counter_32k"; 399 400 /* 401 * If device-tree is present, then search the DT blob 402 * to see if the 32kHz counter is supported. 403 */ 404 if (of_have_populated_dt()) { 405 np = omap_get_timer_dt(omap_counter_match, NULL); 406 if (!np) 407 return -ENODEV; 408 409 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 410 if (!oh_name) 411 return -ENODEV; 412 } 413 414 /* 415 * First check hwmod data is available for sync32k counter 416 */ 417 oh = omap_hwmod_lookup(oh_name); 418 if (!oh || oh->slaves_cnt == 0) 419 return -ENODEV; 420 421 omap_hwmod_setup_one(oh_name); 422 423 if (np) { 424 vbase = of_iomap(np, 0); 425 of_node_put(np); 426 } else { 427 vbase = omap_hwmod_get_mpu_rt_va(oh); 428 } 429 430 if (!vbase) { 431 pr_warn("%s: failed to get counter_32k resource\n", __func__); 432 return -ENXIO; 433 } 434 435 ret = omap_hwmod_enable(oh); 436 if (ret) { 437 pr_warn("%s: failed to enable counter_32k module (%d)\n", 438 __func__, ret); 439 return ret; 440 } 441 442 ret = omap_init_clocksource_32k(vbase); 443 if (ret) { 444 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", 445 __func__, ret); 446 omap_hwmod_idle(oh); 447 } 448 449 return ret; 450 } 451 452 static void __init omap2_gptimer_clocksource_init(int gptimer_id, 453 const char *fck_source, 454 const char *property) 455 { 456 int res; 457 458 clksrc.id = gptimer_id; 459 clksrc.errata = omap_dm_timer_get_errata(); 460 461 res = omap_dm_timer_init_one(&clksrc, fck_source, property, 462 &clocksource_gpt.name, 463 OMAP_TIMER_NONPOSTED); 464 BUG_ON(res); 465 466 __omap_dm_timer_load_start(&clksrc, 467 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 468 OMAP_TIMER_NONPOSTED); 469 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate); 470 471 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 472 pr_err("Could not register clocksource %s\n", 473 clocksource_gpt.name); 474 else 475 pr_info("OMAP clocksource: %s at %lu Hz\n", 476 clocksource_gpt.name, clksrc.rate); 477 } 478 479 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 480 /* 481 * The realtime counter also called master counter, is a free-running 482 * counter, which is related to real time. It produces the count used 483 * by the CPU local timer peripherals in the MPU cluster. The timer counts 484 * at a rate of 6.144 MHz. Because the device operates on different clocks 485 * in different power modes, the master counter shifts operation between 486 * clocks, adjusting the increment per clock in hardware accordingly to 487 * maintain a constant count rate. 488 */ 489 static void __init realtime_counter_init(void) 490 { 491 void __iomem *base; 492 static struct clk *sys_clk; 493 unsigned long rate; 494 unsigned int reg; 495 unsigned long long num, den; 496 497 base = ioremap(REALTIME_COUNTER_BASE, SZ_32); 498 if (!base) { 499 pr_err("%s: ioremap failed\n", __func__); 500 return; 501 } 502 sys_clk = clk_get(NULL, "sys_clkin"); 503 if (IS_ERR(sys_clk)) { 504 pr_err("%s: failed to get system clock handle\n", __func__); 505 iounmap(base); 506 return; 507 } 508 509 rate = clk_get_rate(sys_clk); 510 511 if (soc_is_dra7xx()) { 512 /* 513 * Errata i856 says the 32.768KHz crystal does not start at 514 * power on, so the CPU falls back to an emulated 32KHz clock 515 * based on sysclk / 610 instead. This causes the master counter 516 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 517 * (OR sysclk * 75 / 244) 518 * 519 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions. 520 * Of course any board built without a populated 32.768KHz 521 * crystal would also need this fix even if the CPU is fixed 522 * later. 523 * 524 * Either case can be detected by using the two speedselect bits 525 * If they are not 0, then the 32.768KHz clock driving the 526 * coarse counter that corrects the fine counter every time it 527 * ticks is actually rate/610 rather than 32.768KHz and we 528 * should compensate to avoid the 570ppm (at 20MHz, much worse 529 * at other rates) too fast system time. 530 */ 531 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); 532 if (reg & DRA7_SPEEDSELECT_MASK) { 533 num = 75; 534 den = 244; 535 goto sysclk1_based; 536 } 537 } 538 539 /* Numerator/denumerator values refer TRM Realtime Counter section */ 540 switch (rate) { 541 case 12000000: 542 num = 64; 543 den = 125; 544 break; 545 case 13000000: 546 num = 768; 547 den = 1625; 548 break; 549 case 19200000: 550 num = 8; 551 den = 25; 552 break; 553 case 20000000: 554 num = 192; 555 den = 625; 556 break; 557 case 26000000: 558 num = 384; 559 den = 1625; 560 break; 561 case 27000000: 562 num = 256; 563 den = 1125; 564 break; 565 case 38400000: 566 default: 567 /* Program it for 38.4 MHz */ 568 num = 4; 569 den = 25; 570 break; 571 } 572 573 sysclk1_based: 574 /* Program numerator and denumerator registers */ 575 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & 576 NUMERATOR_DENUMERATOR_MASK; 577 reg |= num; 578 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET); 579 580 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & 581 NUMERATOR_DENUMERATOR_MASK; 582 reg |= den; 583 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); 584 585 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den); 586 set_cntfreq(); 587 588 iounmap(base); 589 } 590 #else 591 static inline void __init realtime_counter_init(void) 592 {} 593 #endif 594 595 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ 596 clksrc_nr, clksrc_src, clksrc_prop) \ 597 void __init omap##name##_gptimer_timer_init(void) \ 598 { \ 599 omap_clk_init(); \ 600 omap_dmtimer_init(); \ 601 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 602 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ 603 clksrc_prop); \ 604 } 605 606 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ 607 clksrc_nr, clksrc_src, clksrc_prop) \ 608 void __init omap##name##_sync32k_timer_init(void) \ 609 { \ 610 omap_clk_init(); \ 611 omap_dmtimer_init(); \ 612 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 613 /* Enable the use of clocksource="gp_timer" kernel parameter */ \ 614 if (use_gptimer_clksrc) \ 615 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ 616 clksrc_prop); \ 617 else \ 618 omap2_sync32k_clocksource_init(); \ 619 } 620 621 #ifdef CONFIG_ARCH_OMAP2 622 OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon", 623 2, "timer_sys_ck", NULL); 624 #endif /* CONFIG_ARCH_OMAP2 */ 625 626 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) 627 OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon", 628 2, "timer_sys_ck", NULL); 629 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure", 630 2, "timer_sys_ck", NULL); 631 #endif /* CONFIG_ARCH_OMAP3 */ 632 633 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \ 634 defined(CONFIG_SOC_AM43XX) 635 OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL, 636 1, "timer_sys_ck", "ti,timer-alwon"); 637 #endif 638 639 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 640 defined(CONFIG_SOC_DRA7XX) 641 static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", 642 2, "sys_clkin_ck", NULL); 643 #endif 644 645 #ifdef CONFIG_ARCH_OMAP4 646 #ifdef CONFIG_HAVE_ARM_TWD 647 void __init omap4_local_timer_init(void) 648 { 649 omap4_sync32k_timer_init(); 650 clocksource_of_init(); 651 } 652 #else 653 void __init omap4_local_timer_init(void) 654 { 655 omap4_sync32k_timer_init(); 656 } 657 #endif /* CONFIG_HAVE_ARM_TWD */ 658 #endif /* CONFIG_ARCH_OMAP4 */ 659 660 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) 661 void __init omap5_realtime_timer_init(void) 662 { 663 omap4_sync32k_timer_init(); 664 realtime_counter_init(); 665 666 clocksource_of_init(); 667 } 668 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ 669 670 /** 671 * omap_timer_init - build and register timer device with an 672 * associated timer hwmod 673 * @oh: timer hwmod pointer to be used to build timer device 674 * @user: parameter that can be passed from calling hwmod API 675 * 676 * Called by omap_hwmod_for_each_by_class to register each of the timer 677 * devices present in the system. The number of timer devices is known 678 * by parsing through the hwmod database for a given class name. At the 679 * end of function call memory is allocated for timer device and it is 680 * registered to the framework ready to be proved by the driver. 681 */ 682 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) 683 { 684 int id; 685 int ret = 0; 686 char *name = "omap_timer"; 687 struct dmtimer_platform_data *pdata; 688 struct platform_device *pdev; 689 struct omap_timer_capability_dev_attr *timer_dev_attr; 690 691 pr_debug("%s: %s\n", __func__, oh->name); 692 693 /* on secure device, do not register secure timer */ 694 timer_dev_attr = oh->dev_attr; 695 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) 696 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) 697 return ret; 698 699 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 700 if (!pdata) { 701 pr_err("%s: No memory for [%s]\n", __func__, oh->name); 702 return -ENOMEM; 703 } 704 705 /* 706 * Extract the IDs from name field in hwmod database 707 * and use the same for constructing ids' for the 708 * timer devices. In a way, we are avoiding usage of 709 * static variable witin the function to do the same. 710 * CAUTION: We have to be careful and make sure the 711 * name in hwmod database does not change in which case 712 * we might either make corresponding change here or 713 * switch back static variable mechanism. 714 */ 715 sscanf(oh->name, "timer%2d", &id); 716 717 if (timer_dev_attr) 718 pdata->timer_capability = timer_dev_attr->timer_capability; 719 720 pdata->timer_errata = omap_dm_timer_get_errata(); 721 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; 722 723 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata)); 724 725 if (IS_ERR(pdev)) { 726 pr_err("%s: Can't build omap_device for %s: %s.\n", 727 __func__, name, oh->name); 728 ret = -EINVAL; 729 } 730 731 kfree(pdata); 732 733 return ret; 734 } 735 736 /** 737 * omap2_dm_timer_init - top level regular device initialization 738 * 739 * Uses dedicated hwmod api to parse through hwmod database for 740 * given class name and then build and register the timer device. 741 */ 742 static int __init omap2_dm_timer_init(void) 743 { 744 int ret; 745 746 /* If dtb is there, the devices will be created dynamically */ 747 if (of_have_populated_dt()) 748 return -ENODEV; 749 750 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); 751 if (unlikely(ret)) { 752 pr_err("%s: device registration failed.\n", __func__); 753 return -EINVAL; 754 } 755 756 return 0; 757 } 758 omap_arch_initcall(omap2_dm_timer_init); 759 760 /** 761 * omap2_override_clocksource - clocksource override with user configuration 762 * 763 * Allows user to override default clocksource, using kernel parameter 764 * clocksource="gp_timer" (For all OMAP2PLUS architectures) 765 * 766 * Note that, here we are using same standard kernel parameter "clocksource=", 767 * and not introducing any OMAP specific interface. 768 */ 769 static int __init omap2_override_clocksource(char *str) 770 { 771 if (!str) 772 return 0; 773 /* 774 * For OMAP architecture, we only have two options 775 * - sync_32k (default) 776 * - gp_timer (sys_clk based) 777 */ 778 if (!strcmp(str, "gp_timer")) 779 use_gptimer_clksrc = true; 780 781 return 0; 782 } 783 early_param("clocksource", omap2_override_clocksource); 784