1 /* 2 * linux/arch/arm/mach-omap2/timer.c 3 * 4 * OMAP2 GP timer support. 5 * 6 * Copyright (C) 2009 Nokia Corporation 7 * 8 * Update to use new clocksource/clockevent layers 9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 10 * Copyright (C) 2007 MontaVista Software, Inc. 11 * 12 * Original driver: 13 * Copyright (C) 2005 Nokia Corporation 14 * Author: Paul Mundt <paul.mundt@nokia.com> 15 * Juha Yrjölä <juha.yrjola@nokia.com> 16 * OMAP Dual-mode timer framework support by Timo Teras 17 * 18 * Some parts based off of TI's 24xx code: 19 * 20 * Copyright (C) 2004-2009 Texas Instruments, Inc. 21 * 22 * Roughly modelled after the OMAP1 MPU timer code. 23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 24 * 25 * This file is subject to the terms and conditions of the GNU General Public 26 * License. See the file "COPYING" in the main directory of this archive 27 * for more details. 28 */ 29 #include <linux/init.h> 30 #include <linux/time.h> 31 #include <linux/interrupt.h> 32 #include <linux/err.h> 33 #include <linux/clk.h> 34 #include <linux/delay.h> 35 #include <linux/irq.h> 36 #include <linux/clocksource.h> 37 #include <linux/clockchips.h> 38 #include <linux/slab.h> 39 40 #include <asm/mach/time.h> 41 #include <plat/dmtimer.h> 42 #include <asm/smp_twd.h> 43 #include <asm/sched_clock.h> 44 #include "common.h" 45 #include <plat/omap_hwmod.h> 46 #include <plat/omap_device.h> 47 #include <plat/omap-pm.h> 48 49 #include "powerdomain.h" 50 51 /* Parent clocks, eventually these will come from the clock framework */ 52 53 #define OMAP2_MPU_SOURCE "sys_ck" 54 #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE 55 #define OMAP4_MPU_SOURCE "sys_clkin_ck" 56 #define OMAP2_32K_SOURCE "func_32k_ck" 57 #define OMAP3_32K_SOURCE "omap_32k_fck" 58 #define OMAP4_32K_SOURCE "sys_32k_ck" 59 60 #ifdef CONFIG_OMAP_32K_TIMER 61 #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE 62 #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE 63 #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE 64 #define OMAP3_SECURE_TIMER 12 65 #else 66 #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE 67 #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE 68 #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE 69 #define OMAP3_SECURE_TIMER 1 70 #endif 71 72 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ 73 #define MAX_GPTIMER_ID 12 74 75 static u32 sys_timer_reserved; 76 77 /* Clockevent code */ 78 79 static struct omap_dm_timer clkev; 80 static struct clock_event_device clockevent_gpt; 81 82 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 83 { 84 struct clock_event_device *evt = &clockevent_gpt; 85 86 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); 87 88 evt->event_handler(evt); 89 return IRQ_HANDLED; 90 } 91 92 static struct irqaction omap2_gp_timer_irq = { 93 .name = "gp timer", 94 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 95 .handler = omap2_gp_timer_interrupt, 96 }; 97 98 static int omap2_gp_timer_set_next_event(unsigned long cycles, 99 struct clock_event_device *evt) 100 { 101 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 102 0xffffffff - cycles, 1); 103 104 return 0; 105 } 106 107 static void omap2_gp_timer_set_mode(enum clock_event_mode mode, 108 struct clock_event_device *evt) 109 { 110 u32 period; 111 112 __omap_dm_timer_stop(&clkev, 1, clkev.rate); 113 114 switch (mode) { 115 case CLOCK_EVT_MODE_PERIODIC: 116 period = clkev.rate / HZ; 117 period -= 1; 118 /* Looks like we need to first set the load value separately */ 119 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 120 0xffffffff - period, 1); 121 __omap_dm_timer_load_start(&clkev, 122 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 123 0xffffffff - period, 1); 124 break; 125 case CLOCK_EVT_MODE_ONESHOT: 126 break; 127 case CLOCK_EVT_MODE_UNUSED: 128 case CLOCK_EVT_MODE_SHUTDOWN: 129 case CLOCK_EVT_MODE_RESUME: 130 break; 131 } 132 } 133 134 static struct clock_event_device clockevent_gpt = { 135 .name = "gp timer", 136 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 137 .shift = 32, 138 .set_next_event = omap2_gp_timer_set_next_event, 139 .set_mode = omap2_gp_timer_set_mode, 140 }; 141 142 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, 143 int gptimer_id, 144 const char *fck_source) 145 { 146 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 147 struct omap_hwmod *oh; 148 struct resource irq_rsrc, mem_rsrc; 149 size_t size; 150 int res = 0; 151 int r; 152 153 sprintf(name, "timer%d", gptimer_id); 154 omap_hwmod_setup_one(name); 155 oh = omap_hwmod_lookup(name); 156 if (!oh) 157 return -ENODEV; 158 159 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc); 160 if (r) 161 return -ENXIO; 162 timer->irq = irq_rsrc.start; 163 164 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc); 165 if (r) 166 return -ENXIO; 167 timer->phys_base = mem_rsrc.start; 168 size = mem_rsrc.end - mem_rsrc.start; 169 170 /* Static mapping, never released */ 171 timer->io_base = ioremap(timer->phys_base, size); 172 if (!timer->io_base) 173 return -ENXIO; 174 175 /* After the dmtimer is using hwmod these clocks won't be needed */ 176 sprintf(name, "gpt%d_fck", gptimer_id); 177 timer->fclk = clk_get(NULL, name); 178 if (IS_ERR(timer->fclk)) 179 return -ENODEV; 180 181 omap_hwmod_enable(oh); 182 183 sys_timer_reserved |= (1 << (gptimer_id - 1)); 184 185 if (gptimer_id != 12) { 186 struct clk *src; 187 188 src = clk_get(NULL, fck_source); 189 if (IS_ERR(src)) { 190 res = -EINVAL; 191 } else { 192 res = __omap_dm_timer_set_source(timer->fclk, src); 193 if (IS_ERR_VALUE(res)) 194 pr_warning("%s: timer%i cannot set source\n", 195 __func__, gptimer_id); 196 clk_put(src); 197 } 198 } 199 __omap_dm_timer_init_regs(timer); 200 __omap_dm_timer_reset(timer, 1, 1); 201 timer->posted = 1; 202 203 timer->rate = clk_get_rate(timer->fclk); 204 205 timer->reserved = 1; 206 207 return res; 208 } 209 210 static void __init omap2_gp_clockevent_init(int gptimer_id, 211 const char *fck_source) 212 { 213 int res; 214 215 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source); 216 BUG_ON(res); 217 218 omap2_gp_timer_irq.dev_id = (void *)&clkev; 219 setup_irq(clkev.irq, &omap2_gp_timer_irq); 220 221 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); 222 223 clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, 224 clockevent_gpt.shift); 225 clockevent_gpt.max_delta_ns = 226 clockevent_delta2ns(0xffffffff, &clockevent_gpt); 227 clockevent_gpt.min_delta_ns = 228 clockevent_delta2ns(3, &clockevent_gpt); 229 /* Timer internal resynch latency. */ 230 231 clockevent_gpt.cpumask = cpumask_of(0); 232 clockevents_register_device(&clockevent_gpt); 233 234 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", 235 gptimer_id, clkev.rate); 236 } 237 238 /* Clocksource code */ 239 240 #ifdef CONFIG_OMAP_32K_TIMER 241 /* 242 * When 32k-timer is enabled, don't use GPTimer for clocksource 243 * instead, just leave default clocksource which uses the 32k 244 * sync counter. See clocksource setup in plat-omap/counter_32k.c 245 */ 246 247 static void __init omap2_gp_clocksource_init(int unused, const char *dummy) 248 { 249 omap_init_clocksource_32k(); 250 } 251 252 #else 253 254 static struct omap_dm_timer clksrc; 255 256 /* 257 * clocksource 258 */ 259 static cycle_t clocksource_read_cycles(struct clocksource *cs) 260 { 261 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1); 262 } 263 264 static struct clocksource clocksource_gpt = { 265 .name = "gp timer", 266 .rating = 300, 267 .read = clocksource_read_cycles, 268 .mask = CLOCKSOURCE_MASK(32), 269 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 270 }; 271 272 static u32 notrace dmtimer_read_sched_clock(void) 273 { 274 if (clksrc.reserved) 275 return __omap_dm_timer_read_counter(&clksrc, 1); 276 277 return 0; 278 } 279 280 /* Setup free-running counter for clocksource */ 281 static void __init omap2_gp_clocksource_init(int gptimer_id, 282 const char *fck_source) 283 { 284 int res; 285 286 res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source); 287 BUG_ON(res); 288 289 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", 290 gptimer_id, clksrc.rate); 291 292 __omap_dm_timer_load_start(&clksrc, 293 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1); 294 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); 295 296 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 297 pr_err("Could not register clocksource %s\n", 298 clocksource_gpt.name); 299 } 300 #endif 301 302 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ 303 clksrc_nr, clksrc_src) \ 304 static void __init omap##name##_timer_init(void) \ 305 { \ 306 omap2_gp_clockevent_init((clkev_nr), clkev_src); \ 307 omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \ 308 } 309 310 #define OMAP_SYS_TIMER(name) \ 311 struct sys_timer omap##name##_timer = { \ 312 .init = omap##name##_timer_init, \ 313 }; 314 315 #ifdef CONFIG_ARCH_OMAP2 316 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE) 317 OMAP_SYS_TIMER(2) 318 #endif 319 320 #ifdef CONFIG_ARCH_OMAP3 321 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE) 322 OMAP_SYS_TIMER(3) 323 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, 324 2, OMAP3_MPU_SOURCE) 325 OMAP_SYS_TIMER(3_secure) 326 #endif 327 328 #ifdef CONFIG_ARCH_OMAP4 329 #ifdef CONFIG_LOCAL_TIMERS 330 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 331 OMAP44XX_LOCAL_TWD_BASE, 332 OMAP44XX_IRQ_LOCALTIMER); 333 #endif 334 335 static void __init omap4_timer_init(void) 336 { 337 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); 338 omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE); 339 #ifdef CONFIG_LOCAL_TIMERS 340 /* Local timers are not supprted on OMAP4430 ES1.0 */ 341 if (omap_rev() != OMAP4430_REV_ES1_0) { 342 int err; 343 344 err = twd_local_timer_register(&twd_local_timer); 345 if (err) 346 pr_err("twd_local_timer_register failed %d\n", err); 347 } 348 #endif 349 } 350 OMAP_SYS_TIMER(4) 351 #endif 352 353 /** 354 * omap2_dm_timer_set_src - change the timer input clock source 355 * @pdev: timer platform device pointer 356 * @source: array index of parent clock source 357 */ 358 static int omap2_dm_timer_set_src(struct platform_device *pdev, int source) 359 { 360 int ret; 361 struct dmtimer_platform_data *pdata = pdev->dev.platform_data; 362 struct clk *fclk, *parent; 363 char *parent_name = NULL; 364 365 fclk = clk_get(&pdev->dev, "fck"); 366 if (IS_ERR_OR_NULL(fclk)) { 367 dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n", 368 __func__, __LINE__); 369 return -EINVAL; 370 } 371 372 switch (source) { 373 case OMAP_TIMER_SRC_SYS_CLK: 374 parent_name = "sys_ck"; 375 break; 376 377 case OMAP_TIMER_SRC_32_KHZ: 378 parent_name = "32k_ck"; 379 break; 380 381 case OMAP_TIMER_SRC_EXT_CLK: 382 if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) { 383 parent_name = "alt_ck"; 384 break; 385 } 386 dev_err(&pdev->dev, "%s: %d: invalid clk src.\n", 387 __func__, __LINE__); 388 clk_put(fclk); 389 return -EINVAL; 390 } 391 392 parent = clk_get(&pdev->dev, parent_name); 393 if (IS_ERR_OR_NULL(parent)) { 394 dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n", 395 __func__, __LINE__, parent_name); 396 clk_put(fclk); 397 return -EINVAL; 398 } 399 400 ret = clk_set_parent(fclk, parent); 401 if (IS_ERR_VALUE(ret)) { 402 dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n", 403 __func__, parent_name); 404 ret = -EINVAL; 405 } 406 407 clk_put(parent); 408 clk_put(fclk); 409 410 return ret; 411 } 412 413 /** 414 * omap_timer_init - build and register timer device with an 415 * associated timer hwmod 416 * @oh: timer hwmod pointer to be used to build timer device 417 * @user: parameter that can be passed from calling hwmod API 418 * 419 * Called by omap_hwmod_for_each_by_class to register each of the timer 420 * devices present in the system. The number of timer devices is known 421 * by parsing through the hwmod database for a given class name. At the 422 * end of function call memory is allocated for timer device and it is 423 * registered to the framework ready to be proved by the driver. 424 */ 425 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) 426 { 427 int id; 428 int ret = 0; 429 char *name = "omap_timer"; 430 struct dmtimer_platform_data *pdata; 431 struct platform_device *pdev; 432 struct omap_timer_capability_dev_attr *timer_dev_attr; 433 struct powerdomain *pwrdm; 434 435 pr_debug("%s: %s\n", __func__, oh->name); 436 437 /* on secure device, do not register secure timer */ 438 timer_dev_attr = oh->dev_attr; 439 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) 440 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) 441 return ret; 442 443 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 444 if (!pdata) { 445 pr_err("%s: No memory for [%s]\n", __func__, oh->name); 446 return -ENOMEM; 447 } 448 449 /* 450 * Extract the IDs from name field in hwmod database 451 * and use the same for constructing ids' for the 452 * timer devices. In a way, we are avoiding usage of 453 * static variable witin the function to do the same. 454 * CAUTION: We have to be careful and make sure the 455 * name in hwmod database does not change in which case 456 * we might either make corresponding change here or 457 * switch back static variable mechanism. 458 */ 459 sscanf(oh->name, "timer%2d", &id); 460 461 pdata->set_timer_src = omap2_dm_timer_set_src; 462 pdata->timer_ip_version = oh->class->rev; 463 464 /* Mark clocksource and clockevent timers as reserved */ 465 if ((sys_timer_reserved >> (id - 1)) & 0x1) 466 pdata->reserved = 1; 467 468 pwrdm = omap_hwmod_get_pwrdm(oh); 469 pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm); 470 #ifdef CONFIG_PM 471 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; 472 #endif 473 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), 474 NULL, 0, 0); 475 476 if (IS_ERR(pdev)) { 477 pr_err("%s: Can't build omap_device for %s: %s.\n", 478 __func__, name, oh->name); 479 ret = -EINVAL; 480 } 481 482 kfree(pdata); 483 484 return ret; 485 } 486 487 /** 488 * omap2_dm_timer_init - top level regular device initialization 489 * 490 * Uses dedicated hwmod api to parse through hwmod database for 491 * given class name and then build and register the timer device. 492 */ 493 static int __init omap2_dm_timer_init(void) 494 { 495 int ret; 496 497 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); 498 if (unlikely(ret)) { 499 pr_err("%s: device registration failed.\n", __func__); 500 return -EINVAL; 501 } 502 503 return 0; 504 } 505 arch_initcall(omap2_dm_timer_init); 506