1 /* 2 * linux/arch/arm/mach-omap2/timer.c 3 * 4 * OMAP2 GP timer support. 5 * 6 * Copyright (C) 2009 Nokia Corporation 7 * 8 * Update to use new clocksource/clockevent layers 9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 10 * Copyright (C) 2007 MontaVista Software, Inc. 11 * 12 * Original driver: 13 * Copyright (C) 2005 Nokia Corporation 14 * Author: Paul Mundt <paul.mundt@nokia.com> 15 * Juha Yrjölä <juha.yrjola@nokia.com> 16 * OMAP Dual-mode timer framework support by Timo Teras 17 * 18 * Some parts based off of TI's 24xx code: 19 * 20 * Copyright (C) 2004-2009 Texas Instruments, Inc. 21 * 22 * Roughly modelled after the OMAP1 MPU timer code. 23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 24 * 25 * This file is subject to the terms and conditions of the GNU General Public 26 * License. See the file "COPYING" in the main directory of this archive 27 * for more details. 28 */ 29 #include <linux/init.h> 30 #include <linux/time.h> 31 #include <linux/interrupt.h> 32 #include <linux/err.h> 33 #include <linux/clk.h> 34 #include <linux/delay.h> 35 #include <linux/irq.h> 36 #include <linux/clocksource.h> 37 #include <linux/clockchips.h> 38 #include <linux/slab.h> 39 40 #include <asm/mach/time.h> 41 #include <plat/dmtimer.h> 42 #include <asm/smp_twd.h> 43 #include <asm/sched_clock.h> 44 #include <asm/arch_timer.h> 45 #include "common.h" 46 #include <plat/omap_hwmod.h> 47 #include <plat/omap_device.h> 48 #include <plat/omap-pm.h> 49 50 #include "powerdomain.h" 51 52 /* Parent clocks, eventually these will come from the clock framework */ 53 54 #define OMAP2_MPU_SOURCE "sys_ck" 55 #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE 56 #define OMAP4_MPU_SOURCE "sys_clkin_ck" 57 #define OMAP2_32K_SOURCE "func_32k_ck" 58 #define OMAP3_32K_SOURCE "omap_32k_fck" 59 #define OMAP4_32K_SOURCE "sys_32k_ck" 60 61 #ifdef CONFIG_OMAP_32K_TIMER 62 #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE 63 #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE 64 #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE 65 #define OMAP3_SECURE_TIMER 12 66 #else 67 #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE 68 #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE 69 #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE 70 #define OMAP3_SECURE_TIMER 1 71 #endif 72 73 #define REALTIME_COUNTER_BASE 0x48243200 74 #define INCREMENTER_NUMERATOR_OFFSET 0x10 75 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 76 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 77 78 /* Clockevent code */ 79 80 static struct omap_dm_timer clkev; 81 static struct clock_event_device clockevent_gpt; 82 83 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 84 { 85 struct clock_event_device *evt = &clockevent_gpt; 86 87 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); 88 89 evt->event_handler(evt); 90 return IRQ_HANDLED; 91 } 92 93 static struct irqaction omap2_gp_timer_irq = { 94 .name = "gp_timer", 95 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 96 .handler = omap2_gp_timer_interrupt, 97 }; 98 99 static int omap2_gp_timer_set_next_event(unsigned long cycles, 100 struct clock_event_device *evt) 101 { 102 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 103 0xffffffff - cycles, 1); 104 105 return 0; 106 } 107 108 static void omap2_gp_timer_set_mode(enum clock_event_mode mode, 109 struct clock_event_device *evt) 110 { 111 u32 period; 112 113 __omap_dm_timer_stop(&clkev, 1, clkev.rate); 114 115 switch (mode) { 116 case CLOCK_EVT_MODE_PERIODIC: 117 period = clkev.rate / HZ; 118 period -= 1; 119 /* Looks like we need to first set the load value separately */ 120 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 121 0xffffffff - period, 1); 122 __omap_dm_timer_load_start(&clkev, 123 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 124 0xffffffff - period, 1); 125 break; 126 case CLOCK_EVT_MODE_ONESHOT: 127 break; 128 case CLOCK_EVT_MODE_UNUSED: 129 case CLOCK_EVT_MODE_SHUTDOWN: 130 case CLOCK_EVT_MODE_RESUME: 131 break; 132 } 133 } 134 135 static struct clock_event_device clockevent_gpt = { 136 .name = "gp_timer", 137 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 138 .shift = 32, 139 .rating = 300, 140 .set_next_event = omap2_gp_timer_set_next_event, 141 .set_mode = omap2_gp_timer_set_mode, 142 }; 143 144 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, 145 int gptimer_id, 146 const char *fck_source) 147 { 148 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 149 struct omap_hwmod *oh; 150 struct resource irq_rsrc, mem_rsrc; 151 size_t size; 152 int res = 0; 153 int r; 154 155 sprintf(name, "timer%d", gptimer_id); 156 omap_hwmod_setup_one(name); 157 oh = omap_hwmod_lookup(name); 158 if (!oh) 159 return -ENODEV; 160 161 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc); 162 if (r) 163 return -ENXIO; 164 timer->irq = irq_rsrc.start; 165 166 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc); 167 if (r) 168 return -ENXIO; 169 timer->phys_base = mem_rsrc.start; 170 size = mem_rsrc.end - mem_rsrc.start; 171 172 /* Static mapping, never released */ 173 timer->io_base = ioremap(timer->phys_base, size); 174 if (!timer->io_base) 175 return -ENXIO; 176 177 /* After the dmtimer is using hwmod these clocks won't be needed */ 178 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); 179 if (IS_ERR(timer->fclk)) 180 return -ENODEV; 181 182 omap_hwmod_enable(oh); 183 184 if (omap_dm_timer_reserve_systimer(gptimer_id)) 185 return -ENODEV; 186 187 if (gptimer_id != 12) { 188 struct clk *src; 189 190 src = clk_get(NULL, fck_source); 191 if (IS_ERR(src)) { 192 res = -EINVAL; 193 } else { 194 res = __omap_dm_timer_set_source(timer->fclk, src); 195 if (IS_ERR_VALUE(res)) 196 pr_warning("%s: timer%i cannot set source\n", 197 __func__, gptimer_id); 198 clk_put(src); 199 } 200 } 201 __omap_dm_timer_init_regs(timer); 202 __omap_dm_timer_reset(timer, 1, 1); 203 timer->posted = 1; 204 205 timer->rate = clk_get_rate(timer->fclk); 206 207 timer->reserved = 1; 208 209 return res; 210 } 211 212 static void __init omap2_gp_clockevent_init(int gptimer_id, 213 const char *fck_source) 214 { 215 int res; 216 217 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source); 218 BUG_ON(res); 219 220 omap2_gp_timer_irq.dev_id = (void *)&clkev; 221 setup_irq(clkev.irq, &omap2_gp_timer_irq); 222 223 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); 224 225 clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, 226 clockevent_gpt.shift); 227 clockevent_gpt.max_delta_ns = 228 clockevent_delta2ns(0xffffffff, &clockevent_gpt); 229 clockevent_gpt.min_delta_ns = 230 clockevent_delta2ns(3, &clockevent_gpt); 231 /* Timer internal resynch latency. */ 232 233 clockevent_gpt.cpumask = cpu_possible_mask; 234 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); 235 clockevents_register_device(&clockevent_gpt); 236 237 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", 238 gptimer_id, clkev.rate); 239 } 240 241 /* Clocksource code */ 242 static struct omap_dm_timer clksrc; 243 static bool use_gptimer_clksrc; 244 245 /* 246 * clocksource 247 */ 248 static cycle_t clocksource_read_cycles(struct clocksource *cs) 249 { 250 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1); 251 } 252 253 static struct clocksource clocksource_gpt = { 254 .name = "gp_timer", 255 .rating = 300, 256 .read = clocksource_read_cycles, 257 .mask = CLOCKSOURCE_MASK(32), 258 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 259 }; 260 261 static u32 notrace dmtimer_read_sched_clock(void) 262 { 263 if (clksrc.reserved) 264 return __omap_dm_timer_read_counter(&clksrc, 1); 265 266 return 0; 267 } 268 269 #ifdef CONFIG_OMAP_32K_TIMER 270 /* Setup free-running counter for clocksource */ 271 static int __init omap2_sync32k_clocksource_init(void) 272 { 273 int ret; 274 struct omap_hwmod *oh; 275 void __iomem *vbase; 276 const char *oh_name = "counter_32k"; 277 278 /* 279 * First check hwmod data is available for sync32k counter 280 */ 281 oh = omap_hwmod_lookup(oh_name); 282 if (!oh || oh->slaves_cnt == 0) 283 return -ENODEV; 284 285 omap_hwmod_setup_one(oh_name); 286 287 vbase = omap_hwmod_get_mpu_rt_va(oh); 288 if (!vbase) { 289 pr_warn("%s: failed to get counter_32k resource\n", __func__); 290 return -ENXIO; 291 } 292 293 ret = omap_hwmod_enable(oh); 294 if (ret) { 295 pr_warn("%s: failed to enable counter_32k module (%d)\n", 296 __func__, ret); 297 return ret; 298 } 299 300 ret = omap_init_clocksource_32k(vbase); 301 if (ret) { 302 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", 303 __func__, ret); 304 omap_hwmod_idle(oh); 305 } 306 307 return ret; 308 } 309 #else 310 static inline int omap2_sync32k_clocksource_init(void) 311 { 312 return -ENODEV; 313 } 314 #endif 315 316 static void __init omap2_gptimer_clocksource_init(int gptimer_id, 317 const char *fck_source) 318 { 319 int res; 320 321 res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source); 322 BUG_ON(res); 323 324 __omap_dm_timer_load_start(&clksrc, 325 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1); 326 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); 327 328 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 329 pr_err("Could not register clocksource %s\n", 330 clocksource_gpt.name); 331 else 332 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", 333 gptimer_id, clksrc.rate); 334 } 335 336 static void __init omap2_clocksource_init(int gptimer_id, 337 const char *fck_source) 338 { 339 /* 340 * First give preference to kernel parameter configuration 341 * by user (clocksource="gp_timer"). 342 * 343 * In case of missing kernel parameter for clocksource, 344 * first check for availability for 32k-sync timer, in case 345 * of failure in finding 32k_counter module or registering 346 * it as clocksource, execution will fallback to gp-timer. 347 */ 348 if (use_gptimer_clksrc == true) 349 omap2_gptimer_clocksource_init(gptimer_id, fck_source); 350 else if (omap2_sync32k_clocksource_init()) 351 /* Fall back to gp-timer code */ 352 omap2_gptimer_clocksource_init(gptimer_id, fck_source); 353 } 354 355 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 356 /* 357 * The realtime counter also called master counter, is a free-running 358 * counter, which is related to real time. It produces the count used 359 * by the CPU local timer peripherals in the MPU cluster. The timer counts 360 * at a rate of 6.144 MHz. Because the device operates on different clocks 361 * in different power modes, the master counter shifts operation between 362 * clocks, adjusting the increment per clock in hardware accordingly to 363 * maintain a constant count rate. 364 */ 365 static void __init realtime_counter_init(void) 366 { 367 void __iomem *base; 368 static struct clk *sys_clk; 369 unsigned long rate; 370 unsigned int reg, num, den; 371 372 base = ioremap(REALTIME_COUNTER_BASE, SZ_32); 373 if (!base) { 374 pr_err("%s: ioremap failed\n", __func__); 375 return; 376 } 377 sys_clk = clk_get(NULL, "sys_clkin_ck"); 378 if (!sys_clk) { 379 pr_err("%s: failed to get system clock handle\n", __func__); 380 iounmap(base); 381 return; 382 } 383 384 rate = clk_get_rate(sys_clk); 385 /* Numerator/denumerator values refer TRM Realtime Counter section */ 386 switch (rate) { 387 case 1200000: 388 num = 64; 389 den = 125; 390 break; 391 case 1300000: 392 num = 768; 393 den = 1625; 394 break; 395 case 19200000: 396 num = 8; 397 den = 25; 398 break; 399 case 2600000: 400 num = 384; 401 den = 1625; 402 break; 403 case 2700000: 404 num = 256; 405 den = 1125; 406 break; 407 case 38400000: 408 default: 409 /* Program it for 38.4 MHz */ 410 num = 4; 411 den = 25; 412 break; 413 } 414 415 /* Program numerator and denumerator registers */ 416 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & 417 NUMERATOR_DENUMERATOR_MASK; 418 reg |= num; 419 __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); 420 421 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & 422 NUMERATOR_DENUMERATOR_MASK; 423 reg |= den; 424 __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); 425 426 iounmap(base); 427 } 428 #else 429 static inline void __init realtime_counter_init(void) 430 {} 431 #endif 432 433 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ 434 clksrc_nr, clksrc_src) \ 435 static void __init omap##name##_timer_init(void) \ 436 { \ 437 omap2_gp_clockevent_init((clkev_nr), clkev_src); \ 438 omap2_clocksource_init((clksrc_nr), clksrc_src); \ 439 } 440 441 #define OMAP_SYS_TIMER(name) \ 442 struct sys_timer omap##name##_timer = { \ 443 .init = omap##name##_timer_init, \ 444 }; 445 446 #ifdef CONFIG_ARCH_OMAP2 447 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE) 448 OMAP_SYS_TIMER(2) 449 #endif 450 451 #ifdef CONFIG_ARCH_OMAP3 452 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE) 453 OMAP_SYS_TIMER(3) 454 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, 455 2, OMAP3_MPU_SOURCE) 456 OMAP_SYS_TIMER(3_secure) 457 #endif 458 459 #ifdef CONFIG_SOC_AM33XX 460 OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE) 461 OMAP_SYS_TIMER(3_am33xx) 462 #endif 463 464 #ifdef CONFIG_ARCH_OMAP4 465 #ifdef CONFIG_LOCAL_TIMERS 466 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 467 OMAP44XX_LOCAL_TWD_BASE, 468 OMAP44XX_IRQ_LOCALTIMER); 469 #endif 470 471 static void __init omap4_timer_init(void) 472 { 473 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); 474 omap2_clocksource_init(2, OMAP4_MPU_SOURCE); 475 #ifdef CONFIG_LOCAL_TIMERS 476 /* Local timers are not supprted on OMAP4430 ES1.0 */ 477 if (omap_rev() != OMAP4430_REV_ES1_0) { 478 int err; 479 480 err = twd_local_timer_register(&twd_local_timer); 481 if (err) 482 pr_err("twd_local_timer_register failed %d\n", err); 483 } 484 #endif 485 } 486 OMAP_SYS_TIMER(4) 487 #endif 488 489 #ifdef CONFIG_SOC_OMAP5 490 static void __init omap5_timer_init(void) 491 { 492 int err; 493 494 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); 495 omap2_clocksource_init(2, OMAP4_MPU_SOURCE); 496 realtime_counter_init(); 497 498 err = arch_timer_of_register(); 499 if (err) 500 pr_err("%s: arch_timer_register failed %d\n", __func__, err); 501 } 502 OMAP_SYS_TIMER(5) 503 #endif 504 505 /** 506 * omap_timer_init - build and register timer device with an 507 * associated timer hwmod 508 * @oh: timer hwmod pointer to be used to build timer device 509 * @user: parameter that can be passed from calling hwmod API 510 * 511 * Called by omap_hwmod_for_each_by_class to register each of the timer 512 * devices present in the system. The number of timer devices is known 513 * by parsing through the hwmod database for a given class name. At the 514 * end of function call memory is allocated for timer device and it is 515 * registered to the framework ready to be proved by the driver. 516 */ 517 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) 518 { 519 int id; 520 int ret = 0; 521 char *name = "omap_timer"; 522 struct dmtimer_platform_data *pdata; 523 struct platform_device *pdev; 524 struct omap_timer_capability_dev_attr *timer_dev_attr; 525 526 pr_debug("%s: %s\n", __func__, oh->name); 527 528 /* on secure device, do not register secure timer */ 529 timer_dev_attr = oh->dev_attr; 530 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) 531 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) 532 return ret; 533 534 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 535 if (!pdata) { 536 pr_err("%s: No memory for [%s]\n", __func__, oh->name); 537 return -ENOMEM; 538 } 539 540 /* 541 * Extract the IDs from name field in hwmod database 542 * and use the same for constructing ids' for the 543 * timer devices. In a way, we are avoiding usage of 544 * static variable witin the function to do the same. 545 * CAUTION: We have to be careful and make sure the 546 * name in hwmod database does not change in which case 547 * we might either make corresponding change here or 548 * switch back static variable mechanism. 549 */ 550 sscanf(oh->name, "timer%2d", &id); 551 552 if (timer_dev_attr) 553 pdata->timer_capability = timer_dev_attr->timer_capability; 554 555 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), 556 NULL, 0, 0); 557 558 if (IS_ERR(pdev)) { 559 pr_err("%s: Can't build omap_device for %s: %s.\n", 560 __func__, name, oh->name); 561 ret = -EINVAL; 562 } 563 564 kfree(pdata); 565 566 return ret; 567 } 568 569 /** 570 * omap2_dm_timer_init - top level regular device initialization 571 * 572 * Uses dedicated hwmod api to parse through hwmod database for 573 * given class name and then build and register the timer device. 574 */ 575 static int __init omap2_dm_timer_init(void) 576 { 577 int ret; 578 579 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); 580 if (unlikely(ret)) { 581 pr_err("%s: device registration failed.\n", __func__); 582 return -EINVAL; 583 } 584 585 return 0; 586 } 587 arch_initcall(omap2_dm_timer_init); 588 589 /** 590 * omap2_override_clocksource - clocksource override with user configuration 591 * 592 * Allows user to override default clocksource, using kernel parameter 593 * clocksource="gp_timer" (For all OMAP2PLUS architectures) 594 * 595 * Note that, here we are using same standard kernel parameter "clocksource=", 596 * and not introducing any OMAP specific interface. 597 */ 598 static int __init omap2_override_clocksource(char *str) 599 { 600 if (!str) 601 return 0; 602 /* 603 * For OMAP architecture, we only have two options 604 * - sync_32k (default) 605 * - gp_timer (sys_clk based) 606 */ 607 if (!strcmp(str, "gp_timer")) 608 use_gptimer_clksrc = true; 609 610 return 0; 611 } 612 early_param("clocksource", omap2_override_clocksource); 613