18bd22949SKevin Hilman/* 28bd22949SKevin Hilman * linux/arch/arm/mach-omap2/sleep.S 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * (C) Copyright 2007 58bd22949SKevin Hilman * Texas Instruments 68bd22949SKevin Hilman * Karthik Dasu <karthik-dp@ti.com> 78bd22949SKevin Hilman * 88bd22949SKevin Hilman * (C) Copyright 2004 98bd22949SKevin Hilman * Texas Instruments, <www.ti.com> 108bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 118bd22949SKevin Hilman * 128bd22949SKevin Hilman * This program is free software; you can redistribute it and/or 138bd22949SKevin Hilman * modify it under the terms of the GNU General Public License as 148bd22949SKevin Hilman * published by the Free Software Foundation; either version 2 of 158bd22949SKevin Hilman * the License, or (at your option) any later version. 168bd22949SKevin Hilman * 178bd22949SKevin Hilman * This program is distributed in the hope that it will be useful, 188bd22949SKevin Hilman * but WITHOUT ANY WARRANTY; without even the implied warranty of 198bd22949SKevin Hilman * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 208bd22949SKevin Hilman * GNU General Public License for more details. 218bd22949SKevin Hilman * 228bd22949SKevin Hilman * You should have received a copy of the GNU General Public License 238bd22949SKevin Hilman * along with this program; if not, write to the Free Software 248bd22949SKevin Hilman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 258bd22949SKevin Hilman * MA 02111-1307 USA 268bd22949SKevin Hilman */ 278bd22949SKevin Hilman#include <linux/linkage.h> 288bd22949SKevin Hilman#include <asm/assembler.h> 29b4b36fd9SJean Pihet#include <plat/sram.h> 308bd22949SKevin Hilman#include <mach/io.h> 318bd22949SKevin Hilman 3289139dceSPeter 'p2' De Schrijver#include "cm.h" 338bd22949SKevin Hilman#include "prm.h" 348bd22949SKevin Hilman#include "sdrc.h" 354814ced5SPaul Walmsley#include "control.h" 368bd22949SKevin Hilman 37fe360e1cSJean Pihet/* 38fe360e1cSJean Pihet * Registers access definitions 39fe360e1cSJean Pihet */ 40fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_OFFS 0xc 41fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ 42fe360e1cSJean Pihet (SDRC_SCRATCHPAD_SEM_OFFS) 43fe360e1cSJean Pihet#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ 44fe360e1cSJean Pihet OMAP3430_PM_PREPWSTST 4537903009SAbhijit Pagare#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL 4689139dceSPeter 'p2' De Schrijver#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) 479d93b8a2SPeter 'p2' De Schrijver#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) 48fe360e1cSJean Pihet#define SRAM_BASE_P OMAP3_SRAM_PA 49fe360e1cSJean Pihet#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS 50fe360e1cSJean Pihet#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ 51fe360e1cSJean Pihet OMAP36XX_CONTROL_MEM_RTA_CTRL) 52fe360e1cSJean Pihet 53fe360e1cSJean Pihet/* Move this as correct place is available */ 54fe360e1cSJean Pihet#define SCRATCHPAD_MEM_OFFS 0x310 55fe360e1cSJean Pihet#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ 56fe360e1cSJean Pihet OMAP343X_CONTROL_MEM_WKUP +\ 57fe360e1cSJean Pihet SCRATCHPAD_MEM_OFFS) 588bd22949SKevin Hilman#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 590795a75aSTero Kristo#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) 600795a75aSTero Kristo#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) 610795a75aSTero Kristo#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) 620795a75aSTero Kristo#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) 630795a75aSTero Kristo#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) 640795a75aSTero Kristo#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) 650795a75aSTero Kristo#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) 6689139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 6789139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 688bd22949SKevin Hilman 69a89b6f00SRajendra Nayak 70d3cdfd2aSJean Pihet/* 71d3cdfd2aSJean Pihet * API functions 72d3cdfd2aSJean Pihet */ 73a89b6f00SRajendra Nayak 74*f7dfe3d8SJean Pihet/* 75*f7dfe3d8SJean Pihet * The "get_*restore_pointer" functions are used to provide a 76*f7dfe3d8SJean Pihet * physical restore address where the ROM code jumps while waking 77*f7dfe3d8SJean Pihet * up from MPU OFF/OSWR state. 78*f7dfe3d8SJean Pihet * The restore pointer is stored into the scratchpad. 79*f7dfe3d8SJean Pihet */ 80*f7dfe3d8SJean Pihet 81a89b6f00SRajendra Nayak .text 828bd22949SKevin Hilman/* Function call to get the restore pointer for resume from OFF */ 838bd22949SKevin HilmanENTRY(get_restore_pointer) 848bd22949SKevin Hilman stmfd sp!, {lr} @ save registers on stack 858bd22949SKevin Hilman adr r0, restore 868bd22949SKevin Hilman ldmfd sp!, {pc} @ restore regs and return 878bd22949SKevin HilmanENTRY(get_restore_pointer_sz) 880795a75aSTero Kristo .word . - get_restore_pointer 891e81bc01SJean Pihet 90458e999eSNishanth Menon .text 91458e999eSNishanth Menon/* Function call to get the restore pointer for 3630 resume from OFF */ 92458e999eSNishanth MenonENTRY(get_omap3630_restore_pointer) 93458e999eSNishanth Menon stmfd sp!, {lr} @ save registers on stack 94458e999eSNishanth Menon adr r0, restore_3630 95458e999eSNishanth Menon ldmfd sp!, {pc} @ restore regs and return 96458e999eSNishanth MenonENTRY(get_omap3630_restore_pointer_sz) 97458e999eSNishanth Menon .word . - get_omap3630_restore_pointer 980795a75aSTero Kristo 990795a75aSTero Kristo .text 1001e81bc01SJean Pihet/* Function call to get the restore pointer for ES3 to resume from OFF */ 1011e81bc01SJean PihetENTRY(get_es3_restore_pointer) 1021e81bc01SJean Pihet stmfd sp!, {lr} @ save registers on stack 1031e81bc01SJean Pihet adr r0, restore_es3 1041e81bc01SJean Pihet ldmfd sp!, {pc} @ restore regs and return 1051e81bc01SJean PihetENTRY(get_es3_restore_pointer_sz) 1061e81bc01SJean Pihet .word . - get_es3_restore_pointer 1071e81bc01SJean Pihet 1081e81bc01SJean Pihet .text 109c4236d2eSPeter 'p2' De Schrijver/* 110c4236d2eSPeter 'p2' De Schrijver * L2 cache needs to be toggled for stable OFF mode functionality on 3630. 1111e81bc01SJean Pihet * This function sets up a flag that will allow for this toggling to take 112*f7dfe3d8SJean Pihet * place on 3630. Hopefully some version in the future may not need this. 113c4236d2eSPeter 'p2' De Schrijver */ 114c4236d2eSPeter 'p2' De SchrijverENTRY(enable_omap3630_toggle_l2_on_restore) 115c4236d2eSPeter 'p2' De Schrijver stmfd sp!, {lr} @ save registers on stack 116c4236d2eSPeter 'p2' De Schrijver /* Setup so that we will disable and enable l2 */ 117c4236d2eSPeter 'p2' De Schrijver mov r1, #0x1 118c4236d2eSPeter 'p2' De Schrijver str r1, l2dis_3630 119c4236d2eSPeter 'p2' De Schrijver ldmfd sp!, {pc} @ restore regs and return 120c4236d2eSPeter 'p2' De Schrijver 12127d59a4aSTero Kristo/* Function to call rom code to save secure ram context */ 12227d59a4aSTero KristoENTRY(save_secure_ram_context) 12327d59a4aSTero Kristo stmfd sp!, {r1-r12, lr} @ save registers on stack 124d3cdfd2aSJean Pihet 12527d59a4aSTero Kristo adr r3, api_params @ r3 points to parameters 12627d59a4aSTero Kristo str r0, [r3,#0x4] @ r0 has sdram address 12727d59a4aSTero Kristo ldr r12, high_mask 12827d59a4aSTero Kristo and r3, r3, r12 12927d59a4aSTero Kristo ldr r12, sram_phy_addr_mask 13027d59a4aSTero Kristo orr r3, r3, r12 13127d59a4aSTero Kristo mov r0, #25 @ set service ID for PPA 13227d59a4aSTero Kristo mov r12, r0 @ copy secure service ID in r12 13327d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 134ba50ea7eSKalle Jokiniemi mov r2, #4 @ set some flags in r2, r6 13527d59a4aSTero Kristo mov r6, #0xff 13627d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 13727d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 13827d59a4aSTero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 13927d59a4aSTero Kristo nop 14027d59a4aSTero Kristo nop 14127d59a4aSTero Kristo nop 14227d59a4aSTero Kristo nop 14327d59a4aSTero Kristo ldmfd sp!, {r1-r12, pc} 14427d59a4aSTero Kristosram_phy_addr_mask: 14527d59a4aSTero Kristo .word SRAM_BASE_P 14627d59a4aSTero Kristohigh_mask: 14727d59a4aSTero Kristo .word 0xffff 14827d59a4aSTero Kristoapi_params: 14927d59a4aSTero Kristo .word 0x4, 0x0, 0x0, 0x1, 0x1 15027d59a4aSTero KristoENTRY(save_secure_ram_context_sz) 15127d59a4aSTero Kristo .word . - save_secure_ram_context 15227d59a4aSTero Kristo 1538bd22949SKevin Hilman/* 154*f7dfe3d8SJean Pihet * ====================== 155*f7dfe3d8SJean Pihet * == Idle entry point == 156*f7dfe3d8SJean Pihet * ====================== 157*f7dfe3d8SJean Pihet */ 158*f7dfe3d8SJean Pihet 159*f7dfe3d8SJean Pihet/* 1608bd22949SKevin Hilman * Forces OMAP into idle state 1618bd22949SKevin Hilman * 162*f7dfe3d8SJean Pihet * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed 163*f7dfe3d8SJean Pihet * and executes the WFI instruction. Calling WFI effectively changes the 164*f7dfe3d8SJean Pihet * power domains states to the desired target power states. 1658bd22949SKevin Hilman * 166*f7dfe3d8SJean Pihet * 167*f7dfe3d8SJean Pihet * Notes: 168*f7dfe3d8SJean Pihet * - this code gets copied to internal SRAM at boot. The execution pointer 169*f7dfe3d8SJean Pihet * in SRAM is _omap_sram_idle. 170*f7dfe3d8SJean Pihet * - when the OMAP wakes up it continues at different execution points 171*f7dfe3d8SJean Pihet * depending on the low power mode (non-OFF vs OFF modes), 172*f7dfe3d8SJean Pihet * cf. 'Resume path for xxx mode' comments. 1738bd22949SKevin Hilman */ 1748bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend) 1758bd22949SKevin Hilman stmfd sp!, {r0-r12, lr} @ save registers on stack 176d3cdfd2aSJean Pihet 177*f7dfe3d8SJean Pihet /* 178*f7dfe3d8SJean Pihet * r0 contains restore pointer in sdram 179*f7dfe3d8SJean Pihet * r1 contains information about saving context: 180*f7dfe3d8SJean Pihet * 0 - No context lost 181*f7dfe3d8SJean Pihet * 1 - Only L1 and logic lost 182*f7dfe3d8SJean Pihet * 2 - Only L2 lost 183*f7dfe3d8SJean Pihet * 3 - Both L1 and L2 lost 184*f7dfe3d8SJean Pihet */ 185*f7dfe3d8SJean Pihet 186*f7dfe3d8SJean Pihet /* Directly jump to WFI is the context save is not required */ 187*f7dfe3d8SJean Pihet cmp r1, #0x0 188*f7dfe3d8SJean Pihet beq omap3_do_wfi 189*f7dfe3d8SJean Pihet 190*f7dfe3d8SJean Pihet /* Otherwise fall through to the save context code */ 191*f7dfe3d8SJean Pihetsave_context_wfi: 192*f7dfe3d8SJean Pihet mov r8, r0 @ Store SDRAM address in r8 193*f7dfe3d8SJean Pihet mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register 194*f7dfe3d8SJean Pihet mov r4, #0x1 @ Number of parameters for restore call 195*f7dfe3d8SJean Pihet stmia r8!, {r4-r5} @ Push parameters for restore call 196*f7dfe3d8SJean Pihet mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register 197*f7dfe3d8SJean Pihet stmia r8!, {r4-r5} @ Push parameters for restore call 198*f7dfe3d8SJean Pihet 199*f7dfe3d8SJean Pihet /* Check what that target sleep state is from r1 */ 200*f7dfe3d8SJean Pihet cmp r1, #0x2 @ Only L2 lost, no need to save context 201*f7dfe3d8SJean Pihet beq clean_caches 202*f7dfe3d8SJean Pihet 203*f7dfe3d8SJean Pihetl1_logic_lost: 204*f7dfe3d8SJean Pihet /* Store sp and spsr to SDRAM */ 205*f7dfe3d8SJean Pihet mov r4, sp 206*f7dfe3d8SJean Pihet mrs r5, spsr 207*f7dfe3d8SJean Pihet mov r6, lr 208*f7dfe3d8SJean Pihet stmia r8!, {r4-r6} 209*f7dfe3d8SJean Pihet /* Save all ARM registers */ 210*f7dfe3d8SJean Pihet /* Coprocessor access control register */ 211*f7dfe3d8SJean Pihet mrc p15, 0, r6, c1, c0, 2 212*f7dfe3d8SJean Pihet stmia r8!, {r6} 213*f7dfe3d8SJean Pihet /* TTBR0, TTBR1 and Translation table base control */ 214*f7dfe3d8SJean Pihet mrc p15, 0, r4, c2, c0, 0 215*f7dfe3d8SJean Pihet mrc p15, 0, r5, c2, c0, 1 216*f7dfe3d8SJean Pihet mrc p15, 0, r6, c2, c0, 2 217*f7dfe3d8SJean Pihet stmia r8!, {r4-r6} 218*f7dfe3d8SJean Pihet /* 219*f7dfe3d8SJean Pihet * Domain access control register, data fault status register, 220*f7dfe3d8SJean Pihet * and instruction fault status register 221*f7dfe3d8SJean Pihet */ 222*f7dfe3d8SJean Pihet mrc p15, 0, r4, c3, c0, 0 223*f7dfe3d8SJean Pihet mrc p15, 0, r5, c5, c0, 0 224*f7dfe3d8SJean Pihet mrc p15, 0, r6, c5, c0, 1 225*f7dfe3d8SJean Pihet stmia r8!, {r4-r6} 226*f7dfe3d8SJean Pihet /* 227*f7dfe3d8SJean Pihet * Data aux fault status register, instruction aux fault status, 228*f7dfe3d8SJean Pihet * data fault address register and instruction fault address register 229*f7dfe3d8SJean Pihet */ 230*f7dfe3d8SJean Pihet mrc p15, 0, r4, c5, c1, 0 231*f7dfe3d8SJean Pihet mrc p15, 0, r5, c5, c1, 1 232*f7dfe3d8SJean Pihet mrc p15, 0, r6, c6, c0, 0 233*f7dfe3d8SJean Pihet mrc p15, 0, r7, c6, c0, 2 234*f7dfe3d8SJean Pihet stmia r8!, {r4-r7} 235*f7dfe3d8SJean Pihet /* 236*f7dfe3d8SJean Pihet * user r/w thread and process ID, user r/o thread and process ID, 237*f7dfe3d8SJean Pihet * priv only thread and process ID, cache size selection 238*f7dfe3d8SJean Pihet */ 239*f7dfe3d8SJean Pihet mrc p15, 0, r4, c13, c0, 2 240*f7dfe3d8SJean Pihet mrc p15, 0, r5, c13, c0, 3 241*f7dfe3d8SJean Pihet mrc p15, 0, r6, c13, c0, 4 242*f7dfe3d8SJean Pihet mrc p15, 2, r7, c0, c0, 0 243*f7dfe3d8SJean Pihet stmia r8!, {r4-r7} 244*f7dfe3d8SJean Pihet /* Data TLB lockdown, instruction TLB lockdown registers */ 245*f7dfe3d8SJean Pihet mrc p15, 0, r5, c10, c0, 0 246*f7dfe3d8SJean Pihet mrc p15, 0, r6, c10, c0, 1 247*f7dfe3d8SJean Pihet stmia r8!, {r5-r6} 248*f7dfe3d8SJean Pihet /* Secure or non secure vector base address, FCSE PID, Context PID*/ 249*f7dfe3d8SJean Pihet mrc p15, 0, r4, c12, c0, 0 250*f7dfe3d8SJean Pihet mrc p15, 0, r5, c13, c0, 0 251*f7dfe3d8SJean Pihet mrc p15, 0, r6, c13, c0, 1 252*f7dfe3d8SJean Pihet stmia r8!, {r4-r6} 253*f7dfe3d8SJean Pihet /* Primary remap, normal remap registers */ 254*f7dfe3d8SJean Pihet mrc p15, 0, r4, c10, c2, 0 255*f7dfe3d8SJean Pihet mrc p15, 0, r5, c10, c2, 1 256*f7dfe3d8SJean Pihet stmia r8!,{r4-r5} 257*f7dfe3d8SJean Pihet 258*f7dfe3d8SJean Pihet /* Store current cpsr*/ 259*f7dfe3d8SJean Pihet mrs r2, cpsr 260*f7dfe3d8SJean Pihet stmia r8!, {r2} 261*f7dfe3d8SJean Pihet 262*f7dfe3d8SJean Pihet mrc p15, 0, r4, c1, c0, 0 263*f7dfe3d8SJean Pihet /* save control register */ 264*f7dfe3d8SJean Pihet stmia r8!, {r4} 265*f7dfe3d8SJean Pihet 266*f7dfe3d8SJean Pihetclean_caches: 267*f7dfe3d8SJean Pihet /* 268*f7dfe3d8SJean Pihet * Clean Data or unified cache to POU 269*f7dfe3d8SJean Pihet * How to invalidate only L1 cache???? - #FIX_ME# 270*f7dfe3d8SJean Pihet * mcr p15, 0, r11, c7, c11, 1 271*f7dfe3d8SJean Pihet */ 272*f7dfe3d8SJean Pihet cmp r1, #0x1 @ Check whether L2 inval is required 273*f7dfe3d8SJean Pihet beq omap3_do_wfi 274*f7dfe3d8SJean Pihet 275*f7dfe3d8SJean Pihetclean_l2: 276*f7dfe3d8SJean Pihet /* 277*f7dfe3d8SJean Pihet * jump out to kernel flush routine 278*f7dfe3d8SJean Pihet * - reuse that code is better 279*f7dfe3d8SJean Pihet * - it executes in a cached space so is faster than refetch per-block 280*f7dfe3d8SJean Pihet * - should be faster and will change with kernel 281*f7dfe3d8SJean Pihet * - 'might' have to copy address, load and jump to it 282*f7dfe3d8SJean Pihet */ 283*f7dfe3d8SJean Pihet ldr r1, kernel_flush 284*f7dfe3d8SJean Pihet mov lr, pc 285*f7dfe3d8SJean Pihet bx r1 286*f7dfe3d8SJean Pihet 287*f7dfe3d8SJean Pihetomap3_do_wfi: 2888bd22949SKevin Hilman ldr r4, sdrc_power @ read the SDRC_POWER register 2898bd22949SKevin Hilman ldr r5, [r4] @ read the contents of SDRC_POWER 2908bd22949SKevin Hilman orr r5, r5, #0x40 @ enable self refresh on idle req 2918bd22949SKevin Hilman str r5, [r4] @ write back to SDRC_POWER register 2928bd22949SKevin Hilman 2938bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 2948bd22949SKevin Hilman mov r1, #0 2958bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 4 2968bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 5 2978bd22949SKevin Hilman 298*f7dfe3d8SJean Pihet/* 299*f7dfe3d8SJean Pihet * =================================== 300*f7dfe3d8SJean Pihet * == WFI instruction => Enter idle == 301*f7dfe3d8SJean Pihet * =================================== 302*f7dfe3d8SJean Pihet */ 3038bd22949SKevin Hilman wfi @ wait for interrupt 3048bd22949SKevin Hilman 305*f7dfe3d8SJean Pihet/* 306*f7dfe3d8SJean Pihet * =================================== 307*f7dfe3d8SJean Pihet * == Resume path for non-OFF modes == 308*f7dfe3d8SJean Pihet * =================================== 309*f7dfe3d8SJean Pihet */ 3108bd22949SKevin Hilman nop 3118bd22949SKevin Hilman nop 3128bd22949SKevin Hilman nop 3138bd22949SKevin Hilman nop 3148bd22949SKevin Hilman nop 3158bd22949SKevin Hilman nop 3168bd22949SKevin Hilman nop 3178bd22949SKevin Hilman nop 3188bd22949SKevin Hilman nop 3198bd22949SKevin Hilman nop 32089139dceSPeter 'p2' De Schrijver bl wait_sdrc_ok 3218bd22949SKevin Hilman 322*f7dfe3d8SJean Pihet/* 323*f7dfe3d8SJean Pihet * =================================== 324*f7dfe3d8SJean Pihet * == Exit point from non-OFF modes == 325*f7dfe3d8SJean Pihet * =================================== 326*f7dfe3d8SJean Pihet */ 3278bd22949SKevin Hilman ldmfd sp!, {r0-r12, pc} @ restore regs and return 328*f7dfe3d8SJean Pihet 329*f7dfe3d8SJean Pihet 330*f7dfe3d8SJean Pihet/* 331*f7dfe3d8SJean Pihet * ============================== 332*f7dfe3d8SJean Pihet * == Resume path for OFF mode == 333*f7dfe3d8SJean Pihet * ============================== 334*f7dfe3d8SJean Pihet */ 335*f7dfe3d8SJean Pihet 336*f7dfe3d8SJean Pihet/* 337*f7dfe3d8SJean Pihet * The restore_* functions are called by the ROM code 338*f7dfe3d8SJean Pihet * when back from WFI in OFF mode. 339*f7dfe3d8SJean Pihet * Cf. the get_*restore_pointer functions. 340*f7dfe3d8SJean Pihet * 341*f7dfe3d8SJean Pihet * restore_es3: applies to 34xx >= ES3.0 342*f7dfe3d8SJean Pihet * restore_3630: applies to 36xx 343*f7dfe3d8SJean Pihet * restore: common code for 3xxx 344*f7dfe3d8SJean Pihet */ 3450795a75aSTero Kristorestore_es3: 3460795a75aSTero Kristo ldr r5, pm_prepwstst_core_p 3470795a75aSTero Kristo ldr r4, [r5] 3480795a75aSTero Kristo and r4, r4, #0x3 3490795a75aSTero Kristo cmp r4, #0x0 @ Check if previous power state of CORE is OFF 3500795a75aSTero Kristo bne restore 3510795a75aSTero Kristo adr r0, es3_sdrc_fix 3520795a75aSTero Kristo ldr r1, sram_base 3530795a75aSTero Kristo ldr r2, es3_sdrc_fix_sz 3540795a75aSTero Kristo mov r2, r2, ror #2 3550795a75aSTero Kristocopy_to_sram: 3560795a75aSTero Kristo ldmia r0!, {r3} @ val = *src 3570795a75aSTero Kristo stmia r1!, {r3} @ *dst = val 3580795a75aSTero Kristo subs r2, r2, #0x1 @ num_words-- 3590795a75aSTero Kristo bne copy_to_sram 3600795a75aSTero Kristo ldr r1, sram_base 3610795a75aSTero Kristo blx r1 362458e999eSNishanth Menon b restore 363458e999eSNishanth Menon 364458e999eSNishanth Menonrestore_3630: 365458e999eSNishanth Menon ldr r1, pm_prepwstst_core_p 366458e999eSNishanth Menon ldr r2, [r1] 367458e999eSNishanth Menon and r2, r2, #0x3 368458e999eSNishanth Menon cmp r2, #0x0 @ Check if previous power state of CORE is OFF 369458e999eSNishanth Menon bne restore 370458e999eSNishanth Menon /* Disable RTA before giving control */ 371458e999eSNishanth Menon ldr r1, control_mem_rta 372458e999eSNishanth Menon mov r2, #OMAP36XX_RTA_DISABLE 373458e999eSNishanth Menon str r2, [r1] 374*f7dfe3d8SJean Pihet 375*f7dfe3d8SJean Pihet /* Fall through to common code for the remaining logic */ 376*f7dfe3d8SJean Pihet 3778bd22949SKevin Hilmanrestore: 378*f7dfe3d8SJean Pihet /* 379*f7dfe3d8SJean Pihet * Check what was the reason for mpu reset and store the reason in r9: 380*f7dfe3d8SJean Pihet * 0 - No context lost 381*f7dfe3d8SJean Pihet * 1 - Only L1 and logic lost 382*f7dfe3d8SJean Pihet * 2 - Only L2 lost - In this case, we wont be here 383*f7dfe3d8SJean Pihet * 3 - Both L1 and L2 lost 384*f7dfe3d8SJean Pihet */ 3858bd22949SKevin Hilman ldr r1, pm_pwstctrl_mpu 3868bd22949SKevin Hilman ldr r2, [r1] 3878bd22949SKevin Hilman and r2, r2, #0x3 3888bd22949SKevin Hilman cmp r2, #0x0 @ Check if target power state was OFF or RET 3898bd22949SKevin Hilman moveq r9, #0x3 @ MPU OFF => L1 and L2 lost 3908bd22949SKevin Hilman movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation 3918bd22949SKevin Hilman bne logic_l1_restore 392c4236d2eSPeter 'p2' De Schrijver 393c4236d2eSPeter 'p2' De Schrijver ldr r0, l2dis_3630 394c4236d2eSPeter 'p2' De Schrijver cmp r0, #0x1 @ should we disable L2 on 3630? 395c4236d2eSPeter 'p2' De Schrijver bne skipl2dis 396c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r0, c1, c0, 1 397c4236d2eSPeter 'p2' De Schrijver bic r0, r0, #2 @ disable L2 cache 398c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r0, c1, c0, 1 399c4236d2eSPeter 'p2' De Schrijverskipl2dis: 40027d59a4aSTero Kristo ldr r0, control_stat 40127d59a4aSTero Kristo ldr r1, [r0] 40227d59a4aSTero Kristo and r1, #0x700 40327d59a4aSTero Kristo cmp r1, #0x300 40427d59a4aSTero Kristo beq l2_inv_gp 40527d59a4aSTero Kristo mov r0, #40 @ set service ID for PPA 40627d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 40727d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 40827d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 40927d59a4aSTero Kristo mov r6, #0xff 41027d59a4aSTero Kristo adr r3, l2_inv_api_params @ r3 points to dummy parameters 41127d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 41227d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 41327d59a4aSTero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 41427d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 41527d59a4aSTero Kristo mov r0, #42 @ set service ID for PPA 41627d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 41727d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 41827d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 41927d59a4aSTero Kristo mov r6, #0xff 420a087cad9STero Kristo ldr r4, scratchpad_base 421a087cad9STero Kristo ldr r3, [r4, #0xBC] @ r3 points to parameters 42227d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 42327d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 42427d59a4aSTero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 42527d59a4aSTero Kristo 42679dcfdd4STero Kristo#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 42779dcfdd4STero Kristo /* Restore L2 aux control register */ 42879dcfdd4STero Kristo @ set service ID for PPA 42979dcfdd4STero Kristo mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 43079dcfdd4STero Kristo mov r12, r0 @ copy service ID in r12 43179dcfdd4STero Kristo mov r1, #0 @ set task ID for ROM code in r1 43279dcfdd4STero Kristo mov r2, #4 @ set some flags in r2, r6 43379dcfdd4STero Kristo mov r6, #0xff 43479dcfdd4STero Kristo ldr r4, scratchpad_base 43579dcfdd4STero Kristo ldr r3, [r4, #0xBC] 43679dcfdd4STero Kristo adds r3, r3, #8 @ r3 points to parameters 43779dcfdd4STero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 43879dcfdd4STero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 43979dcfdd4STero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 44079dcfdd4STero Kristo#endif 44127d59a4aSTero Kristo b logic_l1_restore 44227d59a4aSTero Kristol2_inv_api_params: 44327d59a4aSTero Kristo .word 0x1, 0x00 44427d59a4aSTero Kristol2_inv_gp: 4458bd22949SKevin Hilman /* Execute smi to invalidate L2 cache */ 4468bd22949SKevin Hilman mov r12, #0x1 @ set up to invalide L2 4478bd22949SKevin Hilmansmi: .word 0xE1600070 @ Call SMI monitor (smieq) 44827d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 449a087cad9STero Kristo ldr r4, scratchpad_base 450a087cad9STero Kristo ldr r3, [r4,#0xBC] 451a087cad9STero Kristo ldr r0, [r3,#4] 45227d59a4aSTero Kristo mov r12, #0x3 45327d59a4aSTero Kristo .word 0xE1600070 @ Call SMI monitor (smieq) 45479dcfdd4STero Kristo ldr r4, scratchpad_base 45579dcfdd4STero Kristo ldr r3, [r4,#0xBC] 45679dcfdd4STero Kristo ldr r0, [r3,#12] 45779dcfdd4STero Kristo mov r12, #0x2 45879dcfdd4STero Kristo .word 0xE1600070 @ Call SMI monitor (smieq) 4598bd22949SKevin Hilmanlogic_l1_restore: 460c4236d2eSPeter 'p2' De Schrijver ldr r1, l2dis_3630 461c4236d2eSPeter 'p2' De Schrijver cmp r1, #0x1 @ Do we need to re-enable L2 on 3630? 462c4236d2eSPeter 'p2' De Schrijver bne skipl2reen 463c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r1, c1, c0, 1 464c4236d2eSPeter 'p2' De Schrijver orr r1, r1, #2 @ re-enable L2 cache 465c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r1, c1, c0, 1 466c4236d2eSPeter 'p2' De Schrijverskipl2reen: 4678bd22949SKevin Hilman mov r1, #0 4688bd22949SKevin Hilman /* Invalidate all instruction caches to PoU 4698bd22949SKevin Hilman * and flush branch target cache */ 4708bd22949SKevin Hilman mcr p15, 0, r1, c7, c5, 0 4718bd22949SKevin Hilman 4728bd22949SKevin Hilman ldr r4, scratchpad_base 4738bd22949SKevin Hilman ldr r3, [r4,#0xBC] 47479dcfdd4STero Kristo adds r3, r3, #16 4758bd22949SKevin Hilman ldmia r3!, {r4-r6} 4768bd22949SKevin Hilman mov sp, r4 4778bd22949SKevin Hilman msr spsr_cxsf, r5 4788bd22949SKevin Hilman mov lr, r6 4798bd22949SKevin Hilman 4808bd22949SKevin Hilman ldmia r3!, {r4-r9} 4818bd22949SKevin Hilman /* Coprocessor access Control Register */ 4828bd22949SKevin Hilman mcr p15, 0, r4, c1, c0, 2 4838bd22949SKevin Hilman 4848bd22949SKevin Hilman /* TTBR0 */ 4858bd22949SKevin Hilman MCR p15, 0, r5, c2, c0, 0 4868bd22949SKevin Hilman /* TTBR1 */ 4878bd22949SKevin Hilman MCR p15, 0, r6, c2, c0, 1 4888bd22949SKevin Hilman /* Translation table base control register */ 4898bd22949SKevin Hilman MCR p15, 0, r7, c2, c0, 2 4908bd22949SKevin Hilman /*domain access Control Register */ 4918bd22949SKevin Hilman MCR p15, 0, r8, c3, c0, 0 4928bd22949SKevin Hilman /* data fault status Register */ 4938bd22949SKevin Hilman MCR p15, 0, r9, c5, c0, 0 4948bd22949SKevin Hilman 4958bd22949SKevin Hilman ldmia r3!,{r4-r8} 4968bd22949SKevin Hilman /* instruction fault status Register */ 4978bd22949SKevin Hilman MCR p15, 0, r4, c5, c0, 1 4988bd22949SKevin Hilman /*Data Auxiliary Fault Status Register */ 4998bd22949SKevin Hilman MCR p15, 0, r5, c5, c1, 0 5008bd22949SKevin Hilman /*Instruction Auxiliary Fault Status Register*/ 5018bd22949SKevin Hilman MCR p15, 0, r6, c5, c1, 1 5028bd22949SKevin Hilman /*Data Fault Address Register */ 5038bd22949SKevin Hilman MCR p15, 0, r7, c6, c0, 0 5048bd22949SKevin Hilman /*Instruction Fault Address Register*/ 5058bd22949SKevin Hilman MCR p15, 0, r8, c6, c0, 2 5068bd22949SKevin Hilman ldmia r3!,{r4-r7} 5078bd22949SKevin Hilman 5088bd22949SKevin Hilman /* user r/w thread and process ID */ 5098bd22949SKevin Hilman MCR p15, 0, r4, c13, c0, 2 5108bd22949SKevin Hilman /* user ro thread and process ID */ 5118bd22949SKevin Hilman MCR p15, 0, r5, c13, c0, 3 5128bd22949SKevin Hilman /*Privileged only thread and process ID */ 5138bd22949SKevin Hilman MCR p15, 0, r6, c13, c0, 4 5148bd22949SKevin Hilman /* cache size selection */ 5158bd22949SKevin Hilman MCR p15, 2, r7, c0, c0, 0 5168bd22949SKevin Hilman ldmia r3!,{r4-r8} 5178bd22949SKevin Hilman /* Data TLB lockdown registers */ 5188bd22949SKevin Hilman MCR p15, 0, r4, c10, c0, 0 5198bd22949SKevin Hilman /* Instruction TLB lockdown registers */ 5208bd22949SKevin Hilman MCR p15, 0, r5, c10, c0, 1 5218bd22949SKevin Hilman /* Secure or Nonsecure Vector Base Address */ 5228bd22949SKevin Hilman MCR p15, 0, r6, c12, c0, 0 5238bd22949SKevin Hilman /* FCSE PID */ 5248bd22949SKevin Hilman MCR p15, 0, r7, c13, c0, 0 5258bd22949SKevin Hilman /* Context PID */ 5268bd22949SKevin Hilman MCR p15, 0, r8, c13, c0, 1 5278bd22949SKevin Hilman 5288bd22949SKevin Hilman ldmia r3!,{r4-r5} 5298bd22949SKevin Hilman /* primary memory remap register */ 5308bd22949SKevin Hilman MCR p15, 0, r4, c10, c2, 0 5318bd22949SKevin Hilman /*normal memory remap register */ 5328bd22949SKevin Hilman MCR p15, 0, r5, c10, c2, 1 5338bd22949SKevin Hilman 5348bd22949SKevin Hilman /* Restore cpsr */ 5358bd22949SKevin Hilman ldmia r3!,{r4} /*load CPSR from SDRAM*/ 5368bd22949SKevin Hilman msr cpsr, r4 /*store cpsr */ 5378bd22949SKevin Hilman 5388bd22949SKevin Hilman /* Enabling MMU here */ 5398bd22949SKevin Hilman mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */ 5408bd22949SKevin Hilman /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/ 5418bd22949SKevin Hilman and r7, #0x7 5428bd22949SKevin Hilman cmp r7, #0x0 5438bd22949SKevin Hilman beq usettbr0 5448bd22949SKevin Hilmanttbr_error: 5458bd22949SKevin Hilman /* More work needs to be done to support N[0:2] value other than 0 5468bd22949SKevin Hilman * So looping here so that the error can be detected 5478bd22949SKevin Hilman */ 5488bd22949SKevin Hilman b ttbr_error 5498bd22949SKevin Hilmanusettbr0: 5508bd22949SKevin Hilman mrc p15, 0, r2, c2, c0, 0 5518bd22949SKevin Hilman ldr r5, ttbrbit_mask 5528bd22949SKevin Hilman and r2, r5 5538bd22949SKevin Hilman mov r4, pc 5548bd22949SKevin Hilman ldr r5, table_index_mask 5558bd22949SKevin Hilman and r4, r5 /* r4 = 31 to 20 bits of pc */ 5568bd22949SKevin Hilman /* Extract the value to be written to table entry */ 5578bd22949SKevin Hilman ldr r1, table_entry 5588bd22949SKevin Hilman add r1, r1, r4 /* r1 has value to be written to table entry*/ 5598bd22949SKevin Hilman /* Getting the address of table entry to modify */ 5608bd22949SKevin Hilman lsr r4, #18 5618bd22949SKevin Hilman add r2, r4 /* r2 has the location which needs to be modified */ 5628bd22949SKevin Hilman /* Storing previous entry of location being modified */ 5638bd22949SKevin Hilman ldr r5, scratchpad_base 5648bd22949SKevin Hilman ldr r4, [r2] 5658bd22949SKevin Hilman str r4, [r5, #0xC0] 5668bd22949SKevin Hilman /* Modify the table entry */ 5678bd22949SKevin Hilman str r1, [r2] 5688bd22949SKevin Hilman /* Storing address of entry being modified 5698bd22949SKevin Hilman * - will be restored after enabling MMU */ 5708bd22949SKevin Hilman ldr r5, scratchpad_base 5718bd22949SKevin Hilman str r2, [r5, #0xC4] 5728bd22949SKevin Hilman 5738bd22949SKevin Hilman mov r0, #0 5748bd22949SKevin Hilman mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer 5758bd22949SKevin Hilman mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array 5768bd22949SKevin Hilman mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB 5778bd22949SKevin Hilman mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB 5788bd22949SKevin Hilman /* Restore control register but dont enable caches here*/ 5798bd22949SKevin Hilman /* Caches will be enabled after restoring MMU table entry */ 5808bd22949SKevin Hilman ldmia r3!, {r4} 5818bd22949SKevin Hilman /* Store previous value of control register in scratchpad */ 5828bd22949SKevin Hilman str r4, [r5, #0xC8] 5838bd22949SKevin Hilman ldr r2, cache_pred_disable_mask 5848bd22949SKevin Hilman and r4, r2 5858bd22949SKevin Hilman mcr p15, 0, r4, c1, c0, 0 5868bd22949SKevin Hilman 5870bd40535SRichard Woodruff/* 588*f7dfe3d8SJean Pihet * ============================== 589*f7dfe3d8SJean Pihet * == Exit point from OFF mode == 590*f7dfe3d8SJean Pihet * ============================== 5910bd40535SRichard Woodruff */ 592*f7dfe3d8SJean Pihet ldmfd sp!, {r0-r12, pc} @ restore regs and return 5938bd22949SKevin Hilman 5941e81bc01SJean Pihet 5951e81bc01SJean Pihet/* 5961e81bc01SJean Pihet * Internal functions 5971e81bc01SJean Pihet */ 5981e81bc01SJean Pihet 5991e81bc01SJean Pihet .text 6001e81bc01SJean PihetENTRY(es3_sdrc_fix) 6011e81bc01SJean Pihet ldr r4, sdrc_syscfg @ get config addr 6021e81bc01SJean Pihet ldr r5, [r4] @ get value 6031e81bc01SJean Pihet tst r5, #0x100 @ is part access blocked 6041e81bc01SJean Pihet it eq 6051e81bc01SJean Pihet biceq r5, r5, #0x100 @ clear bit if set 6061e81bc01SJean Pihet str r5, [r4] @ write back change 6071e81bc01SJean Pihet ldr r4, sdrc_mr_0 @ get config addr 6081e81bc01SJean Pihet ldr r5, [r4] @ get value 6091e81bc01SJean Pihet str r5, [r4] @ write back change 6101e81bc01SJean Pihet ldr r4, sdrc_emr2_0 @ get config addr 6111e81bc01SJean Pihet ldr r5, [r4] @ get value 6121e81bc01SJean Pihet str r5, [r4] @ write back change 6131e81bc01SJean Pihet ldr r4, sdrc_manual_0 @ get config addr 6141e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 6151e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 6161e81bc01SJean Pihet ldr r4, sdrc_mr_1 @ get config addr 6171e81bc01SJean Pihet ldr r5, [r4] @ get value 6181e81bc01SJean Pihet str r5, [r4] @ write back change 6191e81bc01SJean Pihet ldr r4, sdrc_emr2_1 @ get config addr 6201e81bc01SJean Pihet ldr r5, [r4] @ get value 6211e81bc01SJean Pihet str r5, [r4] @ write back change 6221e81bc01SJean Pihet ldr r4, sdrc_manual_1 @ get config addr 6231e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 6241e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 6251e81bc01SJean Pihet bx lr 6261e81bc01SJean Pihet 6271e81bc01SJean Pihetsdrc_syscfg: 6281e81bc01SJean Pihet .word SDRC_SYSCONFIG_P 6291e81bc01SJean Pihetsdrc_mr_0: 6301e81bc01SJean Pihet .word SDRC_MR_0_P 6311e81bc01SJean Pihetsdrc_emr2_0: 6321e81bc01SJean Pihet .word SDRC_EMR2_0_P 6331e81bc01SJean Pihetsdrc_manual_0: 6341e81bc01SJean Pihet .word SDRC_MANUAL_0_P 6351e81bc01SJean Pihetsdrc_mr_1: 6361e81bc01SJean Pihet .word SDRC_MR_1_P 6371e81bc01SJean Pihetsdrc_emr2_1: 6381e81bc01SJean Pihet .word SDRC_EMR2_1_P 6391e81bc01SJean Pihetsdrc_manual_1: 6401e81bc01SJean Pihet .word SDRC_MANUAL_1_P 6411e81bc01SJean PihetENTRY(es3_sdrc_fix_sz) 6421e81bc01SJean Pihet .word . - es3_sdrc_fix 6431e81bc01SJean Pihet 64489139dceSPeter 'p2' De Schrijver/* Make sure SDRC accesses are ok */ 64589139dceSPeter 'p2' De Schrijverwait_sdrc_ok: 6469d93b8a2SPeter 'p2' De Schrijver 6479d93b8a2SPeter 'p2' De Schrijver/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */ 6489d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest_ckgen 6499d93b8a2SPeter 'p2' De Schrijverwait_dpll3_lock: 65089139dceSPeter 'p2' De Schrijver ldr r5, [r4] 6519d93b8a2SPeter 'p2' De Schrijver tst r5, #1 6529d93b8a2SPeter 'p2' De Schrijver beq wait_dpll3_lock 6539d93b8a2SPeter 'p2' De Schrijver 6549d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest1_core 6559d93b8a2SPeter 'p2' De Schrijverwait_sdrc_ready: 6569d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 6579d93b8a2SPeter 'p2' De Schrijver tst r5, #0x2 6589d93b8a2SPeter 'p2' De Schrijver bne wait_sdrc_ready 6599d93b8a2SPeter 'p2' De Schrijver /* allow DLL powerdown upon hw idle req */ 6608bd22949SKevin Hilman ldr r4, sdrc_power 6618bd22949SKevin Hilman ldr r5, [r4] 6628bd22949SKevin Hilman bic r5, r5, #0x40 6638bd22949SKevin Hilman str r5, [r4] 6649d93b8a2SPeter 'p2' De Schrijveris_dll_in_lock_mode: 6659d93b8a2SPeter 'p2' De Schrijver 66689139dceSPeter 'p2' De Schrijver /* Is dll in lock mode? */ 66789139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 66889139dceSPeter 'p2' De Schrijver ldr r5, [r4] 66989139dceSPeter 'p2' De Schrijver tst r5, #0x4 67089139dceSPeter 'p2' De Schrijver bxne lr 67189139dceSPeter 'p2' De Schrijver /* wait till dll locks */ 6729d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_timed: 6739d93b8a2SPeter 'p2' De Schrijver ldr r4, wait_dll_lock_counter 6749d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 6759d93b8a2SPeter 'p2' De Schrijver str r4, wait_dll_lock_counter 67689139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_status 6779d93b8a2SPeter 'p2' De Schrijver mov r6, #8 /* Wait 20uS for lock */ 6789d93b8a2SPeter 'p2' De Schrijverwait_dll_lock: 6799d93b8a2SPeter 'p2' De Schrijver subs r6, r6, #0x1 6809d93b8a2SPeter 'p2' De Schrijver beq kick_dll 68189139dceSPeter 'p2' De Schrijver ldr r5, [r4] 68289139dceSPeter 'p2' De Schrijver and r5, r5, #0x4 68389139dceSPeter 'p2' De Schrijver cmp r5, #0x4 68489139dceSPeter 'p2' De Schrijver bne wait_dll_lock 6858bd22949SKevin Hilman bx lr 68689139dceSPeter 'p2' De Schrijver 6879d93b8a2SPeter 'p2' De Schrijver /* disable/reenable DLL if not locked */ 6889d93b8a2SPeter 'p2' De Schrijverkick_dll: 6899d93b8a2SPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 6909d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 6919d93b8a2SPeter 'p2' De Schrijver mov r6, r5 6929d93b8a2SPeter 'p2' De Schrijver bic r6, #(1<<3) /* disable dll */ 6939d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 6949d93b8a2SPeter 'p2' De Schrijver dsb 6959d93b8a2SPeter 'p2' De Schrijver orr r6, r6, #(1<<3) /* enable dll */ 6969d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 6979d93b8a2SPeter 'p2' De Schrijver dsb 6989d93b8a2SPeter 'p2' De Schrijver ldr r4, kick_counter 6999d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 7009d93b8a2SPeter 'p2' De Schrijver str r4, kick_counter 7019d93b8a2SPeter 'p2' De Schrijver b wait_dll_lock_timed 7029d93b8a2SPeter 'p2' De Schrijver 70389139dceSPeter 'p2' De Schrijvercm_idlest1_core: 70489139dceSPeter 'p2' De Schrijver .word CM_IDLEST1_CORE_V 7059d93b8a2SPeter 'p2' De Schrijvercm_idlest_ckgen: 7069d93b8a2SPeter 'p2' De Schrijver .word CM_IDLEST_CKGEN_V 70789139dceSPeter 'p2' De Schrijversdrc_dlla_status: 70889139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_STATUS_V 70989139dceSPeter 'p2' De Schrijversdrc_dlla_ctrl: 71089139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_CTRL_V 7110795a75aSTero Kristopm_prepwstst_core_p: 7120795a75aSTero Kristo .word PM_PREPWSTST_CORE_P 7138bd22949SKevin Hilmanpm_pwstctrl_mpu: 7148bd22949SKevin Hilman .word PM_PWSTCTRL_MPU_P 7158bd22949SKevin Hilmanscratchpad_base: 7168bd22949SKevin Hilman .word SCRATCHPAD_BASE_P 7170795a75aSTero Kristosram_base: 7180795a75aSTero Kristo .word SRAM_BASE_P + 0x8000 7198bd22949SKevin Hilmansdrc_power: 7208bd22949SKevin Hilman .word SDRC_POWER_V 7218bd22949SKevin Hilmanttbrbit_mask: 7228bd22949SKevin Hilman .word 0xFFFFC000 7238bd22949SKevin Hilmantable_index_mask: 7248bd22949SKevin Hilman .word 0xFFF00000 7258bd22949SKevin Hilmantable_entry: 7268bd22949SKevin Hilman .word 0x00000C02 7278bd22949SKevin Hilmancache_pred_disable_mask: 7288bd22949SKevin Hilman .word 0xFFFFE7FB 72927d59a4aSTero Kristocontrol_stat: 73027d59a4aSTero Kristo .word CONTROL_STAT 731458e999eSNishanth Menoncontrol_mem_rta: 732458e999eSNishanth Menon .word CONTROL_MEM_RTA_CTRL 7330bd40535SRichard Woodruffkernel_flush: 7340bd40535SRichard Woodruff .word v7_flush_dcache_all 735c4236d2eSPeter 'p2' De Schrijverl2dis_3630: 736c4236d2eSPeter 'p2' De Schrijver .word 0 7379d93b8a2SPeter 'p2' De Schrijver /* 7389d93b8a2SPeter 'p2' De Schrijver * When exporting to userspace while the counters are in SRAM, 7399d93b8a2SPeter 'p2' De Schrijver * these 2 words need to be at the end to facilitate retrival! 7409d93b8a2SPeter 'p2' De Schrijver */ 7419d93b8a2SPeter 'p2' De Schrijverkick_counter: 7429d93b8a2SPeter 'p2' De Schrijver .word 0 7439d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_counter: 7449d93b8a2SPeter 'p2' De Schrijver .word 0 745*f7dfe3d8SJean Pihet 7468bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend_sz) 7478bd22949SKevin Hilman .word . - omap34xx_cpu_suspend 748