18bd22949SKevin Hilman/* 28bd22949SKevin Hilman * (C) Copyright 2007 38bd22949SKevin Hilman * Texas Instruments 48bd22949SKevin Hilman * Karthik Dasu <karthik-dp@ti.com> 58bd22949SKevin Hilman * 68bd22949SKevin Hilman * (C) Copyright 2004 78bd22949SKevin Hilman * Texas Instruments, <www.ti.com> 88bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 98bd22949SKevin Hilman * 108bd22949SKevin Hilman * This program is free software; you can redistribute it and/or 118bd22949SKevin Hilman * modify it under the terms of the GNU General Public License as 128bd22949SKevin Hilman * published by the Free Software Foundation; either version 2 of 138bd22949SKevin Hilman * the License, or (at your option) any later version. 148bd22949SKevin Hilman * 158bd22949SKevin Hilman * This program is distributed in the hope that it will be useful, 168bd22949SKevin Hilman * but WITHOUT ANY WARRANTY; without even the implied warranty of 178bd22949SKevin Hilman * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 188bd22949SKevin Hilman * GNU General Public License for more details. 198bd22949SKevin Hilman * 208bd22949SKevin Hilman * You should have received a copy of the GNU General Public License 218bd22949SKevin Hilman * along with this program; if not, write to the Free Software 228bd22949SKevin Hilman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 238bd22949SKevin Hilman * MA 02111-1307 USA 248bd22949SKevin Hilman */ 258bd22949SKevin Hilman#include <linux/linkage.h> 268bd22949SKevin Hilman 27ee0839c2STony Lindgren#include <asm/assembler.h> 28ee0839c2STony Lindgren 29c49f34bcSTony Lindgren#include "omap34xx.h" 30ee0839c2STony Lindgren#include "iomap.h" 31ff4ae5d9SPaul Walmsley#include "cm3xxx.h" 32139563adSPaul Walmsley#include "prm3xxx.h" 338bd22949SKevin Hilman#include "sdrc.h" 34bf027ca1STony Lindgren#include "sram.h" 354814ced5SPaul Walmsley#include "control.h" 368bd22949SKevin Hilman 37fe360e1cSJean Pihet/* 38fe360e1cSJean Pihet * Registers access definitions 39fe360e1cSJean Pihet */ 40fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_OFFS 0xc 41fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ 42fe360e1cSJean Pihet (SDRC_SCRATCHPAD_SEM_OFFS) 43fe360e1cSJean Pihet#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ 44fe360e1cSJean Pihet OMAP3430_PM_PREPWSTST 4537903009SAbhijit Pagare#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL 4689139dceSPeter 'p2' De Schrijver#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) 479d93b8a2SPeter 'p2' De Schrijver#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) 48fe360e1cSJean Pihet#define SRAM_BASE_P OMAP3_SRAM_PA 49fe360e1cSJean Pihet#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS 50fe360e1cSJean Pihet#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ 51fe360e1cSJean Pihet OMAP36XX_CONTROL_MEM_RTA_CTRL) 52fe360e1cSJean Pihet 53fe360e1cSJean Pihet/* Move this as correct place is available */ 54fe360e1cSJean Pihet#define SCRATCHPAD_MEM_OFFS 0x310 55fe360e1cSJean Pihet#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ 56fe360e1cSJean Pihet OMAP343X_CONTROL_MEM_WKUP +\ 57fe360e1cSJean Pihet SCRATCHPAD_MEM_OFFS) 588bd22949SKevin Hilman#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 590795a75aSTero Kristo#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) 600795a75aSTero Kristo#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) 610795a75aSTero Kristo#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) 620795a75aSTero Kristo#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) 630795a75aSTero Kristo#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) 640795a75aSTero Kristo#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) 650795a75aSTero Kristo#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) 6689139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 6789139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 688bd22949SKevin Hilman 69dd313947SDave Martin/* 70dd313947SDave Martin * This file needs be built unconditionally as ARM to interoperate correctly 71dd313947SDave Martin * with non-Thumb-2-capable firmware. 72dd313947SDave Martin */ 73dd313947SDave Martin .arm 74a89b6f00SRajendra Nayak 75d3cdfd2aSJean Pihet/* 76d3cdfd2aSJean Pihet * API functions 77d3cdfd2aSJean Pihet */ 78a89b6f00SRajendra Nayak 791e81bc01SJean Pihet .text 80c4236d2eSPeter 'p2' De Schrijver/* 81c4236d2eSPeter 'p2' De Schrijver * L2 cache needs to be toggled for stable OFF mode functionality on 3630. 821e81bc01SJean Pihet * This function sets up a flag that will allow for this toggling to take 83f7dfe3d8SJean Pihet * place on 3630. Hopefully some version in the future may not need this. 84c4236d2eSPeter 'p2' De Schrijver */ 85c4236d2eSPeter 'p2' De SchrijverENTRY(enable_omap3630_toggle_l2_on_restore) 86c4236d2eSPeter 'p2' De Schrijver stmfd sp!, {lr} @ save registers on stack 87c4236d2eSPeter 'p2' De Schrijver /* Setup so that we will disable and enable l2 */ 88c4236d2eSPeter 'p2' De Schrijver mov r1, #0x1 89eeaf9646STony Lindgren adrl r3, l2dis_3630_offset @ may be too distant for plain adr 90eeaf9646STony Lindgren ldr r2, [r3] @ value for offset 91eeaf9646STony Lindgren str r1, [r2, r3] @ write to l2dis_3630 92c4236d2eSPeter 'p2' De Schrijver ldmfd sp!, {pc} @ restore regs and return 93dd313947SDave MartinENDPROC(enable_omap3630_toggle_l2_on_restore) 94c4236d2eSPeter 'p2' De Schrijver 95a5311d4dSTony Lindgren/* 96*d09220a8STony Lindgren * Function to call rom code to save secure ram context. 97*d09220a8STony Lindgren * 98*d09220a8STony Lindgren * r0 = physical address of the parameters 99a5311d4dSTony Lindgren */ 10027d59a4aSTero KristoENTRY(save_secure_ram_context) 101857c1b81SRussell King stmfd sp!, {r4 - r11, lr} @ save registers on stack 102*d09220a8STony Lindgren mov r3, r0 @ physical address of parameters 10327d59a4aSTero Kristo mov r0, #25 @ set service ID for PPA 10427d59a4aSTero Kristo mov r12, r0 @ copy secure service ID in r12 10527d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 106ba50ea7eSKalle Jokiniemi mov r2, #4 @ set some flags in r2, r6 10727d59a4aSTero Kristo mov r6, #0xff 1084444d712SSantosh Shilimkar dsb @ data write barrier 1094444d712SSantosh Shilimkar dmb @ data memory barrier 11076d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 11127d59a4aSTero Kristo nop 11227d59a4aSTero Kristo nop 11327d59a4aSTero Kristo nop 11427d59a4aSTero Kristo nop 115857c1b81SRussell King ldmfd sp!, {r4 - r11, pc} 116dd313947SDave MartinENDPROC(save_secure_ram_context) 117a5311d4dSTony Lindgren 1188bd22949SKevin Hilman/* 119f7dfe3d8SJean Pihet * ====================== 120f7dfe3d8SJean Pihet * == Idle entry point == 121f7dfe3d8SJean Pihet * ====================== 122f7dfe3d8SJean Pihet */ 123f7dfe3d8SJean Pihet 124f7dfe3d8SJean Pihet/* 1258bd22949SKevin Hilman * Forces OMAP into idle state 1268bd22949SKevin Hilman * 127f7dfe3d8SJean Pihet * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed 128f7dfe3d8SJean Pihet * and executes the WFI instruction. Calling WFI effectively changes the 129f7dfe3d8SJean Pihet * power domains states to the desired target power states. 1308bd22949SKevin Hilman * 131f7dfe3d8SJean Pihet * 132f7dfe3d8SJean Pihet * Notes: 13346e130d2SJean Pihet * - only the minimum set of functions gets copied to internal SRAM at boot 13446e130d2SJean Pihet * and after wake-up from OFF mode, cf. omap_push_sram_idle. The function 13546e130d2SJean Pihet * pointers in SDRAM or SRAM are called depending on the desired low power 13646e130d2SJean Pihet * target state. 137f7dfe3d8SJean Pihet * - when the OMAP wakes up it continues at different execution points 138f7dfe3d8SJean Pihet * depending on the low power mode (non-OFF vs OFF modes), 139f7dfe3d8SJean Pihet * cf. 'Resume path for xxx mode' comments. 1408bd22949SKevin Hilman */ 141b6338bdcSJean Pihet .align 3 1428bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend) 143857c1b81SRussell King stmfd sp!, {r4 - r11, lr} @ save registers on stack 144d3cdfd2aSJean Pihet 145f7dfe3d8SJean Pihet /* 146cbe26349SRussell King * r0 contains information about saving context: 147f7dfe3d8SJean Pihet * 0 - No context lost 148f7dfe3d8SJean Pihet * 1 - Only L1 and logic lost 149c9749a35SSantosh Shilimkar * 2 - Only L2 lost (Even L1 is retained we clean it along with L2) 150c9749a35SSantosh Shilimkar * 3 - Both L1 and L2 lost and logic lost 151f7dfe3d8SJean Pihet */ 152f7dfe3d8SJean Pihet 15346e130d2SJean Pihet /* 15446e130d2SJean Pihet * For OFF mode: save context and jump to WFI in SDRAM (omap3_do_wfi) 15546e130d2SJean Pihet * For non-OFF modes: jump to the WFI code in SRAM (omap3_do_wfi_sram) 15646e130d2SJean Pihet */ 15746e130d2SJean Pihet ldr r4, omap3_do_wfi_sram_addr 15846e130d2SJean Pihet ldr r5, [r4] 159cbe26349SRussell King cmp r0, #0x0 @ If no context save required, 16046e130d2SJean Pihet bxeq r5 @ jump to the WFI code in SRAM 16146e130d2SJean Pihet 162f7dfe3d8SJean Pihet 163f7dfe3d8SJean Pihet /* Otherwise fall through to the save context code */ 164f7dfe3d8SJean Pihetsave_context_wfi: 165f7dfe3d8SJean Pihet /* 166f7dfe3d8SJean Pihet * jump out to kernel flush routine 167f7dfe3d8SJean Pihet * - reuse that code is better 168f7dfe3d8SJean Pihet * - it executes in a cached space so is faster than refetch per-block 169f7dfe3d8SJean Pihet * - should be faster and will change with kernel 170f7dfe3d8SJean Pihet * - 'might' have to copy address, load and jump to it 17190625110SSantosh Shilimkar * Flush all data from the L1 data cache before disabling 17290625110SSantosh Shilimkar * SCTLR.C bit. 173f7dfe3d8SJean Pihet */ 174f7dfe3d8SJean Pihet ldr r1, kernel_flush 175f7dfe3d8SJean Pihet mov lr, pc 176f7dfe3d8SJean Pihet bx r1 177f7dfe3d8SJean Pihet 17890625110SSantosh Shilimkar /* 17990625110SSantosh Shilimkar * Clear the SCTLR.C bit to prevent further data cache 18090625110SSantosh Shilimkar * allocation. Clearing SCTLR.C would make all the data accesses 18190625110SSantosh Shilimkar * strongly ordered and would not hit the cache. 18290625110SSantosh Shilimkar */ 18390625110SSantosh Shilimkar mrc p15, 0, r0, c1, c0, 0 18490625110SSantosh Shilimkar bic r0, r0, #(1 << 2) @ Disable the C bit 18590625110SSantosh Shilimkar mcr p15, 0, r0, c1, c0, 0 18690625110SSantosh Shilimkar isb 18790625110SSantosh Shilimkar 18890625110SSantosh Shilimkar /* 18990625110SSantosh Shilimkar * Invalidate L1 data cache. Even though only invalidate is 19090625110SSantosh Shilimkar * necessary exported flush API is used here. Doing clean 19190625110SSantosh Shilimkar * on already clean cache would be almost NOP. 192f7dfe3d8SJean Pihet */ 193f7dfe3d8SJean Pihet ldr r1, kernel_flush 194dd313947SDave Martin blx r1 19546e130d2SJean Pihet b omap3_do_wfi 196d8a50941STony LindgrenENDPROC(omap34xx_cpu_suspend) 19746e130d2SJean Pihetomap3_do_wfi_sram_addr: 19846e130d2SJean Pihet .word omap3_do_wfi_sram 19946e130d2SJean Pihetkernel_flush: 20046e130d2SJean Pihet .word v7_flush_dcache_all 20146e130d2SJean Pihet 20246e130d2SJean Pihet/* =================================== 20346e130d2SJean Pihet * == WFI instruction => Enter idle == 20446e130d2SJean Pihet * =================================== 20546e130d2SJean Pihet */ 20646e130d2SJean Pihet 20746e130d2SJean Pihet/* 20846e130d2SJean Pihet * Do WFI instruction 20946e130d2SJean Pihet * Includes the resume path for non-OFF modes 21046e130d2SJean Pihet * 21146e130d2SJean Pihet * This code gets copied to internal SRAM and is accessible 21246e130d2SJean Pihet * from both SDRAM and SRAM: 21346e130d2SJean Pihet * - executed from SRAM for non-off modes (omap3_do_wfi_sram), 21446e130d2SJean Pihet * - executed from SDRAM for OFF mode (omap3_do_wfi). 21546e130d2SJean Pihet */ 21646e130d2SJean Pihet .align 3 21746e130d2SJean PihetENTRY(omap3_do_wfi) 2188bd22949SKevin Hilman ldr r4, sdrc_power @ read the SDRC_POWER register 2198bd22949SKevin Hilman ldr r5, [r4] @ read the contents of SDRC_POWER 2208bd22949SKevin Hilman orr r5, r5, #0x40 @ enable self refresh on idle req 2218bd22949SKevin Hilman str r5, [r4] @ write back to SDRC_POWER register 2228bd22949SKevin Hilman 2238bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 2244444d712SSantosh Shilimkar dsb 2254444d712SSantosh Shilimkar dmb 2268bd22949SKevin Hilman 227f7dfe3d8SJean Pihet/* 228f7dfe3d8SJean Pihet * =================================== 229f7dfe3d8SJean Pihet * == WFI instruction => Enter idle == 230f7dfe3d8SJean Pihet * =================================== 231f7dfe3d8SJean Pihet */ 2328bd22949SKevin Hilman wfi @ wait for interrupt 2338bd22949SKevin Hilman 234f7dfe3d8SJean Pihet/* 235f7dfe3d8SJean Pihet * =================================== 236f7dfe3d8SJean Pihet * == Resume path for non-OFF modes == 237f7dfe3d8SJean Pihet * =================================== 238f7dfe3d8SJean Pihet */ 2398bd22949SKevin Hilman nop 2408bd22949SKevin Hilman nop 2418bd22949SKevin Hilman nop 2428bd22949SKevin Hilman nop 2438bd22949SKevin Hilman nop 2448bd22949SKevin Hilman nop 2458bd22949SKevin Hilman nop 2468bd22949SKevin Hilman nop 2478bd22949SKevin Hilman nop 2488bd22949SKevin Hilman nop 2498bd22949SKevin Hilman 25046e130d2SJean Pihet/* 25146e130d2SJean Pihet * This function implements the erratum ID i581 WA: 25246e130d2SJean Pihet * SDRC state restore before accessing the SDRAM 25346e130d2SJean Pihet * 25446e130d2SJean Pihet * Only used at return from non-OFF mode. For OFF 25546e130d2SJean Pihet * mode the ROM code configures the SDRC and 25646e130d2SJean Pihet * the DPLL before calling the restore code directly 25746e130d2SJean Pihet * from DDR. 25846e130d2SJean Pihet */ 25946e130d2SJean Pihet 26046e130d2SJean Pihet/* Make sure SDRC accesses are ok */ 26146e130d2SJean Pihetwait_sdrc_ok: 26246e130d2SJean Pihet 26346e130d2SJean Pihet/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */ 26446e130d2SJean Pihet ldr r4, cm_idlest_ckgen 26546e130d2SJean Pihetwait_dpll3_lock: 26646e130d2SJean Pihet ldr r5, [r4] 26746e130d2SJean Pihet tst r5, #1 26846e130d2SJean Pihet beq wait_dpll3_lock 26946e130d2SJean Pihet 27046e130d2SJean Pihet ldr r4, cm_idlest1_core 27146e130d2SJean Pihetwait_sdrc_ready: 27246e130d2SJean Pihet ldr r5, [r4] 27346e130d2SJean Pihet tst r5, #0x2 27446e130d2SJean Pihet bne wait_sdrc_ready 27546e130d2SJean Pihet /* allow DLL powerdown upon hw idle req */ 27646e130d2SJean Pihet ldr r4, sdrc_power 27746e130d2SJean Pihet ldr r5, [r4] 27846e130d2SJean Pihet bic r5, r5, #0x40 27946e130d2SJean Pihet str r5, [r4] 28046e130d2SJean Pihet 28146e130d2SJean Pihetis_dll_in_lock_mode: 28246e130d2SJean Pihet /* Is dll in lock mode? */ 28346e130d2SJean Pihet ldr r4, sdrc_dlla_ctrl 28446e130d2SJean Pihet ldr r5, [r4] 28546e130d2SJean Pihet tst r5, #0x4 28646e130d2SJean Pihet bne exit_nonoff_modes @ Return if locked 28746e130d2SJean Pihet /* wait till dll locks */ 28846e130d2SJean Pihetwait_dll_lock_timed: 28946e130d2SJean Pihet ldr r4, sdrc_dlla_status 29046e130d2SJean Pihet /* Wait 20uS for lock */ 29146e130d2SJean Pihet mov r6, #8 29246e130d2SJean Pihetwait_dll_lock: 29346e130d2SJean Pihet subs r6, r6, #0x1 29446e130d2SJean Pihet beq kick_dll 29546e130d2SJean Pihet ldr r5, [r4] 29646e130d2SJean Pihet and r5, r5, #0x4 29746e130d2SJean Pihet cmp r5, #0x4 29846e130d2SJean Pihet bne wait_dll_lock 29946e130d2SJean Pihet b exit_nonoff_modes @ Return when locked 30046e130d2SJean Pihet 30146e130d2SJean Pihet /* disable/reenable DLL if not locked */ 30246e130d2SJean Pihetkick_dll: 30346e130d2SJean Pihet ldr r4, sdrc_dlla_ctrl 30446e130d2SJean Pihet ldr r5, [r4] 30546e130d2SJean Pihet mov r6, r5 30646e130d2SJean Pihet bic r6, #(1<<3) @ disable dll 30746e130d2SJean Pihet str r6, [r4] 30846e130d2SJean Pihet dsb 30946e130d2SJean Pihet orr r6, r6, #(1<<3) @ enable dll 31046e130d2SJean Pihet str r6, [r4] 31146e130d2SJean Pihet dsb 31246e130d2SJean Pihet b wait_dll_lock_timed 31346e130d2SJean Pihet 31446e130d2SJean Pihetexit_nonoff_modes: 31546e130d2SJean Pihet /* Re-enable C-bit if needed */ 31690625110SSantosh Shilimkar mrc p15, 0, r0, c1, c0, 0 31790625110SSantosh Shilimkar tst r0, #(1 << 2) @ Check C bit enabled? 31890625110SSantosh Shilimkar orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared 31990625110SSantosh Shilimkar mcreq p15, 0, r0, c1, c0, 0 32090625110SSantosh Shilimkar isb 32190625110SSantosh Shilimkar 322f7dfe3d8SJean Pihet/* 323f7dfe3d8SJean Pihet * =================================== 324f7dfe3d8SJean Pihet * == Exit point from non-OFF modes == 325f7dfe3d8SJean Pihet * =================================== 326f7dfe3d8SJean Pihet */ 327857c1b81SRussell King ldmfd sp!, {r4 - r11, pc} @ restore regs and return 328d8a50941STony LindgrenENDPROC(omap3_do_wfi) 32946e130d2SJean Pihetsdrc_power: 33046e130d2SJean Pihet .word SDRC_POWER_V 33146e130d2SJean Pihetcm_idlest1_core: 33246e130d2SJean Pihet .word CM_IDLEST1_CORE_V 33346e130d2SJean Pihetcm_idlest_ckgen: 33446e130d2SJean Pihet .word CM_IDLEST_CKGEN_V 33546e130d2SJean Pihetsdrc_dlla_status: 33646e130d2SJean Pihet .word SDRC_DLLA_STATUS_V 33746e130d2SJean Pihetsdrc_dlla_ctrl: 33846e130d2SJean Pihet .word SDRC_DLLA_CTRL_V 33946e130d2SJean PihetENTRY(omap3_do_wfi_sz) 34046e130d2SJean Pihet .word . - omap3_do_wfi 34146e130d2SJean Pihet 342f7dfe3d8SJean Pihet 343f7dfe3d8SJean Pihet/* 344f7dfe3d8SJean Pihet * ============================== 345f7dfe3d8SJean Pihet * == Resume path for OFF mode == 346f7dfe3d8SJean Pihet * ============================== 347f7dfe3d8SJean Pihet */ 348f7dfe3d8SJean Pihet 349f7dfe3d8SJean Pihet/* 350f7dfe3d8SJean Pihet * The restore_* functions are called by the ROM code 351f7dfe3d8SJean Pihet * when back from WFI in OFF mode. 352f7dfe3d8SJean Pihet * Cf. the get_*restore_pointer functions. 353f7dfe3d8SJean Pihet * 354f7dfe3d8SJean Pihet * restore_es3: applies to 34xx >= ES3.0 355f7dfe3d8SJean Pihet * restore_3630: applies to 36xx 356f7dfe3d8SJean Pihet * restore: common code for 3xxx 35746e130d2SJean Pihet * 35846e130d2SJean Pihet * Note: when back from CORE and MPU OFF mode we are running 35946e130d2SJean Pihet * from SDRAM, without MMU, without the caches and prediction. 36046e130d2SJean Pihet * Also the SRAM content has been cleared. 361f7dfe3d8SJean Pihet */ 36214c79bbeSKevin HilmanENTRY(omap3_restore_es3) 3630795a75aSTero Kristo ldr r5, pm_prepwstst_core_p 3640795a75aSTero Kristo ldr r4, [r5] 3650795a75aSTero Kristo and r4, r4, #0x3 3660795a75aSTero Kristo cmp r4, #0x0 @ Check if previous power state of CORE is OFF 36746e130d2SJean Pihet bne omap3_restore @ Fall through to OMAP3 common code 3680795a75aSTero Kristo adr r0, es3_sdrc_fix 3690795a75aSTero Kristo ldr r1, sram_base 3700795a75aSTero Kristo ldr r2, es3_sdrc_fix_sz 3710795a75aSTero Kristo mov r2, r2, ror #2 3720795a75aSTero Kristocopy_to_sram: 3730795a75aSTero Kristo ldmia r0!, {r3} @ val = *src 3740795a75aSTero Kristo stmia r1!, {r3} @ *dst = val 3750795a75aSTero Kristo subs r2, r2, #0x1 @ num_words-- 3760795a75aSTero Kristo bne copy_to_sram 3770795a75aSTero Kristo ldr r1, sram_base 3780795a75aSTero Kristo blx r1 37946e130d2SJean Pihet b omap3_restore @ Fall through to OMAP3 common code 38014c79bbeSKevin HilmanENDPROC(omap3_restore_es3) 381458e999eSNishanth Menon 38214c79bbeSKevin HilmanENTRY(omap3_restore_3630) 383458e999eSNishanth Menon ldr r1, pm_prepwstst_core_p 384458e999eSNishanth Menon ldr r2, [r1] 385458e999eSNishanth Menon and r2, r2, #0x3 386458e999eSNishanth Menon cmp r2, #0x0 @ Check if previous power state of CORE is OFF 38746e130d2SJean Pihet bne omap3_restore @ Fall through to OMAP3 common code 388458e999eSNishanth Menon /* Disable RTA before giving control */ 389458e999eSNishanth Menon ldr r1, control_mem_rta 390458e999eSNishanth Menon mov r2, #OMAP36XX_RTA_DISABLE 391458e999eSNishanth Menon str r2, [r1] 39214c79bbeSKevin HilmanENDPROC(omap3_restore_3630) 393f7dfe3d8SJean Pihet 394f7dfe3d8SJean Pihet /* Fall through to common code for the remaining logic */ 395f7dfe3d8SJean Pihet 39614c79bbeSKevin HilmanENTRY(omap3_restore) 397f7dfe3d8SJean Pihet /* 3982637ce30SRussell King * Read the pwstctrl register to check the reason for mpu reset. 3992637ce30SRussell King * This tells us what was lost. 400f7dfe3d8SJean Pihet */ 4018bd22949SKevin Hilman ldr r1, pm_pwstctrl_mpu 4028bd22949SKevin Hilman ldr r2, [r1] 4038bd22949SKevin Hilman and r2, r2, #0x3 4048bd22949SKevin Hilman cmp r2, #0x0 @ Check if target power state was OFF or RET 4058bd22949SKevin Hilman bne logic_l1_restore 406c4236d2eSPeter 'p2' De Schrijver 407eeaf9646STony Lindgren adr r1, l2dis_3630_offset @ address for offset 408eeaf9646STony Lindgren ldr r0, [r1] @ value for offset 409eeaf9646STony Lindgren ldr r0, [r1, r0] @ value at l2dis_3630 410c4236d2eSPeter 'p2' De Schrijver cmp r0, #0x1 @ should we disable L2 on 3630? 411c4236d2eSPeter 'p2' De Schrijver bne skipl2dis 412c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r0, c1, c0, 1 413c4236d2eSPeter 'p2' De Schrijver bic r0, r0, #2 @ disable L2 cache 414c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r0, c1, c0, 1 415c4236d2eSPeter 'p2' De Schrijverskipl2dis: 41627d59a4aSTero Kristo ldr r0, control_stat 41727d59a4aSTero Kristo ldr r1, [r0] 41827d59a4aSTero Kristo and r1, #0x700 41927d59a4aSTero Kristo cmp r1, #0x300 42027d59a4aSTero Kristo beq l2_inv_gp 4210a0b1327STony Lindgren adr r0, l2_inv_api_params_offset 4220a0b1327STony Lindgren ldr r3, [r0] 4230a0b1327STony Lindgren add r3, r3, r0 @ r3 points to dummy parameters 42427d59a4aSTero Kristo mov r0, #40 @ set service ID for PPA 42527d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 42627d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 42727d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 42827d59a4aSTero Kristo mov r6, #0xff 4294444d712SSantosh Shilimkar dsb @ data write barrier 4304444d712SSantosh Shilimkar dmb @ data memory barrier 43176d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 43227d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 43327d59a4aSTero Kristo mov r0, #42 @ set service ID for PPA 43427d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 43527d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 43627d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 43727d59a4aSTero Kristo mov r6, #0xff 438a087cad9STero Kristo ldr r4, scratchpad_base 439a087cad9STero Kristo ldr r3, [r4, #0xBC] @ r3 points to parameters 4404444d712SSantosh Shilimkar dsb @ data write barrier 4414444d712SSantosh Shilimkar dmb @ data memory barrier 44276d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 44327d59a4aSTero Kristo 44479dcfdd4STero Kristo#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 44579dcfdd4STero Kristo /* Restore L2 aux control register */ 44679dcfdd4STero Kristo @ set service ID for PPA 44779dcfdd4STero Kristo mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 44879dcfdd4STero Kristo mov r12, r0 @ copy service ID in r12 44979dcfdd4STero Kristo mov r1, #0 @ set task ID for ROM code in r1 45079dcfdd4STero Kristo mov r2, #4 @ set some flags in r2, r6 45179dcfdd4STero Kristo mov r6, #0xff 45279dcfdd4STero Kristo ldr r4, scratchpad_base 45379dcfdd4STero Kristo ldr r3, [r4, #0xBC] 45479dcfdd4STero Kristo adds r3, r3, #8 @ r3 points to parameters 4554444d712SSantosh Shilimkar dsb @ data write barrier 4564444d712SSantosh Shilimkar dmb @ data memory barrier 45776d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 45879dcfdd4STero Kristo#endif 45927d59a4aSTero Kristo b logic_l1_restore 460bb1c9034SJean Pihet 461dd313947SDave Martin .align 4620a0b1327STony Lindgrenl2_inv_api_params_offset: 4630a0b1327STony Lindgren .long l2_inv_api_params - . 46427d59a4aSTero Kristol2_inv_gp: 4658bd22949SKevin Hilman /* Execute smi to invalidate L2 cache */ 466bb1c9034SJean Pihet mov r12, #0x1 @ set up to invalidate L2 46776d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 46827d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 469a087cad9STero Kristo ldr r4, scratchpad_base 470a087cad9STero Kristo ldr r3, [r4,#0xBC] 471a087cad9STero Kristo ldr r0, [r3,#4] 47227d59a4aSTero Kristo mov r12, #0x3 47376d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 47479dcfdd4STero Kristo ldr r4, scratchpad_base 47579dcfdd4STero Kristo ldr r3, [r4,#0xBC] 47679dcfdd4STero Kristo ldr r0, [r3,#12] 47779dcfdd4STero Kristo mov r12, #0x2 47876d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 4798bd22949SKevin Hilmanlogic_l1_restore: 480eeaf9646STony Lindgren adr r0, l2dis_3630_offset @ adress for offset 481eeaf9646STony Lindgren ldr r1, [r0] @ value for offset 482eeaf9646STony Lindgren ldr r1, [r0, r1] @ value at l2dis_3630 483bb1c9034SJean Pihet cmp r1, #0x1 @ Test if L2 re-enable needed on 3630 484c4236d2eSPeter 'p2' De Schrijver bne skipl2reen 485c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r1, c1, c0, 1 486c4236d2eSPeter 'p2' De Schrijver orr r1, r1, #2 @ re-enable L2 cache 487c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r1, c1, c0, 1 488c4236d2eSPeter 'p2' De Schrijverskipl2reen: 4898bd22949SKevin Hilman 490076f2cc4SRussell King /* Now branch to the common CPU resume function */ 491076f2cc4SRussell King b cpu_resume 49214c79bbeSKevin HilmanENDPROC(omap3_restore) 49346f557cbSSantosh Shilimkar 494076f2cc4SRussell King .ltorg 4951e81bc01SJean Pihet 4961e81bc01SJean Pihet/* 49746e130d2SJean Pihet * Local variables 49846e130d2SJean Pihet */ 49946e130d2SJean Pihetpm_prepwstst_core_p: 50046e130d2SJean Pihet .word PM_PREPWSTST_CORE_P 50146e130d2SJean Pihetpm_pwstctrl_mpu: 50246e130d2SJean Pihet .word PM_PWSTCTRL_MPU_P 50346e130d2SJean Pihetscratchpad_base: 50446e130d2SJean Pihet .word SCRATCHPAD_BASE_P 50546e130d2SJean Pihetsram_base: 50646e130d2SJean Pihet .word SRAM_BASE_P + 0x8000 50746e130d2SJean Pihetcontrol_stat: 50846e130d2SJean Pihet .word CONTROL_STAT 50946e130d2SJean Pihetcontrol_mem_rta: 51046e130d2SJean Pihet .word CONTROL_MEM_RTA_CTRL 511eeaf9646STony Lindgrenl2dis_3630_offset: 512eeaf9646STony Lindgren .long l2dis_3630 - . 513eeaf9646STony Lindgren 514eeaf9646STony Lindgren .data 5151abd3502SRussell King .align 2 51646e130d2SJean Pihetl2dis_3630: 51746e130d2SJean Pihet .word 0 51846e130d2SJean Pihet 5190a0b1327STony Lindgren .data 5201abd3502SRussell King .align 2 5210a0b1327STony Lindgrenl2_inv_api_params: 5220a0b1327STony Lindgren .word 0x1, 0x00 5230a0b1327STony Lindgren 52446e130d2SJean Pihet/* 5251e81bc01SJean Pihet * Internal functions 5261e81bc01SJean Pihet */ 5271e81bc01SJean Pihet 52846e130d2SJean Pihet/* 52946e130d2SJean Pihet * This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 53046e130d2SJean Pihet * Copied to and run from SRAM in order to reconfigure the SDRC parameters. 53146e130d2SJean Pihet */ 5321e81bc01SJean Pihet .text 533dd313947SDave Martin .align 3 5341e81bc01SJean PihetENTRY(es3_sdrc_fix) 5351e81bc01SJean Pihet ldr r4, sdrc_syscfg @ get config addr 5361e81bc01SJean Pihet ldr r5, [r4] @ get value 5371e81bc01SJean Pihet tst r5, #0x100 @ is part access blocked 5381e81bc01SJean Pihet it eq 5391e81bc01SJean Pihet biceq r5, r5, #0x100 @ clear bit if set 5401e81bc01SJean Pihet str r5, [r4] @ write back change 5411e81bc01SJean Pihet ldr r4, sdrc_mr_0 @ get config addr 5421e81bc01SJean Pihet ldr r5, [r4] @ get value 5431e81bc01SJean Pihet str r5, [r4] @ write back change 5441e81bc01SJean Pihet ldr r4, sdrc_emr2_0 @ get config addr 5451e81bc01SJean Pihet ldr r5, [r4] @ get value 5461e81bc01SJean Pihet str r5, [r4] @ write back change 5471e81bc01SJean Pihet ldr r4, sdrc_manual_0 @ get config addr 5481e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 5491e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 5501e81bc01SJean Pihet ldr r4, sdrc_mr_1 @ get config addr 5511e81bc01SJean Pihet ldr r5, [r4] @ get value 5521e81bc01SJean Pihet str r5, [r4] @ write back change 5531e81bc01SJean Pihet ldr r4, sdrc_emr2_1 @ get config addr 5541e81bc01SJean Pihet ldr r5, [r4] @ get value 5551e81bc01SJean Pihet str r5, [r4] @ write back change 5561e81bc01SJean Pihet ldr r4, sdrc_manual_1 @ get config addr 5571e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 5581e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 5591e81bc01SJean Pihet bx lr 5601e81bc01SJean Pihet 56146e130d2SJean Pihet/* 56246e130d2SJean Pihet * Local variables 56346e130d2SJean Pihet */ 564dd313947SDave Martin .align 5651e81bc01SJean Pihetsdrc_syscfg: 5661e81bc01SJean Pihet .word SDRC_SYSCONFIG_P 5671e81bc01SJean Pihetsdrc_mr_0: 5681e81bc01SJean Pihet .word SDRC_MR_0_P 5691e81bc01SJean Pihetsdrc_emr2_0: 5701e81bc01SJean Pihet .word SDRC_EMR2_0_P 5711e81bc01SJean Pihetsdrc_manual_0: 5721e81bc01SJean Pihet .word SDRC_MANUAL_0_P 5731e81bc01SJean Pihetsdrc_mr_1: 5741e81bc01SJean Pihet .word SDRC_MR_1_P 5751e81bc01SJean Pihetsdrc_emr2_1: 5761e81bc01SJean Pihet .word SDRC_EMR2_1_P 5771e81bc01SJean Pihetsdrc_manual_1: 5781e81bc01SJean Pihet .word SDRC_MANUAL_1_P 579dd313947SDave MartinENDPROC(es3_sdrc_fix) 5801e81bc01SJean PihetENTRY(es3_sdrc_fix_sz) 5811e81bc01SJean Pihet .word . - es3_sdrc_fix 582