18bd22949SKevin Hilman/* 28bd22949SKevin Hilman * (C) Copyright 2007 38bd22949SKevin Hilman * Texas Instruments 48bd22949SKevin Hilman * Karthik Dasu <karthik-dp@ti.com> 58bd22949SKevin Hilman * 68bd22949SKevin Hilman * (C) Copyright 2004 78bd22949SKevin Hilman * Texas Instruments, <www.ti.com> 88bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 98bd22949SKevin Hilman * 108bd22949SKevin Hilman * This program is free software; you can redistribute it and/or 118bd22949SKevin Hilman * modify it under the terms of the GNU General Public License as 128bd22949SKevin Hilman * published by the Free Software Foundation; either version 2 of 138bd22949SKevin Hilman * the License, or (at your option) any later version. 148bd22949SKevin Hilman * 158bd22949SKevin Hilman * This program is distributed in the hope that it will be useful, 168bd22949SKevin Hilman * but WITHOUT ANY WARRANTY; without even the implied warranty of 178bd22949SKevin Hilman * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 188bd22949SKevin Hilman * GNU General Public License for more details. 198bd22949SKevin Hilman * 208bd22949SKevin Hilman * You should have received a copy of the GNU General Public License 218bd22949SKevin Hilman * along with this program; if not, write to the Free Software 228bd22949SKevin Hilman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 238bd22949SKevin Hilman * MA 02111-1307 USA 248bd22949SKevin Hilman */ 258bd22949SKevin Hilman#include <linux/linkage.h> 268bd22949SKevin Hilman#include <asm/assembler.h> 27b4b36fd9SJean Pihet#include <plat/sram.h> 288bd22949SKevin Hilman#include <mach/io.h> 298bd22949SKevin Hilman 3059fb659bSPaul Walmsley#include "cm2xxx_3xxx.h" 3159fb659bSPaul Walmsley#include "prm2xxx_3xxx.h" 328bd22949SKevin Hilman#include "sdrc.h" 334814ced5SPaul Walmsley#include "control.h" 348bd22949SKevin Hilman 35fe360e1cSJean Pihet/* 36fe360e1cSJean Pihet * Registers access definitions 37fe360e1cSJean Pihet */ 38fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_OFFS 0xc 39fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ 40fe360e1cSJean Pihet (SDRC_SCRATCHPAD_SEM_OFFS) 41fe360e1cSJean Pihet#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ 42fe360e1cSJean Pihet OMAP3430_PM_PREPWSTST 4337903009SAbhijit Pagare#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL 4489139dceSPeter 'p2' De Schrijver#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) 459d93b8a2SPeter 'p2' De Schrijver#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) 46fe360e1cSJean Pihet#define SRAM_BASE_P OMAP3_SRAM_PA 47fe360e1cSJean Pihet#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS 48fe360e1cSJean Pihet#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ 49fe360e1cSJean Pihet OMAP36XX_CONTROL_MEM_RTA_CTRL) 50fe360e1cSJean Pihet 51fe360e1cSJean Pihet/* Move this as correct place is available */ 52fe360e1cSJean Pihet#define SCRATCHPAD_MEM_OFFS 0x310 53fe360e1cSJean Pihet#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ 54fe360e1cSJean Pihet OMAP343X_CONTROL_MEM_WKUP +\ 55fe360e1cSJean Pihet SCRATCHPAD_MEM_OFFS) 568bd22949SKevin Hilman#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 570795a75aSTero Kristo#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) 580795a75aSTero Kristo#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) 590795a75aSTero Kristo#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) 600795a75aSTero Kristo#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) 610795a75aSTero Kristo#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) 620795a75aSTero Kristo#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) 630795a75aSTero Kristo#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) 6489139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 6589139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 668bd22949SKevin Hilman 67a89b6f00SRajendra Nayak 68d3cdfd2aSJean Pihet/* 69d3cdfd2aSJean Pihet * API functions 70d3cdfd2aSJean Pihet */ 71a89b6f00SRajendra Nayak 72f7dfe3d8SJean Pihet/* 73f7dfe3d8SJean Pihet * The "get_*restore_pointer" functions are used to provide a 74f7dfe3d8SJean Pihet * physical restore address where the ROM code jumps while waking 75f7dfe3d8SJean Pihet * up from MPU OFF/OSWR state. 76f7dfe3d8SJean Pihet * The restore pointer is stored into the scratchpad. 77f7dfe3d8SJean Pihet */ 78f7dfe3d8SJean Pihet 79a89b6f00SRajendra Nayak .text 808bd22949SKevin Hilman/* Function call to get the restore pointer for resume from OFF */ 818bd22949SKevin HilmanENTRY(get_restore_pointer) 828bd22949SKevin Hilman stmfd sp!, {lr} @ save registers on stack 838bd22949SKevin Hilman adr r0, restore 848bd22949SKevin Hilman ldmfd sp!, {pc} @ restore regs and return 858bd22949SKevin HilmanENTRY(get_restore_pointer_sz) 860795a75aSTero Kristo .word . - get_restore_pointer 871e81bc01SJean Pihet 88458e999eSNishanth Menon .text 89458e999eSNishanth Menon/* Function call to get the restore pointer for 3630 resume from OFF */ 90458e999eSNishanth MenonENTRY(get_omap3630_restore_pointer) 91458e999eSNishanth Menon stmfd sp!, {lr} @ save registers on stack 92458e999eSNishanth Menon adr r0, restore_3630 93458e999eSNishanth Menon ldmfd sp!, {pc} @ restore regs and return 94458e999eSNishanth MenonENTRY(get_omap3630_restore_pointer_sz) 95458e999eSNishanth Menon .word . - get_omap3630_restore_pointer 960795a75aSTero Kristo 970795a75aSTero Kristo .text 981e81bc01SJean Pihet/* Function call to get the restore pointer for ES3 to resume from OFF */ 991e81bc01SJean PihetENTRY(get_es3_restore_pointer) 1001e81bc01SJean Pihet stmfd sp!, {lr} @ save registers on stack 1011e81bc01SJean Pihet adr r0, restore_es3 1021e81bc01SJean Pihet ldmfd sp!, {pc} @ restore regs and return 1031e81bc01SJean PihetENTRY(get_es3_restore_pointer_sz) 1041e81bc01SJean Pihet .word . - get_es3_restore_pointer 1051e81bc01SJean Pihet 1061e81bc01SJean Pihet .text 107c4236d2eSPeter 'p2' De Schrijver/* 108c4236d2eSPeter 'p2' De Schrijver * L2 cache needs to be toggled for stable OFF mode functionality on 3630. 1091e81bc01SJean Pihet * This function sets up a flag that will allow for this toggling to take 110f7dfe3d8SJean Pihet * place on 3630. Hopefully some version in the future may not need this. 111c4236d2eSPeter 'p2' De Schrijver */ 112c4236d2eSPeter 'p2' De SchrijverENTRY(enable_omap3630_toggle_l2_on_restore) 113c4236d2eSPeter 'p2' De Schrijver stmfd sp!, {lr} @ save registers on stack 114c4236d2eSPeter 'p2' De Schrijver /* Setup so that we will disable and enable l2 */ 115c4236d2eSPeter 'p2' De Schrijver mov r1, #0x1 116c4236d2eSPeter 'p2' De Schrijver str r1, l2dis_3630 117c4236d2eSPeter 'p2' De Schrijver ldmfd sp!, {pc} @ restore regs and return 118c4236d2eSPeter 'p2' De Schrijver 119bb1c9034SJean Pihet .text 12027d59a4aSTero Kristo/* Function to call rom code to save secure ram context */ 12127d59a4aSTero KristoENTRY(save_secure_ram_context) 12227d59a4aSTero Kristo stmfd sp!, {r1-r12, lr} @ save registers on stack 12327d59a4aSTero Kristo adr r3, api_params @ r3 points to parameters 12427d59a4aSTero Kristo str r0, [r3,#0x4] @ r0 has sdram address 12527d59a4aSTero Kristo ldr r12, high_mask 12627d59a4aSTero Kristo and r3, r3, r12 12727d59a4aSTero Kristo ldr r12, sram_phy_addr_mask 12827d59a4aSTero Kristo orr r3, r3, r12 12927d59a4aSTero Kristo mov r0, #25 @ set service ID for PPA 13027d59a4aSTero Kristo mov r12, r0 @ copy secure service ID in r12 13127d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 132ba50ea7eSKalle Jokiniemi mov r2, #4 @ set some flags in r2, r6 13327d59a4aSTero Kristo mov r6, #0xff 13427d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 13527d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 136*76d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 13727d59a4aSTero Kristo nop 13827d59a4aSTero Kristo nop 13927d59a4aSTero Kristo nop 14027d59a4aSTero Kristo nop 14127d59a4aSTero Kristo ldmfd sp!, {r1-r12, pc} 14227d59a4aSTero Kristosram_phy_addr_mask: 14327d59a4aSTero Kristo .word SRAM_BASE_P 14427d59a4aSTero Kristohigh_mask: 14527d59a4aSTero Kristo .word 0xffff 14627d59a4aSTero Kristoapi_params: 14727d59a4aSTero Kristo .word 0x4, 0x0, 0x0, 0x1, 0x1 14827d59a4aSTero KristoENTRY(save_secure_ram_context_sz) 14927d59a4aSTero Kristo .word . - save_secure_ram_context 15027d59a4aSTero Kristo 1518bd22949SKevin Hilman/* 152f7dfe3d8SJean Pihet * ====================== 153f7dfe3d8SJean Pihet * == Idle entry point == 154f7dfe3d8SJean Pihet * ====================== 155f7dfe3d8SJean Pihet */ 156f7dfe3d8SJean Pihet 157f7dfe3d8SJean Pihet/* 1588bd22949SKevin Hilman * Forces OMAP into idle state 1598bd22949SKevin Hilman * 160f7dfe3d8SJean Pihet * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed 161f7dfe3d8SJean Pihet * and executes the WFI instruction. Calling WFI effectively changes the 162f7dfe3d8SJean Pihet * power domains states to the desired target power states. 1638bd22949SKevin Hilman * 164f7dfe3d8SJean Pihet * 165f7dfe3d8SJean Pihet * Notes: 166bb1c9034SJean Pihet * - this code gets copied to internal SRAM at boot and after wake-up 167bb1c9034SJean Pihet * from OFF mode. The execution pointer in SRAM is _omap_sram_idle. 168f7dfe3d8SJean Pihet * - when the OMAP wakes up it continues at different execution points 169f7dfe3d8SJean Pihet * depending on the low power mode (non-OFF vs OFF modes), 170f7dfe3d8SJean Pihet * cf. 'Resume path for xxx mode' comments. 1718bd22949SKevin Hilman */ 1728bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend) 1738bd22949SKevin Hilman stmfd sp!, {r0-r12, lr} @ save registers on stack 174d3cdfd2aSJean Pihet 175f7dfe3d8SJean Pihet /* 176f7dfe3d8SJean Pihet * r0 contains restore pointer in sdram 177f7dfe3d8SJean Pihet * r1 contains information about saving context: 178f7dfe3d8SJean Pihet * 0 - No context lost 179f7dfe3d8SJean Pihet * 1 - Only L1 and logic lost 180f7dfe3d8SJean Pihet * 2 - Only L2 lost 181f7dfe3d8SJean Pihet * 3 - Both L1 and L2 lost 182f7dfe3d8SJean Pihet */ 183f7dfe3d8SJean Pihet 184f7dfe3d8SJean Pihet /* Directly jump to WFI is the context save is not required */ 185f7dfe3d8SJean Pihet cmp r1, #0x0 186f7dfe3d8SJean Pihet beq omap3_do_wfi 187f7dfe3d8SJean Pihet 188f7dfe3d8SJean Pihet /* Otherwise fall through to the save context code */ 189f7dfe3d8SJean Pihetsave_context_wfi: 190f7dfe3d8SJean Pihet mov r8, r0 @ Store SDRAM address in r8 191f7dfe3d8SJean Pihet mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register 192f7dfe3d8SJean Pihet mov r4, #0x1 @ Number of parameters for restore call 193f7dfe3d8SJean Pihet stmia r8!, {r4-r5} @ Push parameters for restore call 194f7dfe3d8SJean Pihet mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register 195f7dfe3d8SJean Pihet stmia r8!, {r4-r5} @ Push parameters for restore call 196f7dfe3d8SJean Pihet 197f7dfe3d8SJean Pihet /* Check what that target sleep state is from r1 */ 198f7dfe3d8SJean Pihet cmp r1, #0x2 @ Only L2 lost, no need to save context 199f7dfe3d8SJean Pihet beq clean_caches 200f7dfe3d8SJean Pihet 201f7dfe3d8SJean Pihetl1_logic_lost: 202f7dfe3d8SJean Pihet /* Store sp and spsr to SDRAM */ 203f7dfe3d8SJean Pihet mov r4, sp 204f7dfe3d8SJean Pihet mrs r5, spsr 205f7dfe3d8SJean Pihet mov r6, lr 206f7dfe3d8SJean Pihet stmia r8!, {r4-r6} 207f7dfe3d8SJean Pihet /* Save all ARM registers */ 208f7dfe3d8SJean Pihet /* Coprocessor access control register */ 209f7dfe3d8SJean Pihet mrc p15, 0, r6, c1, c0, 2 210f7dfe3d8SJean Pihet stmia r8!, {r6} 211f7dfe3d8SJean Pihet /* TTBR0, TTBR1 and Translation table base control */ 212f7dfe3d8SJean Pihet mrc p15, 0, r4, c2, c0, 0 213f7dfe3d8SJean Pihet mrc p15, 0, r5, c2, c0, 1 214f7dfe3d8SJean Pihet mrc p15, 0, r6, c2, c0, 2 215f7dfe3d8SJean Pihet stmia r8!, {r4-r6} 216f7dfe3d8SJean Pihet /* 217f7dfe3d8SJean Pihet * Domain access control register, data fault status register, 218f7dfe3d8SJean Pihet * and instruction fault status register 219f7dfe3d8SJean Pihet */ 220f7dfe3d8SJean Pihet mrc p15, 0, r4, c3, c0, 0 221f7dfe3d8SJean Pihet mrc p15, 0, r5, c5, c0, 0 222f7dfe3d8SJean Pihet mrc p15, 0, r6, c5, c0, 1 223f7dfe3d8SJean Pihet stmia r8!, {r4-r6} 224f7dfe3d8SJean Pihet /* 225f7dfe3d8SJean Pihet * Data aux fault status register, instruction aux fault status, 226f7dfe3d8SJean Pihet * data fault address register and instruction fault address register 227f7dfe3d8SJean Pihet */ 228f7dfe3d8SJean Pihet mrc p15, 0, r4, c5, c1, 0 229f7dfe3d8SJean Pihet mrc p15, 0, r5, c5, c1, 1 230f7dfe3d8SJean Pihet mrc p15, 0, r6, c6, c0, 0 231f7dfe3d8SJean Pihet mrc p15, 0, r7, c6, c0, 2 232f7dfe3d8SJean Pihet stmia r8!, {r4-r7} 233f7dfe3d8SJean Pihet /* 234f7dfe3d8SJean Pihet * user r/w thread and process ID, user r/o thread and process ID, 235f7dfe3d8SJean Pihet * priv only thread and process ID, cache size selection 236f7dfe3d8SJean Pihet */ 237f7dfe3d8SJean Pihet mrc p15, 0, r4, c13, c0, 2 238f7dfe3d8SJean Pihet mrc p15, 0, r5, c13, c0, 3 239f7dfe3d8SJean Pihet mrc p15, 0, r6, c13, c0, 4 240f7dfe3d8SJean Pihet mrc p15, 2, r7, c0, c0, 0 241f7dfe3d8SJean Pihet stmia r8!, {r4-r7} 242f7dfe3d8SJean Pihet /* Data TLB lockdown, instruction TLB lockdown registers */ 243f7dfe3d8SJean Pihet mrc p15, 0, r5, c10, c0, 0 244f7dfe3d8SJean Pihet mrc p15, 0, r6, c10, c0, 1 245f7dfe3d8SJean Pihet stmia r8!, {r5-r6} 246f7dfe3d8SJean Pihet /* Secure or non secure vector base address, FCSE PID, Context PID*/ 247f7dfe3d8SJean Pihet mrc p15, 0, r4, c12, c0, 0 248f7dfe3d8SJean Pihet mrc p15, 0, r5, c13, c0, 0 249f7dfe3d8SJean Pihet mrc p15, 0, r6, c13, c0, 1 250f7dfe3d8SJean Pihet stmia r8!, {r4-r6} 251f7dfe3d8SJean Pihet /* Primary remap, normal remap registers */ 252f7dfe3d8SJean Pihet mrc p15, 0, r4, c10, c2, 0 253f7dfe3d8SJean Pihet mrc p15, 0, r5, c10, c2, 1 254f7dfe3d8SJean Pihet stmia r8!,{r4-r5} 255f7dfe3d8SJean Pihet 256f7dfe3d8SJean Pihet /* Store current cpsr*/ 257f7dfe3d8SJean Pihet mrs r2, cpsr 258f7dfe3d8SJean Pihet stmia r8!, {r2} 259f7dfe3d8SJean Pihet 260f7dfe3d8SJean Pihet mrc p15, 0, r4, c1, c0, 0 261f7dfe3d8SJean Pihet /* save control register */ 262f7dfe3d8SJean Pihet stmia r8!, {r4} 263f7dfe3d8SJean Pihet 264f7dfe3d8SJean Pihetclean_caches: 265f7dfe3d8SJean Pihet /* 266f7dfe3d8SJean Pihet * Clean Data or unified cache to POU 267f7dfe3d8SJean Pihet * How to invalidate only L1 cache???? - #FIX_ME# 268f7dfe3d8SJean Pihet * mcr p15, 0, r11, c7, c11, 1 269f7dfe3d8SJean Pihet */ 270f7dfe3d8SJean Pihet cmp r1, #0x1 @ Check whether L2 inval is required 271f7dfe3d8SJean Pihet beq omap3_do_wfi 272f7dfe3d8SJean Pihet 273f7dfe3d8SJean Pihetclean_l2: 274f7dfe3d8SJean Pihet /* 275f7dfe3d8SJean Pihet * jump out to kernel flush routine 276f7dfe3d8SJean Pihet * - reuse that code is better 277f7dfe3d8SJean Pihet * - it executes in a cached space so is faster than refetch per-block 278f7dfe3d8SJean Pihet * - should be faster and will change with kernel 279f7dfe3d8SJean Pihet * - 'might' have to copy address, load and jump to it 280f7dfe3d8SJean Pihet */ 281f7dfe3d8SJean Pihet ldr r1, kernel_flush 282f7dfe3d8SJean Pihet mov lr, pc 283f7dfe3d8SJean Pihet bx r1 284f7dfe3d8SJean Pihet 285f7dfe3d8SJean Pihetomap3_do_wfi: 2868bd22949SKevin Hilman ldr r4, sdrc_power @ read the SDRC_POWER register 2878bd22949SKevin Hilman ldr r5, [r4] @ read the contents of SDRC_POWER 2888bd22949SKevin Hilman orr r5, r5, #0x40 @ enable self refresh on idle req 2898bd22949SKevin Hilman str r5, [r4] @ write back to SDRC_POWER register 2908bd22949SKevin Hilman 2918bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 2928bd22949SKevin Hilman mov r1, #0 2938bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 4 2948bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 5 2958bd22949SKevin Hilman 296f7dfe3d8SJean Pihet/* 297f7dfe3d8SJean Pihet * =================================== 298f7dfe3d8SJean Pihet * == WFI instruction => Enter idle == 299f7dfe3d8SJean Pihet * =================================== 300f7dfe3d8SJean Pihet */ 3018bd22949SKevin Hilman wfi @ wait for interrupt 3028bd22949SKevin Hilman 303f7dfe3d8SJean Pihet/* 304f7dfe3d8SJean Pihet * =================================== 305f7dfe3d8SJean Pihet * == Resume path for non-OFF modes == 306f7dfe3d8SJean Pihet * =================================== 307f7dfe3d8SJean Pihet */ 3088bd22949SKevin Hilman nop 3098bd22949SKevin Hilman nop 3108bd22949SKevin Hilman nop 3118bd22949SKevin Hilman nop 3128bd22949SKevin Hilman nop 3138bd22949SKevin Hilman nop 3148bd22949SKevin Hilman nop 3158bd22949SKevin Hilman nop 3168bd22949SKevin Hilman nop 3178bd22949SKevin Hilman nop 31889139dceSPeter 'p2' De Schrijver bl wait_sdrc_ok 3198bd22949SKevin Hilman 320f7dfe3d8SJean Pihet/* 321f7dfe3d8SJean Pihet * =================================== 322f7dfe3d8SJean Pihet * == Exit point from non-OFF modes == 323f7dfe3d8SJean Pihet * =================================== 324f7dfe3d8SJean Pihet */ 3258bd22949SKevin Hilman ldmfd sp!, {r0-r12, pc} @ restore regs and return 326f7dfe3d8SJean Pihet 327f7dfe3d8SJean Pihet 328f7dfe3d8SJean Pihet/* 329f7dfe3d8SJean Pihet * ============================== 330f7dfe3d8SJean Pihet * == Resume path for OFF mode == 331f7dfe3d8SJean Pihet * ============================== 332f7dfe3d8SJean Pihet */ 333f7dfe3d8SJean Pihet 334f7dfe3d8SJean Pihet/* 335f7dfe3d8SJean Pihet * The restore_* functions are called by the ROM code 336f7dfe3d8SJean Pihet * when back from WFI in OFF mode. 337f7dfe3d8SJean Pihet * Cf. the get_*restore_pointer functions. 338f7dfe3d8SJean Pihet * 339f7dfe3d8SJean Pihet * restore_es3: applies to 34xx >= ES3.0 340f7dfe3d8SJean Pihet * restore_3630: applies to 36xx 341f7dfe3d8SJean Pihet * restore: common code for 3xxx 342f7dfe3d8SJean Pihet */ 3430795a75aSTero Kristorestore_es3: 3440795a75aSTero Kristo ldr r5, pm_prepwstst_core_p 3450795a75aSTero Kristo ldr r4, [r5] 3460795a75aSTero Kristo and r4, r4, #0x3 3470795a75aSTero Kristo cmp r4, #0x0 @ Check if previous power state of CORE is OFF 3480795a75aSTero Kristo bne restore 3490795a75aSTero Kristo adr r0, es3_sdrc_fix 3500795a75aSTero Kristo ldr r1, sram_base 3510795a75aSTero Kristo ldr r2, es3_sdrc_fix_sz 3520795a75aSTero Kristo mov r2, r2, ror #2 3530795a75aSTero Kristocopy_to_sram: 3540795a75aSTero Kristo ldmia r0!, {r3} @ val = *src 3550795a75aSTero Kristo stmia r1!, {r3} @ *dst = val 3560795a75aSTero Kristo subs r2, r2, #0x1 @ num_words-- 3570795a75aSTero Kristo bne copy_to_sram 3580795a75aSTero Kristo ldr r1, sram_base 3590795a75aSTero Kristo blx r1 360458e999eSNishanth Menon b restore 361458e999eSNishanth Menon 362458e999eSNishanth Menonrestore_3630: 363458e999eSNishanth Menon ldr r1, pm_prepwstst_core_p 364458e999eSNishanth Menon ldr r2, [r1] 365458e999eSNishanth Menon and r2, r2, #0x3 366458e999eSNishanth Menon cmp r2, #0x0 @ Check if previous power state of CORE is OFF 367458e999eSNishanth Menon bne restore 368458e999eSNishanth Menon /* Disable RTA before giving control */ 369458e999eSNishanth Menon ldr r1, control_mem_rta 370458e999eSNishanth Menon mov r2, #OMAP36XX_RTA_DISABLE 371458e999eSNishanth Menon str r2, [r1] 372f7dfe3d8SJean Pihet 373f7dfe3d8SJean Pihet /* Fall through to common code for the remaining logic */ 374f7dfe3d8SJean Pihet 3758bd22949SKevin Hilmanrestore: 376f7dfe3d8SJean Pihet /* 377f7dfe3d8SJean Pihet * Check what was the reason for mpu reset and store the reason in r9: 378f7dfe3d8SJean Pihet * 0 - No context lost 379f7dfe3d8SJean Pihet * 1 - Only L1 and logic lost 380f7dfe3d8SJean Pihet * 2 - Only L2 lost - In this case, we wont be here 381f7dfe3d8SJean Pihet * 3 - Both L1 and L2 lost 382f7dfe3d8SJean Pihet */ 3838bd22949SKevin Hilman ldr r1, pm_pwstctrl_mpu 3848bd22949SKevin Hilman ldr r2, [r1] 3858bd22949SKevin Hilman and r2, r2, #0x3 3868bd22949SKevin Hilman cmp r2, #0x0 @ Check if target power state was OFF or RET 3878bd22949SKevin Hilman moveq r9, #0x3 @ MPU OFF => L1 and L2 lost 3888bd22949SKevin Hilman movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation 3898bd22949SKevin Hilman bne logic_l1_restore 390c4236d2eSPeter 'p2' De Schrijver 391c4236d2eSPeter 'p2' De Schrijver ldr r0, l2dis_3630 392c4236d2eSPeter 'p2' De Schrijver cmp r0, #0x1 @ should we disable L2 on 3630? 393c4236d2eSPeter 'p2' De Schrijver bne skipl2dis 394c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r0, c1, c0, 1 395c4236d2eSPeter 'p2' De Schrijver bic r0, r0, #2 @ disable L2 cache 396c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r0, c1, c0, 1 397c4236d2eSPeter 'p2' De Schrijverskipl2dis: 39827d59a4aSTero Kristo ldr r0, control_stat 39927d59a4aSTero Kristo ldr r1, [r0] 40027d59a4aSTero Kristo and r1, #0x700 40127d59a4aSTero Kristo cmp r1, #0x300 40227d59a4aSTero Kristo beq l2_inv_gp 40327d59a4aSTero Kristo mov r0, #40 @ set service ID for PPA 40427d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 40527d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 40627d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 40727d59a4aSTero Kristo mov r6, #0xff 40827d59a4aSTero Kristo adr r3, l2_inv_api_params @ r3 points to dummy parameters 40927d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 41027d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 411*76d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 41227d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 41327d59a4aSTero Kristo mov r0, #42 @ set service ID for PPA 41427d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 41527d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 41627d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 41727d59a4aSTero Kristo mov r6, #0xff 418a087cad9STero Kristo ldr r4, scratchpad_base 419a087cad9STero Kristo ldr r3, [r4, #0xBC] @ r3 points to parameters 42027d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 42127d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 422*76d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 42327d59a4aSTero Kristo 42479dcfdd4STero Kristo#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 42579dcfdd4STero Kristo /* Restore L2 aux control register */ 42679dcfdd4STero Kristo @ set service ID for PPA 42779dcfdd4STero Kristo mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 42879dcfdd4STero Kristo mov r12, r0 @ copy service ID in r12 42979dcfdd4STero Kristo mov r1, #0 @ set task ID for ROM code in r1 43079dcfdd4STero Kristo mov r2, #4 @ set some flags in r2, r6 43179dcfdd4STero Kristo mov r6, #0xff 43279dcfdd4STero Kristo ldr r4, scratchpad_base 43379dcfdd4STero Kristo ldr r3, [r4, #0xBC] 43479dcfdd4STero Kristo adds r3, r3, #8 @ r3 points to parameters 43579dcfdd4STero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 43679dcfdd4STero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 437*76d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 43879dcfdd4STero Kristo#endif 43927d59a4aSTero Kristo b logic_l1_restore 440bb1c9034SJean Pihet 44127d59a4aSTero Kristol2_inv_api_params: 44227d59a4aSTero Kristo .word 0x1, 0x00 44327d59a4aSTero Kristol2_inv_gp: 4448bd22949SKevin Hilman /* Execute smi to invalidate L2 cache */ 445bb1c9034SJean Pihet mov r12, #0x1 @ set up to invalidate L2 446*76d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 44727d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 448a087cad9STero Kristo ldr r4, scratchpad_base 449a087cad9STero Kristo ldr r3, [r4,#0xBC] 450a087cad9STero Kristo ldr r0, [r3,#4] 45127d59a4aSTero Kristo mov r12, #0x3 452*76d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 45379dcfdd4STero Kristo ldr r4, scratchpad_base 45479dcfdd4STero Kristo ldr r3, [r4,#0xBC] 45579dcfdd4STero Kristo ldr r0, [r3,#12] 45679dcfdd4STero Kristo mov r12, #0x2 457*76d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 4588bd22949SKevin Hilmanlogic_l1_restore: 459c4236d2eSPeter 'p2' De Schrijver ldr r1, l2dis_3630 460bb1c9034SJean Pihet cmp r1, #0x1 @ Test if L2 re-enable needed on 3630 461c4236d2eSPeter 'p2' De Schrijver bne skipl2reen 462c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r1, c1, c0, 1 463c4236d2eSPeter 'p2' De Schrijver orr r1, r1, #2 @ re-enable L2 cache 464c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r1, c1, c0, 1 465c4236d2eSPeter 'p2' De Schrijverskipl2reen: 4668bd22949SKevin Hilman mov r1, #0 467bb1c9034SJean Pihet /* 468bb1c9034SJean Pihet * Invalidate all instruction caches to PoU 469bb1c9034SJean Pihet * and flush branch target cache 470bb1c9034SJean Pihet */ 4718bd22949SKevin Hilman mcr p15, 0, r1, c7, c5, 0 4728bd22949SKevin Hilman 4738bd22949SKevin Hilman ldr r4, scratchpad_base 4748bd22949SKevin Hilman ldr r3, [r4,#0xBC] 47579dcfdd4STero Kristo adds r3, r3, #16 4768bd22949SKevin Hilman ldmia r3!, {r4-r6} 4778bd22949SKevin Hilman mov sp, r4 4788bd22949SKevin Hilman msr spsr_cxsf, r5 4798bd22949SKevin Hilman mov lr, r6 4808bd22949SKevin Hilman 4818bd22949SKevin Hilman ldmia r3!, {r4-r9} 4828bd22949SKevin Hilman /* Coprocessor access Control Register */ 4838bd22949SKevin Hilman mcr p15, 0, r4, c1, c0, 2 4848bd22949SKevin Hilman 4858bd22949SKevin Hilman /* TTBR0 */ 4868bd22949SKevin Hilman MCR p15, 0, r5, c2, c0, 0 4878bd22949SKevin Hilman /* TTBR1 */ 4888bd22949SKevin Hilman MCR p15, 0, r6, c2, c0, 1 4898bd22949SKevin Hilman /* Translation table base control register */ 4908bd22949SKevin Hilman MCR p15, 0, r7, c2, c0, 2 491bb1c9034SJean Pihet /* Domain access Control Register */ 4928bd22949SKevin Hilman MCR p15, 0, r8, c3, c0, 0 493bb1c9034SJean Pihet /* Data fault status Register */ 4948bd22949SKevin Hilman MCR p15, 0, r9, c5, c0, 0 4958bd22949SKevin Hilman 4968bd22949SKevin Hilman ldmia r3!,{r4-r8} 497bb1c9034SJean Pihet /* Instruction fault status Register */ 4988bd22949SKevin Hilman MCR p15, 0, r4, c5, c0, 1 4998bd22949SKevin Hilman /* Data Auxiliary Fault Status Register */ 5008bd22949SKevin Hilman MCR p15, 0, r5, c5, c1, 0 5018bd22949SKevin Hilman /* Instruction Auxiliary Fault Status Register*/ 5028bd22949SKevin Hilman MCR p15, 0, r6, c5, c1, 1 5038bd22949SKevin Hilman /* Data Fault Address Register */ 5048bd22949SKevin Hilman MCR p15, 0, r7, c6, c0, 0 5058bd22949SKevin Hilman /* Instruction Fault Address Register*/ 5068bd22949SKevin Hilman MCR p15, 0, r8, c6, c0, 2 5078bd22949SKevin Hilman ldmia r3!,{r4-r7} 5088bd22949SKevin Hilman 509bb1c9034SJean Pihet /* User r/w thread and process ID */ 5108bd22949SKevin Hilman MCR p15, 0, r4, c13, c0, 2 511bb1c9034SJean Pihet /* User ro thread and process ID */ 5128bd22949SKevin Hilman MCR p15, 0, r5, c13, c0, 3 5138bd22949SKevin Hilman /* Privileged only thread and process ID */ 5148bd22949SKevin Hilman MCR p15, 0, r6, c13, c0, 4 515bb1c9034SJean Pihet /* Cache size selection */ 5168bd22949SKevin Hilman MCR p15, 2, r7, c0, c0, 0 5178bd22949SKevin Hilman ldmia r3!,{r4-r8} 5188bd22949SKevin Hilman /* Data TLB lockdown registers */ 5198bd22949SKevin Hilman MCR p15, 0, r4, c10, c0, 0 5208bd22949SKevin Hilman /* Instruction TLB lockdown registers */ 5218bd22949SKevin Hilman MCR p15, 0, r5, c10, c0, 1 5228bd22949SKevin Hilman /* Secure or Nonsecure Vector Base Address */ 5238bd22949SKevin Hilman MCR p15, 0, r6, c12, c0, 0 5248bd22949SKevin Hilman /* FCSE PID */ 5258bd22949SKevin Hilman MCR p15, 0, r7, c13, c0, 0 5268bd22949SKevin Hilman /* Context PID */ 5278bd22949SKevin Hilman MCR p15, 0, r8, c13, c0, 1 5288bd22949SKevin Hilman 5298bd22949SKevin Hilman ldmia r3!,{r4-r5} 530bb1c9034SJean Pihet /* Primary memory remap register */ 5318bd22949SKevin Hilman MCR p15, 0, r4, c10, c2, 0 532bb1c9034SJean Pihet /* Normal memory remap register */ 5338bd22949SKevin Hilman MCR p15, 0, r5, c10, c2, 1 5348bd22949SKevin Hilman 5358bd22949SKevin Hilman /* Restore cpsr */ 536bb1c9034SJean Pihet ldmia r3!,{r4} @ load CPSR from SDRAM 537bb1c9034SJean Pihet msr cpsr, r4 @ store cpsr 5388bd22949SKevin Hilman 5398bd22949SKevin Hilman /* Enabling MMU here */ 540bb1c9034SJean Pihet mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl 5418bd22949SKevin Hilman /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */ 5428bd22949SKevin Hilman and r7, #0x7 5438bd22949SKevin Hilman cmp r7, #0x0 5448bd22949SKevin Hilman beq usettbr0 5458bd22949SKevin Hilmanttbr_error: 546bb1c9034SJean Pihet /* 547bb1c9034SJean Pihet * More work needs to be done to support N[0:2] value other than 0 5488bd22949SKevin Hilman * So looping here so that the error can be detected 5498bd22949SKevin Hilman */ 5508bd22949SKevin Hilman b ttbr_error 5518bd22949SKevin Hilmanusettbr0: 5528bd22949SKevin Hilman mrc p15, 0, r2, c2, c0, 0 5538bd22949SKevin Hilman ldr r5, ttbrbit_mask 5548bd22949SKevin Hilman and r2, r5 5558bd22949SKevin Hilman mov r4, pc 5568bd22949SKevin Hilman ldr r5, table_index_mask 557bb1c9034SJean Pihet and r4, r5 @ r4 = 31 to 20 bits of pc 5588bd22949SKevin Hilman /* Extract the value to be written to table entry */ 5598bd22949SKevin Hilman ldr r1, table_entry 560bb1c9034SJean Pihet /* r1 has the value to be written to table entry*/ 561bb1c9034SJean Pihet add r1, r1, r4 5628bd22949SKevin Hilman /* Getting the address of table entry to modify */ 5638bd22949SKevin Hilman lsr r4, #18 564bb1c9034SJean Pihet /* r2 has the location which needs to be modified */ 565bb1c9034SJean Pihet add r2, r4 5668bd22949SKevin Hilman /* Storing previous entry of location being modified */ 5678bd22949SKevin Hilman ldr r5, scratchpad_base 5688bd22949SKevin Hilman ldr r4, [r2] 5698bd22949SKevin Hilman str r4, [r5, #0xC0] 5708bd22949SKevin Hilman /* Modify the table entry */ 5718bd22949SKevin Hilman str r1, [r2] 572bb1c9034SJean Pihet /* 573bb1c9034SJean Pihet * Storing address of entry being modified 574bb1c9034SJean Pihet * - will be restored after enabling MMU 575bb1c9034SJean Pihet */ 5768bd22949SKevin Hilman ldr r5, scratchpad_base 5778bd22949SKevin Hilman str r2, [r5, #0xC4] 5788bd22949SKevin Hilman 5798bd22949SKevin Hilman mov r0, #0 5808bd22949SKevin Hilman mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer 5818bd22949SKevin Hilman mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array 5828bd22949SKevin Hilman mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB 5838bd22949SKevin Hilman mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB 584bb1c9034SJean Pihet /* 585bb1c9034SJean Pihet * Restore control register. This enables the MMU. 586bb1c9034SJean Pihet * The caches and prediction are not enabled here, they 587bb1c9034SJean Pihet * will be enabled after restoring the MMU table entry. 588bb1c9034SJean Pihet */ 5898bd22949SKevin Hilman ldmia r3!, {r4} 5908bd22949SKevin Hilman /* Store previous value of control register in scratchpad */ 5918bd22949SKevin Hilman str r4, [r5, #0xC8] 5928bd22949SKevin Hilman ldr r2, cache_pred_disable_mask 5938bd22949SKevin Hilman and r4, r2 5948bd22949SKevin Hilman mcr p15, 0, r4, c1, c0, 0 5958bd22949SKevin Hilman 5960bd40535SRichard Woodruff/* 597f7dfe3d8SJean Pihet * ============================== 598f7dfe3d8SJean Pihet * == Exit point from OFF mode == 599f7dfe3d8SJean Pihet * ============================== 6000bd40535SRichard Woodruff */ 601f7dfe3d8SJean Pihet ldmfd sp!, {r0-r12, pc} @ restore regs and return 6028bd22949SKevin Hilman 6031e81bc01SJean Pihet 6041e81bc01SJean Pihet/* 6051e81bc01SJean Pihet * Internal functions 6061e81bc01SJean Pihet */ 6071e81bc01SJean Pihet 60883521291SJean Pihet/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */ 6091e81bc01SJean Pihet .text 6101e81bc01SJean PihetENTRY(es3_sdrc_fix) 6111e81bc01SJean Pihet ldr r4, sdrc_syscfg @ get config addr 6121e81bc01SJean Pihet ldr r5, [r4] @ get value 6131e81bc01SJean Pihet tst r5, #0x100 @ is part access blocked 6141e81bc01SJean Pihet it eq 6151e81bc01SJean Pihet biceq r5, r5, #0x100 @ clear bit if set 6161e81bc01SJean Pihet str r5, [r4] @ write back change 6171e81bc01SJean Pihet ldr r4, sdrc_mr_0 @ get config addr 6181e81bc01SJean Pihet ldr r5, [r4] @ get value 6191e81bc01SJean Pihet str r5, [r4] @ write back change 6201e81bc01SJean Pihet ldr r4, sdrc_emr2_0 @ get config addr 6211e81bc01SJean Pihet ldr r5, [r4] @ get value 6221e81bc01SJean Pihet str r5, [r4] @ write back change 6231e81bc01SJean Pihet ldr r4, sdrc_manual_0 @ get config addr 6241e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 6251e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 6261e81bc01SJean Pihet ldr r4, sdrc_mr_1 @ get config addr 6271e81bc01SJean Pihet ldr r5, [r4] @ get value 6281e81bc01SJean Pihet str r5, [r4] @ write back change 6291e81bc01SJean Pihet ldr r4, sdrc_emr2_1 @ get config addr 6301e81bc01SJean Pihet ldr r5, [r4] @ get value 6311e81bc01SJean Pihet str r5, [r4] @ write back change 6321e81bc01SJean Pihet ldr r4, sdrc_manual_1 @ get config addr 6331e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 6341e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 6351e81bc01SJean Pihet bx lr 6361e81bc01SJean Pihet 6371e81bc01SJean Pihetsdrc_syscfg: 6381e81bc01SJean Pihet .word SDRC_SYSCONFIG_P 6391e81bc01SJean Pihetsdrc_mr_0: 6401e81bc01SJean Pihet .word SDRC_MR_0_P 6411e81bc01SJean Pihetsdrc_emr2_0: 6421e81bc01SJean Pihet .word SDRC_EMR2_0_P 6431e81bc01SJean Pihetsdrc_manual_0: 6441e81bc01SJean Pihet .word SDRC_MANUAL_0_P 6451e81bc01SJean Pihetsdrc_mr_1: 6461e81bc01SJean Pihet .word SDRC_MR_1_P 6471e81bc01SJean Pihetsdrc_emr2_1: 6481e81bc01SJean Pihet .word SDRC_EMR2_1_P 6491e81bc01SJean Pihetsdrc_manual_1: 6501e81bc01SJean Pihet .word SDRC_MANUAL_1_P 6511e81bc01SJean PihetENTRY(es3_sdrc_fix_sz) 6521e81bc01SJean Pihet .word . - es3_sdrc_fix 6531e81bc01SJean Pihet 65483521291SJean Pihet/* 65583521291SJean Pihet * This function implements the erratum ID i581 WA: 65683521291SJean Pihet * SDRC state restore before accessing the SDRAM 65783521291SJean Pihet * 65883521291SJean Pihet * Only used at return from non-OFF mode. For OFF 65983521291SJean Pihet * mode the ROM code configures the SDRC and 66083521291SJean Pihet * the DPLL before calling the restore code directly 66183521291SJean Pihet * from DDR. 66283521291SJean Pihet */ 66383521291SJean Pihet 66489139dceSPeter 'p2' De Schrijver/* Make sure SDRC accesses are ok */ 66589139dceSPeter 'p2' De Schrijverwait_sdrc_ok: 6669d93b8a2SPeter 'p2' De Schrijver 667bb1c9034SJean Pihet/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */ 6689d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest_ckgen 6699d93b8a2SPeter 'p2' De Schrijverwait_dpll3_lock: 67089139dceSPeter 'p2' De Schrijver ldr r5, [r4] 6719d93b8a2SPeter 'p2' De Schrijver tst r5, #1 6729d93b8a2SPeter 'p2' De Schrijver beq wait_dpll3_lock 6739d93b8a2SPeter 'p2' De Schrijver 6749d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest1_core 6759d93b8a2SPeter 'p2' De Schrijverwait_sdrc_ready: 6769d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 6779d93b8a2SPeter 'p2' De Schrijver tst r5, #0x2 6789d93b8a2SPeter 'p2' De Schrijver bne wait_sdrc_ready 6799d93b8a2SPeter 'p2' De Schrijver /* allow DLL powerdown upon hw idle req */ 6808bd22949SKevin Hilman ldr r4, sdrc_power 6818bd22949SKevin Hilman ldr r5, [r4] 6828bd22949SKevin Hilman bic r5, r5, #0x40 6838bd22949SKevin Hilman str r5, [r4] 6849d93b8a2SPeter 'p2' De Schrijver 685bb1c9034SJean Pihetis_dll_in_lock_mode: 68689139dceSPeter 'p2' De Schrijver /* Is dll in lock mode? */ 68789139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 68889139dceSPeter 'p2' De Schrijver ldr r5, [r4] 68989139dceSPeter 'p2' De Schrijver tst r5, #0x4 690bb1c9034SJean Pihet bxne lr @ Return if locked 69189139dceSPeter 'p2' De Schrijver /* wait till dll locks */ 6929d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_timed: 6939d93b8a2SPeter 'p2' De Schrijver ldr r4, wait_dll_lock_counter 6949d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 6959d93b8a2SPeter 'p2' De Schrijver str r4, wait_dll_lock_counter 69689139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_status 697bb1c9034SJean Pihet /* Wait 20uS for lock */ 698bb1c9034SJean Pihet mov r6, #8 6999d93b8a2SPeter 'p2' De Schrijverwait_dll_lock: 7009d93b8a2SPeter 'p2' De Schrijver subs r6, r6, #0x1 7019d93b8a2SPeter 'p2' De Schrijver beq kick_dll 70289139dceSPeter 'p2' De Schrijver ldr r5, [r4] 70389139dceSPeter 'p2' De Schrijver and r5, r5, #0x4 70489139dceSPeter 'p2' De Schrijver cmp r5, #0x4 70589139dceSPeter 'p2' De Schrijver bne wait_dll_lock 706bb1c9034SJean Pihet bx lr @ Return when locked 70789139dceSPeter 'p2' De Schrijver 7089d93b8a2SPeter 'p2' De Schrijver /* disable/reenable DLL if not locked */ 7099d93b8a2SPeter 'p2' De Schrijverkick_dll: 7109d93b8a2SPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 7119d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 7129d93b8a2SPeter 'p2' De Schrijver mov r6, r5 713bb1c9034SJean Pihet bic r6, #(1<<3) @ disable dll 7149d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 7159d93b8a2SPeter 'p2' De Schrijver dsb 716bb1c9034SJean Pihet orr r6, r6, #(1<<3) @ enable dll 7179d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 7189d93b8a2SPeter 'p2' De Schrijver dsb 7199d93b8a2SPeter 'p2' De Schrijver ldr r4, kick_counter 7209d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 7219d93b8a2SPeter 'p2' De Schrijver str r4, kick_counter 7229d93b8a2SPeter 'p2' De Schrijver b wait_dll_lock_timed 7239d93b8a2SPeter 'p2' De Schrijver 72489139dceSPeter 'p2' De Schrijvercm_idlest1_core: 72589139dceSPeter 'p2' De Schrijver .word CM_IDLEST1_CORE_V 7269d93b8a2SPeter 'p2' De Schrijvercm_idlest_ckgen: 7279d93b8a2SPeter 'p2' De Schrijver .word CM_IDLEST_CKGEN_V 72889139dceSPeter 'p2' De Schrijversdrc_dlla_status: 72989139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_STATUS_V 73089139dceSPeter 'p2' De Schrijversdrc_dlla_ctrl: 73189139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_CTRL_V 7320795a75aSTero Kristopm_prepwstst_core_p: 7330795a75aSTero Kristo .word PM_PREPWSTST_CORE_P 7348bd22949SKevin Hilmanpm_pwstctrl_mpu: 7358bd22949SKevin Hilman .word PM_PWSTCTRL_MPU_P 7368bd22949SKevin Hilmanscratchpad_base: 7378bd22949SKevin Hilman .word SCRATCHPAD_BASE_P 7380795a75aSTero Kristosram_base: 7390795a75aSTero Kristo .word SRAM_BASE_P + 0x8000 7408bd22949SKevin Hilmansdrc_power: 7418bd22949SKevin Hilman .word SDRC_POWER_V 7428bd22949SKevin Hilmanttbrbit_mask: 7438bd22949SKevin Hilman .word 0xFFFFC000 7448bd22949SKevin Hilmantable_index_mask: 7458bd22949SKevin Hilman .word 0xFFF00000 7468bd22949SKevin Hilmantable_entry: 7478bd22949SKevin Hilman .word 0x00000C02 7488bd22949SKevin Hilmancache_pred_disable_mask: 7498bd22949SKevin Hilman .word 0xFFFFE7FB 75027d59a4aSTero Kristocontrol_stat: 75127d59a4aSTero Kristo .word CONTROL_STAT 752458e999eSNishanth Menoncontrol_mem_rta: 753458e999eSNishanth Menon .word CONTROL_MEM_RTA_CTRL 7540bd40535SRichard Woodruffkernel_flush: 7550bd40535SRichard Woodruff .word v7_flush_dcache_all 756c4236d2eSPeter 'p2' De Schrijverl2dis_3630: 757c4236d2eSPeter 'p2' De Schrijver .word 0 7589d93b8a2SPeter 'p2' De Schrijver /* 7599d93b8a2SPeter 'p2' De Schrijver * When exporting to userspace while the counters are in SRAM, 7609d93b8a2SPeter 'p2' De Schrijver * these 2 words need to be at the end to facilitate retrival! 7619d93b8a2SPeter 'p2' De Schrijver */ 7629d93b8a2SPeter 'p2' De Schrijverkick_counter: 7639d93b8a2SPeter 'p2' De Schrijver .word 0 7649d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_counter: 7659d93b8a2SPeter 'p2' De Schrijver .word 0 766f7dfe3d8SJean Pihet 7678bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend_sz) 7688bd22949SKevin Hilman .word . - omap34xx_cpu_suspend 769