18bd22949SKevin Hilman/* 28bd22949SKevin Hilman * (C) Copyright 2007 38bd22949SKevin Hilman * Texas Instruments 48bd22949SKevin Hilman * Karthik Dasu <karthik-dp@ti.com> 58bd22949SKevin Hilman * 68bd22949SKevin Hilman * (C) Copyright 2004 78bd22949SKevin Hilman * Texas Instruments, <www.ti.com> 88bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 98bd22949SKevin Hilman * 108bd22949SKevin Hilman * This program is free software; you can redistribute it and/or 118bd22949SKevin Hilman * modify it under the terms of the GNU General Public License as 128bd22949SKevin Hilman * published by the Free Software Foundation; either version 2 of 138bd22949SKevin Hilman * the License, or (at your option) any later version. 148bd22949SKevin Hilman * 158bd22949SKevin Hilman * This program is distributed in the hope that it will be useful, 168bd22949SKevin Hilman * but WITHOUT ANY WARRANTY; without even the implied warranty of 178bd22949SKevin Hilman * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 188bd22949SKevin Hilman * GNU General Public License for more details. 198bd22949SKevin Hilman * 208bd22949SKevin Hilman * You should have received a copy of the GNU General Public License 218bd22949SKevin Hilman * along with this program; if not, write to the Free Software 228bd22949SKevin Hilman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 238bd22949SKevin Hilman * MA 02111-1307 USA 248bd22949SKevin Hilman */ 258bd22949SKevin Hilman#include <linux/linkage.h> 268bd22949SKevin Hilman#include <asm/assembler.h> 27b4b36fd9SJean Pihet#include <plat/sram.h> 288bd22949SKevin Hilman#include <mach/io.h> 298bd22949SKevin Hilman 3059fb659bSPaul Walmsley#include "cm2xxx_3xxx.h" 3159fb659bSPaul Walmsley#include "prm2xxx_3xxx.h" 328bd22949SKevin Hilman#include "sdrc.h" 334814ced5SPaul Walmsley#include "control.h" 348bd22949SKevin Hilman 35fe360e1cSJean Pihet/* 36fe360e1cSJean Pihet * Registers access definitions 37fe360e1cSJean Pihet */ 38fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_OFFS 0xc 39fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ 40fe360e1cSJean Pihet (SDRC_SCRATCHPAD_SEM_OFFS) 41fe360e1cSJean Pihet#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ 42fe360e1cSJean Pihet OMAP3430_PM_PREPWSTST 4337903009SAbhijit Pagare#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL 4489139dceSPeter 'p2' De Schrijver#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) 459d93b8a2SPeter 'p2' De Schrijver#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) 46fe360e1cSJean Pihet#define SRAM_BASE_P OMAP3_SRAM_PA 47fe360e1cSJean Pihet#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS 48fe360e1cSJean Pihet#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ 49fe360e1cSJean Pihet OMAP36XX_CONTROL_MEM_RTA_CTRL) 50fe360e1cSJean Pihet 51fe360e1cSJean Pihet/* Move this as correct place is available */ 52fe360e1cSJean Pihet#define SCRATCHPAD_MEM_OFFS 0x310 53fe360e1cSJean Pihet#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ 54fe360e1cSJean Pihet OMAP343X_CONTROL_MEM_WKUP +\ 55fe360e1cSJean Pihet SCRATCHPAD_MEM_OFFS) 568bd22949SKevin Hilman#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 570795a75aSTero Kristo#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) 580795a75aSTero Kristo#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) 590795a75aSTero Kristo#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) 600795a75aSTero Kristo#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) 610795a75aSTero Kristo#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) 620795a75aSTero Kristo#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) 630795a75aSTero Kristo#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) 6489139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 6589139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 668bd22949SKevin Hilman 67dd313947SDave Martin/* 68dd313947SDave Martin * This file needs be built unconditionally as ARM to interoperate correctly 69dd313947SDave Martin * with non-Thumb-2-capable firmware. 70dd313947SDave Martin */ 71dd313947SDave Martin .arm 72a89b6f00SRajendra Nayak 73d3cdfd2aSJean Pihet/* 74d3cdfd2aSJean Pihet * API functions 75d3cdfd2aSJean Pihet */ 76a89b6f00SRajendra Nayak 771e81bc01SJean Pihet .text 78c4236d2eSPeter 'p2' De Schrijver/* 79c4236d2eSPeter 'p2' De Schrijver * L2 cache needs to be toggled for stable OFF mode functionality on 3630. 801e81bc01SJean Pihet * This function sets up a flag that will allow for this toggling to take 81f7dfe3d8SJean Pihet * place on 3630. Hopefully some version in the future may not need this. 82c4236d2eSPeter 'p2' De Schrijver */ 83c4236d2eSPeter 'p2' De SchrijverENTRY(enable_omap3630_toggle_l2_on_restore) 84c4236d2eSPeter 'p2' De Schrijver stmfd sp!, {lr} @ save registers on stack 85c4236d2eSPeter 'p2' De Schrijver /* Setup so that we will disable and enable l2 */ 86c4236d2eSPeter 'p2' De Schrijver mov r1, #0x1 87dd313947SDave Martin adrl r2, l2dis_3630 @ may be too distant for plain adr 88dd313947SDave Martin str r1, [r2] 89c4236d2eSPeter 'p2' De Schrijver ldmfd sp!, {pc} @ restore regs and return 90dd313947SDave MartinENDPROC(enable_omap3630_toggle_l2_on_restore) 91c4236d2eSPeter 'p2' De Schrijver 92bb1c9034SJean Pihet .text 9327d59a4aSTero Kristo/* Function to call rom code to save secure ram context */ 94b6338bdcSJean Pihet .align 3 9527d59a4aSTero KristoENTRY(save_secure_ram_context) 96857c1b81SRussell King stmfd sp!, {r4 - r11, lr} @ save registers on stack 9727d59a4aSTero Kristo adr r3, api_params @ r3 points to parameters 9827d59a4aSTero Kristo str r0, [r3,#0x4] @ r0 has sdram address 9927d59a4aSTero Kristo ldr r12, high_mask 10027d59a4aSTero Kristo and r3, r3, r12 10127d59a4aSTero Kristo ldr r12, sram_phy_addr_mask 10227d59a4aSTero Kristo orr r3, r3, r12 10327d59a4aSTero Kristo mov r0, #25 @ set service ID for PPA 10427d59a4aSTero Kristo mov r12, r0 @ copy secure service ID in r12 10527d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 106ba50ea7eSKalle Jokiniemi mov r2, #4 @ set some flags in r2, r6 10727d59a4aSTero Kristo mov r6, #0xff 1084444d712SSantosh Shilimkar dsb @ data write barrier 1094444d712SSantosh Shilimkar dmb @ data memory barrier 11076d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 11127d59a4aSTero Kristo nop 11227d59a4aSTero Kristo nop 11327d59a4aSTero Kristo nop 11427d59a4aSTero Kristo nop 115857c1b81SRussell King ldmfd sp!, {r4 - r11, pc} 116dd313947SDave Martin .align 11727d59a4aSTero Kristosram_phy_addr_mask: 11827d59a4aSTero Kristo .word SRAM_BASE_P 11927d59a4aSTero Kristohigh_mask: 12027d59a4aSTero Kristo .word 0xffff 12127d59a4aSTero Kristoapi_params: 12227d59a4aSTero Kristo .word 0x4, 0x0, 0x0, 0x1, 0x1 123dd313947SDave MartinENDPROC(save_secure_ram_context) 12427d59a4aSTero KristoENTRY(save_secure_ram_context_sz) 12527d59a4aSTero Kristo .word . - save_secure_ram_context 12627d59a4aSTero Kristo 1278bd22949SKevin Hilman/* 128f7dfe3d8SJean Pihet * ====================== 129f7dfe3d8SJean Pihet * == Idle entry point == 130f7dfe3d8SJean Pihet * ====================== 131f7dfe3d8SJean Pihet */ 132f7dfe3d8SJean Pihet 133f7dfe3d8SJean Pihet/* 1348bd22949SKevin Hilman * Forces OMAP into idle state 1358bd22949SKevin Hilman * 136f7dfe3d8SJean Pihet * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed 137f7dfe3d8SJean Pihet * and executes the WFI instruction. Calling WFI effectively changes the 138f7dfe3d8SJean Pihet * power domains states to the desired target power states. 1398bd22949SKevin Hilman * 140f7dfe3d8SJean Pihet * 141f7dfe3d8SJean Pihet * Notes: 142*46e130d2SJean Pihet * - only the minimum set of functions gets copied to internal SRAM at boot 143*46e130d2SJean Pihet * and after wake-up from OFF mode, cf. omap_push_sram_idle. The function 144*46e130d2SJean Pihet * pointers in SDRAM or SRAM are called depending on the desired low power 145*46e130d2SJean Pihet * target state. 146f7dfe3d8SJean Pihet * - when the OMAP wakes up it continues at different execution points 147f7dfe3d8SJean Pihet * depending on the low power mode (non-OFF vs OFF modes), 148f7dfe3d8SJean Pihet * cf. 'Resume path for xxx mode' comments. 1498bd22949SKevin Hilman */ 150b6338bdcSJean Pihet .align 3 1518bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend) 152857c1b81SRussell King stmfd sp!, {r4 - r11, lr} @ save registers on stack 153d3cdfd2aSJean Pihet 154f7dfe3d8SJean Pihet /* 155c9749a35SSantosh Shilimkar * r0 contains CPU context save/restore pointer in sdram 156f7dfe3d8SJean Pihet * r1 contains information about saving context: 157f7dfe3d8SJean Pihet * 0 - No context lost 158f7dfe3d8SJean Pihet * 1 - Only L1 and logic lost 159c9749a35SSantosh Shilimkar * 2 - Only L2 lost (Even L1 is retained we clean it along with L2) 160c9749a35SSantosh Shilimkar * 3 - Both L1 and L2 lost and logic lost 161f7dfe3d8SJean Pihet */ 162f7dfe3d8SJean Pihet 163*46e130d2SJean Pihet /* 164*46e130d2SJean Pihet * For OFF mode: save context and jump to WFI in SDRAM (omap3_do_wfi) 165*46e130d2SJean Pihet * For non-OFF modes: jump to the WFI code in SRAM (omap3_do_wfi_sram) 166*46e130d2SJean Pihet */ 167*46e130d2SJean Pihet ldr r4, omap3_do_wfi_sram_addr 168*46e130d2SJean Pihet ldr r5, [r4] 169*46e130d2SJean Pihet cmp r1, #0x0 @ If no context save required, 170*46e130d2SJean Pihet bxeq r5 @ jump to the WFI code in SRAM 171*46e130d2SJean Pihet 172f7dfe3d8SJean Pihet 173f7dfe3d8SJean Pihet /* Otherwise fall through to the save context code */ 174f7dfe3d8SJean Pihetsave_context_wfi: 175f7dfe3d8SJean Pihet mov r8, r0 @ Store SDRAM address in r8 176f7dfe3d8SJean Pihet mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register 177f7dfe3d8SJean Pihet mov r4, #0x1 @ Number of parameters for restore call 178f7dfe3d8SJean Pihet stmia r8!, {r4-r5} @ Push parameters for restore call 179f7dfe3d8SJean Pihet mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register 180f7dfe3d8SJean Pihet stmia r8!, {r4-r5} @ Push parameters for restore call 181f7dfe3d8SJean Pihet 182f7dfe3d8SJean Pihet /* 183f7dfe3d8SJean Pihet * jump out to kernel flush routine 184f7dfe3d8SJean Pihet * - reuse that code is better 185f7dfe3d8SJean Pihet * - it executes in a cached space so is faster than refetch per-block 186f7dfe3d8SJean Pihet * - should be faster and will change with kernel 187f7dfe3d8SJean Pihet * - 'might' have to copy address, load and jump to it 18890625110SSantosh Shilimkar * Flush all data from the L1 data cache before disabling 18990625110SSantosh Shilimkar * SCTLR.C bit. 190f7dfe3d8SJean Pihet */ 191f7dfe3d8SJean Pihet ldr r1, kernel_flush 192f7dfe3d8SJean Pihet mov lr, pc 193f7dfe3d8SJean Pihet bx r1 194f7dfe3d8SJean Pihet 19590625110SSantosh Shilimkar /* 19690625110SSantosh Shilimkar * Clear the SCTLR.C bit to prevent further data cache 19790625110SSantosh Shilimkar * allocation. Clearing SCTLR.C would make all the data accesses 19890625110SSantosh Shilimkar * strongly ordered and would not hit the cache. 19990625110SSantosh Shilimkar */ 20090625110SSantosh Shilimkar mrc p15, 0, r0, c1, c0, 0 20190625110SSantosh Shilimkar bic r0, r0, #(1 << 2) @ Disable the C bit 20290625110SSantosh Shilimkar mcr p15, 0, r0, c1, c0, 0 20390625110SSantosh Shilimkar isb 20490625110SSantosh Shilimkar 20590625110SSantosh Shilimkar /* 20690625110SSantosh Shilimkar * Invalidate L1 data cache. Even though only invalidate is 20790625110SSantosh Shilimkar * necessary exported flush API is used here. Doing clean 20890625110SSantosh Shilimkar * on already clean cache would be almost NOP. 209f7dfe3d8SJean Pihet */ 210f7dfe3d8SJean Pihet ldr r1, kernel_flush 211dd313947SDave Martin blx r1 212dd313947SDave Martin /* 213dd313947SDave Martin * The kernel doesn't interwork: v7_flush_dcache_all in particluar will 214dd313947SDave Martin * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. 215dd313947SDave Martin * This sequence switches back to ARM. Note that .align may insert a 216dd313947SDave Martin * nop: bx pc needs to be word-aligned in order to work. 217dd313947SDave Martin */ 218dd313947SDave Martin THUMB( .thumb ) 219dd313947SDave Martin THUMB( .align ) 220dd313947SDave Martin THUMB( bx pc ) 221dd313947SDave Martin THUMB( nop ) 222dd313947SDave Martin .arm 223f7dfe3d8SJean Pihet 224*46e130d2SJean Pihet b omap3_do_wfi 225*46e130d2SJean Pihet 226*46e130d2SJean Pihet/* 227*46e130d2SJean Pihet * Local variables 228*46e130d2SJean Pihet */ 229*46e130d2SJean Pihetomap3_do_wfi_sram_addr: 230*46e130d2SJean Pihet .word omap3_do_wfi_sram 231*46e130d2SJean Pihetkernel_flush: 232*46e130d2SJean Pihet .word v7_flush_dcache_all 233*46e130d2SJean Pihet 234*46e130d2SJean Pihet/* =================================== 235*46e130d2SJean Pihet * == WFI instruction => Enter idle == 236*46e130d2SJean Pihet * =================================== 237*46e130d2SJean Pihet */ 238*46e130d2SJean Pihet 239*46e130d2SJean Pihet/* 240*46e130d2SJean Pihet * Do WFI instruction 241*46e130d2SJean Pihet * Includes the resume path for non-OFF modes 242*46e130d2SJean Pihet * 243*46e130d2SJean Pihet * This code gets copied to internal SRAM and is accessible 244*46e130d2SJean Pihet * from both SDRAM and SRAM: 245*46e130d2SJean Pihet * - executed from SRAM for non-off modes (omap3_do_wfi_sram), 246*46e130d2SJean Pihet * - executed from SDRAM for OFF mode (omap3_do_wfi). 247*46e130d2SJean Pihet */ 248*46e130d2SJean Pihet .align 3 249*46e130d2SJean PihetENTRY(omap3_do_wfi) 2508bd22949SKevin Hilman ldr r4, sdrc_power @ read the SDRC_POWER register 2518bd22949SKevin Hilman ldr r5, [r4] @ read the contents of SDRC_POWER 2528bd22949SKevin Hilman orr r5, r5, #0x40 @ enable self refresh on idle req 2538bd22949SKevin Hilman str r5, [r4] @ write back to SDRC_POWER register 2548bd22949SKevin Hilman 2558bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 2564444d712SSantosh Shilimkar dsb 2574444d712SSantosh Shilimkar dmb 2588bd22949SKevin Hilman 259f7dfe3d8SJean Pihet/* 260f7dfe3d8SJean Pihet * =================================== 261f7dfe3d8SJean Pihet * == WFI instruction => Enter idle == 262f7dfe3d8SJean Pihet * =================================== 263f7dfe3d8SJean Pihet */ 2648bd22949SKevin Hilman wfi @ wait for interrupt 2658bd22949SKevin Hilman 266f7dfe3d8SJean Pihet/* 267f7dfe3d8SJean Pihet * =================================== 268f7dfe3d8SJean Pihet * == Resume path for non-OFF modes == 269f7dfe3d8SJean Pihet * =================================== 270f7dfe3d8SJean Pihet */ 2718bd22949SKevin Hilman nop 2728bd22949SKevin Hilman nop 2738bd22949SKevin Hilman nop 2748bd22949SKevin Hilman nop 2758bd22949SKevin Hilman nop 2768bd22949SKevin Hilman nop 2778bd22949SKevin Hilman nop 2788bd22949SKevin Hilman nop 2798bd22949SKevin Hilman nop 2808bd22949SKevin Hilman nop 2818bd22949SKevin Hilman 282*46e130d2SJean Pihet/* 283*46e130d2SJean Pihet * This function implements the erratum ID i581 WA: 284*46e130d2SJean Pihet * SDRC state restore before accessing the SDRAM 285*46e130d2SJean Pihet * 286*46e130d2SJean Pihet * Only used at return from non-OFF mode. For OFF 287*46e130d2SJean Pihet * mode the ROM code configures the SDRC and 288*46e130d2SJean Pihet * the DPLL before calling the restore code directly 289*46e130d2SJean Pihet * from DDR. 290*46e130d2SJean Pihet */ 291*46e130d2SJean Pihet 292*46e130d2SJean Pihet/* Make sure SDRC accesses are ok */ 293*46e130d2SJean Pihetwait_sdrc_ok: 294*46e130d2SJean Pihet 295*46e130d2SJean Pihet/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */ 296*46e130d2SJean Pihet ldr r4, cm_idlest_ckgen 297*46e130d2SJean Pihetwait_dpll3_lock: 298*46e130d2SJean Pihet ldr r5, [r4] 299*46e130d2SJean Pihet tst r5, #1 300*46e130d2SJean Pihet beq wait_dpll3_lock 301*46e130d2SJean Pihet 302*46e130d2SJean Pihet ldr r4, cm_idlest1_core 303*46e130d2SJean Pihetwait_sdrc_ready: 304*46e130d2SJean Pihet ldr r5, [r4] 305*46e130d2SJean Pihet tst r5, #0x2 306*46e130d2SJean Pihet bne wait_sdrc_ready 307*46e130d2SJean Pihet /* allow DLL powerdown upon hw idle req */ 308*46e130d2SJean Pihet ldr r4, sdrc_power 309*46e130d2SJean Pihet ldr r5, [r4] 310*46e130d2SJean Pihet bic r5, r5, #0x40 311*46e130d2SJean Pihet str r5, [r4] 312*46e130d2SJean Pihet 313*46e130d2SJean Pihet/* 314*46e130d2SJean Pihet * PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a 315*46e130d2SJean Pihet * base instead. 316*46e130d2SJean Pihet * Be careful not to clobber r7 when maintaing this code. 317*46e130d2SJean Pihet */ 318*46e130d2SJean Pihet 319*46e130d2SJean Pihetis_dll_in_lock_mode: 320*46e130d2SJean Pihet /* Is dll in lock mode? */ 321*46e130d2SJean Pihet ldr r4, sdrc_dlla_ctrl 322*46e130d2SJean Pihet ldr r5, [r4] 323*46e130d2SJean Pihet tst r5, #0x4 324*46e130d2SJean Pihet bne exit_nonoff_modes @ Return if locked 325*46e130d2SJean Pihet /* wait till dll locks */ 326*46e130d2SJean Pihet adr r7, kick_counter 327*46e130d2SJean Pihetwait_dll_lock_timed: 328*46e130d2SJean Pihet ldr r4, wait_dll_lock_counter 329*46e130d2SJean Pihet add r4, r4, #1 330*46e130d2SJean Pihet str r4, [r7, #wait_dll_lock_counter - kick_counter] 331*46e130d2SJean Pihet ldr r4, sdrc_dlla_status 332*46e130d2SJean Pihet /* Wait 20uS for lock */ 333*46e130d2SJean Pihet mov r6, #8 334*46e130d2SJean Pihetwait_dll_lock: 335*46e130d2SJean Pihet subs r6, r6, #0x1 336*46e130d2SJean Pihet beq kick_dll 337*46e130d2SJean Pihet ldr r5, [r4] 338*46e130d2SJean Pihet and r5, r5, #0x4 339*46e130d2SJean Pihet cmp r5, #0x4 340*46e130d2SJean Pihet bne wait_dll_lock 341*46e130d2SJean Pihet b exit_nonoff_modes @ Return when locked 342*46e130d2SJean Pihet 343*46e130d2SJean Pihet /* disable/reenable DLL if not locked */ 344*46e130d2SJean Pihetkick_dll: 345*46e130d2SJean Pihet ldr r4, sdrc_dlla_ctrl 346*46e130d2SJean Pihet ldr r5, [r4] 347*46e130d2SJean Pihet mov r6, r5 348*46e130d2SJean Pihet bic r6, #(1<<3) @ disable dll 349*46e130d2SJean Pihet str r6, [r4] 350*46e130d2SJean Pihet dsb 351*46e130d2SJean Pihet orr r6, r6, #(1<<3) @ enable dll 352*46e130d2SJean Pihet str r6, [r4] 353*46e130d2SJean Pihet dsb 354*46e130d2SJean Pihet ldr r4, kick_counter 355*46e130d2SJean Pihet add r4, r4, #1 356*46e130d2SJean Pihet str r4, [r7] @ kick_counter 357*46e130d2SJean Pihet b wait_dll_lock_timed 358*46e130d2SJean Pihet 359*46e130d2SJean Pihetexit_nonoff_modes: 360*46e130d2SJean Pihet /* Re-enable C-bit if needed */ 36190625110SSantosh Shilimkar mrc p15, 0, r0, c1, c0, 0 36290625110SSantosh Shilimkar tst r0, #(1 << 2) @ Check C bit enabled? 36390625110SSantosh Shilimkar orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared 36490625110SSantosh Shilimkar mcreq p15, 0, r0, c1, c0, 0 36590625110SSantosh Shilimkar isb 36690625110SSantosh Shilimkar 367f7dfe3d8SJean Pihet/* 368f7dfe3d8SJean Pihet * =================================== 369f7dfe3d8SJean Pihet * == Exit point from non-OFF modes == 370f7dfe3d8SJean Pihet * =================================== 371f7dfe3d8SJean Pihet */ 372857c1b81SRussell King ldmfd sp!, {r4 - r11, pc} @ restore regs and return 373f7dfe3d8SJean Pihet 374*46e130d2SJean Pihet/* 375*46e130d2SJean Pihet * Local variables 376*46e130d2SJean Pihet */ 377*46e130d2SJean Pihetsdrc_power: 378*46e130d2SJean Pihet .word SDRC_POWER_V 379*46e130d2SJean Pihetcm_idlest1_core: 380*46e130d2SJean Pihet .word CM_IDLEST1_CORE_V 381*46e130d2SJean Pihetcm_idlest_ckgen: 382*46e130d2SJean Pihet .word CM_IDLEST_CKGEN_V 383*46e130d2SJean Pihetsdrc_dlla_status: 384*46e130d2SJean Pihet .word SDRC_DLLA_STATUS_V 385*46e130d2SJean Pihetsdrc_dlla_ctrl: 386*46e130d2SJean Pihet .word SDRC_DLLA_CTRL_V 387*46e130d2SJean Pihet /* 388*46e130d2SJean Pihet * When exporting to userspace while the counters are in SRAM, 389*46e130d2SJean Pihet * these 2 words need to be at the end to facilitate retrival! 390*46e130d2SJean Pihet */ 391*46e130d2SJean Pihetkick_counter: 392*46e130d2SJean Pihet .word 0 393*46e130d2SJean Pihetwait_dll_lock_counter: 394*46e130d2SJean Pihet .word 0 395*46e130d2SJean Pihet 396*46e130d2SJean PihetENTRY(omap3_do_wfi_sz) 397*46e130d2SJean Pihet .word . - omap3_do_wfi 398*46e130d2SJean Pihet 399f7dfe3d8SJean Pihet 400f7dfe3d8SJean Pihet/* 401f7dfe3d8SJean Pihet * ============================== 402f7dfe3d8SJean Pihet * == Resume path for OFF mode == 403f7dfe3d8SJean Pihet * ============================== 404f7dfe3d8SJean Pihet */ 405f7dfe3d8SJean Pihet 406f7dfe3d8SJean Pihet/* 407f7dfe3d8SJean Pihet * The restore_* functions are called by the ROM code 408f7dfe3d8SJean Pihet * when back from WFI in OFF mode. 409f7dfe3d8SJean Pihet * Cf. the get_*restore_pointer functions. 410f7dfe3d8SJean Pihet * 411f7dfe3d8SJean Pihet * restore_es3: applies to 34xx >= ES3.0 412f7dfe3d8SJean Pihet * restore_3630: applies to 36xx 413f7dfe3d8SJean Pihet * restore: common code for 3xxx 414*46e130d2SJean Pihet * 415*46e130d2SJean Pihet * Note: when back from CORE and MPU OFF mode we are running 416*46e130d2SJean Pihet * from SDRAM, without MMU, without the caches and prediction. 417*46e130d2SJean Pihet * Also the SRAM content has been cleared. 418f7dfe3d8SJean Pihet */ 41914c79bbeSKevin HilmanENTRY(omap3_restore_es3) 4200795a75aSTero Kristo ldr r5, pm_prepwstst_core_p 4210795a75aSTero Kristo ldr r4, [r5] 4220795a75aSTero Kristo and r4, r4, #0x3 4230795a75aSTero Kristo cmp r4, #0x0 @ Check if previous power state of CORE is OFF 424*46e130d2SJean Pihet bne omap3_restore @ Fall through to OMAP3 common code 4250795a75aSTero Kristo adr r0, es3_sdrc_fix 4260795a75aSTero Kristo ldr r1, sram_base 4270795a75aSTero Kristo ldr r2, es3_sdrc_fix_sz 4280795a75aSTero Kristo mov r2, r2, ror #2 4290795a75aSTero Kristocopy_to_sram: 4300795a75aSTero Kristo ldmia r0!, {r3} @ val = *src 4310795a75aSTero Kristo stmia r1!, {r3} @ *dst = val 4320795a75aSTero Kristo subs r2, r2, #0x1 @ num_words-- 4330795a75aSTero Kristo bne copy_to_sram 4340795a75aSTero Kristo ldr r1, sram_base 4350795a75aSTero Kristo blx r1 436*46e130d2SJean Pihet b omap3_restore @ Fall through to OMAP3 common code 43714c79bbeSKevin HilmanENDPROC(omap3_restore_es3) 438458e999eSNishanth Menon 43914c79bbeSKevin HilmanENTRY(omap3_restore_3630) 440458e999eSNishanth Menon ldr r1, pm_prepwstst_core_p 441458e999eSNishanth Menon ldr r2, [r1] 442458e999eSNishanth Menon and r2, r2, #0x3 443458e999eSNishanth Menon cmp r2, #0x0 @ Check if previous power state of CORE is OFF 444*46e130d2SJean Pihet bne omap3_restore @ Fall through to OMAP3 common code 445458e999eSNishanth Menon /* Disable RTA before giving control */ 446458e999eSNishanth Menon ldr r1, control_mem_rta 447458e999eSNishanth Menon mov r2, #OMAP36XX_RTA_DISABLE 448458e999eSNishanth Menon str r2, [r1] 44914c79bbeSKevin HilmanENDPROC(omap3_restore_3630) 450f7dfe3d8SJean Pihet 451f7dfe3d8SJean Pihet /* Fall through to common code for the remaining logic */ 452f7dfe3d8SJean Pihet 45314c79bbeSKevin HilmanENTRY(omap3_restore) 454f7dfe3d8SJean Pihet /* 4552637ce30SRussell King * Read the pwstctrl register to check the reason for mpu reset. 4562637ce30SRussell King * This tells us what was lost. 457f7dfe3d8SJean Pihet */ 4588bd22949SKevin Hilman ldr r1, pm_pwstctrl_mpu 4598bd22949SKevin Hilman ldr r2, [r1] 4608bd22949SKevin Hilman and r2, r2, #0x3 4618bd22949SKevin Hilman cmp r2, #0x0 @ Check if target power state was OFF or RET 4628bd22949SKevin Hilman bne logic_l1_restore 463c4236d2eSPeter 'p2' De Schrijver 464c4236d2eSPeter 'p2' De Schrijver ldr r0, l2dis_3630 465c4236d2eSPeter 'p2' De Schrijver cmp r0, #0x1 @ should we disable L2 on 3630? 466c4236d2eSPeter 'p2' De Schrijver bne skipl2dis 467c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r0, c1, c0, 1 468c4236d2eSPeter 'p2' De Schrijver bic r0, r0, #2 @ disable L2 cache 469c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r0, c1, c0, 1 470c4236d2eSPeter 'p2' De Schrijverskipl2dis: 47127d59a4aSTero Kristo ldr r0, control_stat 47227d59a4aSTero Kristo ldr r1, [r0] 47327d59a4aSTero Kristo and r1, #0x700 47427d59a4aSTero Kristo cmp r1, #0x300 47527d59a4aSTero Kristo beq l2_inv_gp 47627d59a4aSTero Kristo mov r0, #40 @ set service ID for PPA 47727d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 47827d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 47927d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 48027d59a4aSTero Kristo mov r6, #0xff 48127d59a4aSTero Kristo adr r3, l2_inv_api_params @ r3 points to dummy parameters 4824444d712SSantosh Shilimkar dsb @ data write barrier 4834444d712SSantosh Shilimkar dmb @ data memory barrier 48476d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 48527d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 48627d59a4aSTero Kristo mov r0, #42 @ set service ID for PPA 48727d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 48827d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 48927d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 49027d59a4aSTero Kristo mov r6, #0xff 491a087cad9STero Kristo ldr r4, scratchpad_base 492a087cad9STero Kristo ldr r3, [r4, #0xBC] @ r3 points to parameters 4934444d712SSantosh Shilimkar dsb @ data write barrier 4944444d712SSantosh Shilimkar dmb @ data memory barrier 49576d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 49627d59a4aSTero Kristo 49779dcfdd4STero Kristo#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 49879dcfdd4STero Kristo /* Restore L2 aux control register */ 49979dcfdd4STero Kristo @ set service ID for PPA 50079dcfdd4STero Kristo mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 50179dcfdd4STero Kristo mov r12, r0 @ copy service ID in r12 50279dcfdd4STero Kristo mov r1, #0 @ set task ID for ROM code in r1 50379dcfdd4STero Kristo mov r2, #4 @ set some flags in r2, r6 50479dcfdd4STero Kristo mov r6, #0xff 50579dcfdd4STero Kristo ldr r4, scratchpad_base 50679dcfdd4STero Kristo ldr r3, [r4, #0xBC] 50779dcfdd4STero Kristo adds r3, r3, #8 @ r3 points to parameters 5084444d712SSantosh Shilimkar dsb @ data write barrier 5094444d712SSantosh Shilimkar dmb @ data memory barrier 51076d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 51179dcfdd4STero Kristo#endif 51227d59a4aSTero Kristo b logic_l1_restore 513bb1c9034SJean Pihet 514dd313947SDave Martin .align 51527d59a4aSTero Kristol2_inv_api_params: 51627d59a4aSTero Kristo .word 0x1, 0x00 51727d59a4aSTero Kristol2_inv_gp: 5188bd22949SKevin Hilman /* Execute smi to invalidate L2 cache */ 519bb1c9034SJean Pihet mov r12, #0x1 @ set up to invalidate L2 52076d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 52127d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 522a087cad9STero Kristo ldr r4, scratchpad_base 523a087cad9STero Kristo ldr r3, [r4,#0xBC] 524a087cad9STero Kristo ldr r0, [r3,#4] 52527d59a4aSTero Kristo mov r12, #0x3 52676d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 52779dcfdd4STero Kristo ldr r4, scratchpad_base 52879dcfdd4STero Kristo ldr r3, [r4,#0xBC] 52979dcfdd4STero Kristo ldr r0, [r3,#12] 53079dcfdd4STero Kristo mov r12, #0x2 53176d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 5328bd22949SKevin Hilmanlogic_l1_restore: 533c4236d2eSPeter 'p2' De Schrijver ldr r1, l2dis_3630 534bb1c9034SJean Pihet cmp r1, #0x1 @ Test if L2 re-enable needed on 3630 535c4236d2eSPeter 'p2' De Schrijver bne skipl2reen 536c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r1, c1, c0, 1 537c4236d2eSPeter 'p2' De Schrijver orr r1, r1, #2 @ re-enable L2 cache 538c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r1, c1, c0, 1 539c4236d2eSPeter 'p2' De Schrijverskipl2reen: 5408bd22949SKevin Hilman 541076f2cc4SRussell King /* Now branch to the common CPU resume function */ 542076f2cc4SRussell King b cpu_resume 54314c79bbeSKevin HilmanENDPROC(omap3_restore) 54446f557cbSSantosh Shilimkar 545076f2cc4SRussell King .ltorg 5461e81bc01SJean Pihet 5471e81bc01SJean Pihet/* 548*46e130d2SJean Pihet * Local variables 549*46e130d2SJean Pihet */ 550*46e130d2SJean Pihetpm_prepwstst_core_p: 551*46e130d2SJean Pihet .word PM_PREPWSTST_CORE_P 552*46e130d2SJean Pihetpm_pwstctrl_mpu: 553*46e130d2SJean Pihet .word PM_PWSTCTRL_MPU_P 554*46e130d2SJean Pihetscratchpad_base: 555*46e130d2SJean Pihet .word SCRATCHPAD_BASE_P 556*46e130d2SJean Pihetsram_base: 557*46e130d2SJean Pihet .word SRAM_BASE_P + 0x8000 558*46e130d2SJean Pihetcontrol_stat: 559*46e130d2SJean Pihet .word CONTROL_STAT 560*46e130d2SJean Pihetcontrol_mem_rta: 561*46e130d2SJean Pihet .word CONTROL_MEM_RTA_CTRL 562*46e130d2SJean Pihetl2dis_3630: 563*46e130d2SJean Pihet .word 0 564*46e130d2SJean Pihet 565*46e130d2SJean Pihet/* 5661e81bc01SJean Pihet * Internal functions 5671e81bc01SJean Pihet */ 5681e81bc01SJean Pihet 569*46e130d2SJean Pihet/* 570*46e130d2SJean Pihet * This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 571*46e130d2SJean Pihet * Copied to and run from SRAM in order to reconfigure the SDRC parameters. 572*46e130d2SJean Pihet */ 5731e81bc01SJean Pihet .text 574dd313947SDave Martin .align 3 5751e81bc01SJean PihetENTRY(es3_sdrc_fix) 5761e81bc01SJean Pihet ldr r4, sdrc_syscfg @ get config addr 5771e81bc01SJean Pihet ldr r5, [r4] @ get value 5781e81bc01SJean Pihet tst r5, #0x100 @ is part access blocked 5791e81bc01SJean Pihet it eq 5801e81bc01SJean Pihet biceq r5, r5, #0x100 @ clear bit if set 5811e81bc01SJean Pihet str r5, [r4] @ write back change 5821e81bc01SJean Pihet ldr r4, sdrc_mr_0 @ get config addr 5831e81bc01SJean Pihet ldr r5, [r4] @ get value 5841e81bc01SJean Pihet str r5, [r4] @ write back change 5851e81bc01SJean Pihet ldr r4, sdrc_emr2_0 @ get config addr 5861e81bc01SJean Pihet ldr r5, [r4] @ get value 5871e81bc01SJean Pihet str r5, [r4] @ write back change 5881e81bc01SJean Pihet ldr r4, sdrc_manual_0 @ get config addr 5891e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 5901e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 5911e81bc01SJean Pihet ldr r4, sdrc_mr_1 @ get config addr 5921e81bc01SJean Pihet ldr r5, [r4] @ get value 5931e81bc01SJean Pihet str r5, [r4] @ write back change 5941e81bc01SJean Pihet ldr r4, sdrc_emr2_1 @ get config addr 5951e81bc01SJean Pihet ldr r5, [r4] @ get value 5961e81bc01SJean Pihet str r5, [r4] @ write back change 5971e81bc01SJean Pihet ldr r4, sdrc_manual_1 @ get config addr 5981e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 5991e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 6001e81bc01SJean Pihet bx lr 6011e81bc01SJean Pihet 602*46e130d2SJean Pihet/* 603*46e130d2SJean Pihet * Local variables 604*46e130d2SJean Pihet */ 605dd313947SDave Martin .align 6061e81bc01SJean Pihetsdrc_syscfg: 6071e81bc01SJean Pihet .word SDRC_SYSCONFIG_P 6081e81bc01SJean Pihetsdrc_mr_0: 6091e81bc01SJean Pihet .word SDRC_MR_0_P 6101e81bc01SJean Pihetsdrc_emr2_0: 6111e81bc01SJean Pihet .word SDRC_EMR2_0_P 6121e81bc01SJean Pihetsdrc_manual_0: 6131e81bc01SJean Pihet .word SDRC_MANUAL_0_P 6141e81bc01SJean Pihetsdrc_mr_1: 6151e81bc01SJean Pihet .word SDRC_MR_1_P 6161e81bc01SJean Pihetsdrc_emr2_1: 6171e81bc01SJean Pihet .word SDRC_EMR2_1_P 6181e81bc01SJean Pihetsdrc_manual_1: 6191e81bc01SJean Pihet .word SDRC_MANUAL_1_P 620dd313947SDave MartinENDPROC(es3_sdrc_fix) 6211e81bc01SJean PihetENTRY(es3_sdrc_fix_sz) 6221e81bc01SJean Pihet .word . - es3_sdrc_fix 623