18bd22949SKevin Hilman/* 28bd22949SKevin Hilman * (C) Copyright 2007 38bd22949SKevin Hilman * Texas Instruments 48bd22949SKevin Hilman * Karthik Dasu <karthik-dp@ti.com> 58bd22949SKevin Hilman * 68bd22949SKevin Hilman * (C) Copyright 2004 78bd22949SKevin Hilman * Texas Instruments, <www.ti.com> 88bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 98bd22949SKevin Hilman * 108bd22949SKevin Hilman * This program is free software; you can redistribute it and/or 118bd22949SKevin Hilman * modify it under the terms of the GNU General Public License as 128bd22949SKevin Hilman * published by the Free Software Foundation; either version 2 of 138bd22949SKevin Hilman * the License, or (at your option) any later version. 148bd22949SKevin Hilman * 158bd22949SKevin Hilman * This program is distributed in the hope that it will be useful, 168bd22949SKevin Hilman * but WITHOUT ANY WARRANTY; without even the implied warranty of 178bd22949SKevin Hilman * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 188bd22949SKevin Hilman * GNU General Public License for more details. 198bd22949SKevin Hilman * 208bd22949SKevin Hilman * You should have received a copy of the GNU General Public License 218bd22949SKevin Hilman * along with this program; if not, write to the Free Software 228bd22949SKevin Hilman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 238bd22949SKevin Hilman * MA 02111-1307 USA 248bd22949SKevin Hilman */ 258bd22949SKevin Hilman#include <linux/linkage.h> 268bd22949SKevin Hilman 27ee0839c2STony Lindgren#include <asm/assembler.h> 28ee0839c2STony Lindgren 29ee0839c2STony Lindgren#include <plat/sram.h> 30ee0839c2STony Lindgren 31c49f34bcSTony Lindgren#include "omap34xx.h" 32ee0839c2STony Lindgren#include "iomap.h" 3359fb659bSPaul Walmsley#include "cm2xxx_3xxx.h" 34*139563adSPaul Walmsley#include "prm3xxx.h" 358bd22949SKevin Hilman#include "sdrc.h" 364814ced5SPaul Walmsley#include "control.h" 378bd22949SKevin Hilman 38fe360e1cSJean Pihet/* 39fe360e1cSJean Pihet * Registers access definitions 40fe360e1cSJean Pihet */ 41fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_OFFS 0xc 42fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ 43fe360e1cSJean Pihet (SDRC_SCRATCHPAD_SEM_OFFS) 44fe360e1cSJean Pihet#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ 45fe360e1cSJean Pihet OMAP3430_PM_PREPWSTST 4637903009SAbhijit Pagare#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL 4789139dceSPeter 'p2' De Schrijver#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) 489d93b8a2SPeter 'p2' De Schrijver#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) 49fe360e1cSJean Pihet#define SRAM_BASE_P OMAP3_SRAM_PA 50fe360e1cSJean Pihet#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS 51fe360e1cSJean Pihet#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ 52fe360e1cSJean Pihet OMAP36XX_CONTROL_MEM_RTA_CTRL) 53fe360e1cSJean Pihet 54fe360e1cSJean Pihet/* Move this as correct place is available */ 55fe360e1cSJean Pihet#define SCRATCHPAD_MEM_OFFS 0x310 56fe360e1cSJean Pihet#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ 57fe360e1cSJean Pihet OMAP343X_CONTROL_MEM_WKUP +\ 58fe360e1cSJean Pihet SCRATCHPAD_MEM_OFFS) 598bd22949SKevin Hilman#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 600795a75aSTero Kristo#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) 610795a75aSTero Kristo#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) 620795a75aSTero Kristo#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) 630795a75aSTero Kristo#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) 640795a75aSTero Kristo#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) 650795a75aSTero Kristo#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) 660795a75aSTero Kristo#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) 6789139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 6889139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 698bd22949SKevin Hilman 70dd313947SDave Martin/* 71dd313947SDave Martin * This file needs be built unconditionally as ARM to interoperate correctly 72dd313947SDave Martin * with non-Thumb-2-capable firmware. 73dd313947SDave Martin */ 74dd313947SDave Martin .arm 75a89b6f00SRajendra Nayak 76d3cdfd2aSJean Pihet/* 77d3cdfd2aSJean Pihet * API functions 78d3cdfd2aSJean Pihet */ 79a89b6f00SRajendra Nayak 801e81bc01SJean Pihet .text 81c4236d2eSPeter 'p2' De Schrijver/* 82c4236d2eSPeter 'p2' De Schrijver * L2 cache needs to be toggled for stable OFF mode functionality on 3630. 831e81bc01SJean Pihet * This function sets up a flag that will allow for this toggling to take 84f7dfe3d8SJean Pihet * place on 3630. Hopefully some version in the future may not need this. 85c4236d2eSPeter 'p2' De Schrijver */ 86c4236d2eSPeter 'p2' De SchrijverENTRY(enable_omap3630_toggle_l2_on_restore) 87c4236d2eSPeter 'p2' De Schrijver stmfd sp!, {lr} @ save registers on stack 88c4236d2eSPeter 'p2' De Schrijver /* Setup so that we will disable and enable l2 */ 89c4236d2eSPeter 'p2' De Schrijver mov r1, #0x1 90dd313947SDave Martin adrl r2, l2dis_3630 @ may be too distant for plain adr 91dd313947SDave Martin str r1, [r2] 92c4236d2eSPeter 'p2' De Schrijver ldmfd sp!, {pc} @ restore regs and return 93dd313947SDave MartinENDPROC(enable_omap3630_toggle_l2_on_restore) 94c4236d2eSPeter 'p2' De Schrijver 95bb1c9034SJean Pihet .text 9627d59a4aSTero Kristo/* Function to call rom code to save secure ram context */ 97b6338bdcSJean Pihet .align 3 9827d59a4aSTero KristoENTRY(save_secure_ram_context) 99857c1b81SRussell King stmfd sp!, {r4 - r11, lr} @ save registers on stack 10027d59a4aSTero Kristo adr r3, api_params @ r3 points to parameters 10127d59a4aSTero Kristo str r0, [r3,#0x4] @ r0 has sdram address 10227d59a4aSTero Kristo ldr r12, high_mask 10327d59a4aSTero Kristo and r3, r3, r12 10427d59a4aSTero Kristo ldr r12, sram_phy_addr_mask 10527d59a4aSTero Kristo orr r3, r3, r12 10627d59a4aSTero Kristo mov r0, #25 @ set service ID for PPA 10727d59a4aSTero Kristo mov r12, r0 @ copy secure service ID in r12 10827d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 109ba50ea7eSKalle Jokiniemi mov r2, #4 @ set some flags in r2, r6 11027d59a4aSTero Kristo mov r6, #0xff 1114444d712SSantosh Shilimkar dsb @ data write barrier 1124444d712SSantosh Shilimkar dmb @ data memory barrier 11376d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 11427d59a4aSTero Kristo nop 11527d59a4aSTero Kristo nop 11627d59a4aSTero Kristo nop 11727d59a4aSTero Kristo nop 118857c1b81SRussell King ldmfd sp!, {r4 - r11, pc} 119dd313947SDave Martin .align 12027d59a4aSTero Kristosram_phy_addr_mask: 12127d59a4aSTero Kristo .word SRAM_BASE_P 12227d59a4aSTero Kristohigh_mask: 12327d59a4aSTero Kristo .word 0xffff 12427d59a4aSTero Kristoapi_params: 12527d59a4aSTero Kristo .word 0x4, 0x0, 0x0, 0x1, 0x1 126dd313947SDave MartinENDPROC(save_secure_ram_context) 12727d59a4aSTero KristoENTRY(save_secure_ram_context_sz) 12827d59a4aSTero Kristo .word . - save_secure_ram_context 12927d59a4aSTero Kristo 1308bd22949SKevin Hilman/* 131f7dfe3d8SJean Pihet * ====================== 132f7dfe3d8SJean Pihet * == Idle entry point == 133f7dfe3d8SJean Pihet * ====================== 134f7dfe3d8SJean Pihet */ 135f7dfe3d8SJean Pihet 136f7dfe3d8SJean Pihet/* 1378bd22949SKevin Hilman * Forces OMAP into idle state 1388bd22949SKevin Hilman * 139f7dfe3d8SJean Pihet * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed 140f7dfe3d8SJean Pihet * and executes the WFI instruction. Calling WFI effectively changes the 141f7dfe3d8SJean Pihet * power domains states to the desired target power states. 1428bd22949SKevin Hilman * 143f7dfe3d8SJean Pihet * 144f7dfe3d8SJean Pihet * Notes: 14546e130d2SJean Pihet * - only the minimum set of functions gets copied to internal SRAM at boot 14646e130d2SJean Pihet * and after wake-up from OFF mode, cf. omap_push_sram_idle. The function 14746e130d2SJean Pihet * pointers in SDRAM or SRAM are called depending on the desired low power 14846e130d2SJean Pihet * target state. 149f7dfe3d8SJean Pihet * - when the OMAP wakes up it continues at different execution points 150f7dfe3d8SJean Pihet * depending on the low power mode (non-OFF vs OFF modes), 151f7dfe3d8SJean Pihet * cf. 'Resume path for xxx mode' comments. 1528bd22949SKevin Hilman */ 153b6338bdcSJean Pihet .align 3 1548bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend) 155857c1b81SRussell King stmfd sp!, {r4 - r11, lr} @ save registers on stack 156d3cdfd2aSJean Pihet 157f7dfe3d8SJean Pihet /* 158cbe26349SRussell King * r0 contains information about saving context: 159f7dfe3d8SJean Pihet * 0 - No context lost 160f7dfe3d8SJean Pihet * 1 - Only L1 and logic lost 161c9749a35SSantosh Shilimkar * 2 - Only L2 lost (Even L1 is retained we clean it along with L2) 162c9749a35SSantosh Shilimkar * 3 - Both L1 and L2 lost and logic lost 163f7dfe3d8SJean Pihet */ 164f7dfe3d8SJean Pihet 16546e130d2SJean Pihet /* 16646e130d2SJean Pihet * For OFF mode: save context and jump to WFI in SDRAM (omap3_do_wfi) 16746e130d2SJean Pihet * For non-OFF modes: jump to the WFI code in SRAM (omap3_do_wfi_sram) 16846e130d2SJean Pihet */ 16946e130d2SJean Pihet ldr r4, omap3_do_wfi_sram_addr 17046e130d2SJean Pihet ldr r5, [r4] 171cbe26349SRussell King cmp r0, #0x0 @ If no context save required, 17246e130d2SJean Pihet bxeq r5 @ jump to the WFI code in SRAM 17346e130d2SJean Pihet 174f7dfe3d8SJean Pihet 175f7dfe3d8SJean Pihet /* Otherwise fall through to the save context code */ 176f7dfe3d8SJean Pihetsave_context_wfi: 177f7dfe3d8SJean Pihet /* 178f7dfe3d8SJean Pihet * jump out to kernel flush routine 179f7dfe3d8SJean Pihet * - reuse that code is better 180f7dfe3d8SJean Pihet * - it executes in a cached space so is faster than refetch per-block 181f7dfe3d8SJean Pihet * - should be faster and will change with kernel 182f7dfe3d8SJean Pihet * - 'might' have to copy address, load and jump to it 18390625110SSantosh Shilimkar * Flush all data from the L1 data cache before disabling 18490625110SSantosh Shilimkar * SCTLR.C bit. 185f7dfe3d8SJean Pihet */ 186f7dfe3d8SJean Pihet ldr r1, kernel_flush 187f7dfe3d8SJean Pihet mov lr, pc 188f7dfe3d8SJean Pihet bx r1 189f7dfe3d8SJean Pihet 19090625110SSantosh Shilimkar /* 19190625110SSantosh Shilimkar * Clear the SCTLR.C bit to prevent further data cache 19290625110SSantosh Shilimkar * allocation. Clearing SCTLR.C would make all the data accesses 19390625110SSantosh Shilimkar * strongly ordered and would not hit the cache. 19490625110SSantosh Shilimkar */ 19590625110SSantosh Shilimkar mrc p15, 0, r0, c1, c0, 0 19690625110SSantosh Shilimkar bic r0, r0, #(1 << 2) @ Disable the C bit 19790625110SSantosh Shilimkar mcr p15, 0, r0, c1, c0, 0 19890625110SSantosh Shilimkar isb 19990625110SSantosh Shilimkar 20090625110SSantosh Shilimkar /* 20190625110SSantosh Shilimkar * Invalidate L1 data cache. Even though only invalidate is 20290625110SSantosh Shilimkar * necessary exported flush API is used here. Doing clean 20390625110SSantosh Shilimkar * on already clean cache would be almost NOP. 204f7dfe3d8SJean Pihet */ 205f7dfe3d8SJean Pihet ldr r1, kernel_flush 206dd313947SDave Martin blx r1 207dd313947SDave Martin /* 208dd313947SDave Martin * The kernel doesn't interwork: v7_flush_dcache_all in particluar will 209dd313947SDave Martin * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. 210dd313947SDave Martin * This sequence switches back to ARM. Note that .align may insert a 211dd313947SDave Martin * nop: bx pc needs to be word-aligned in order to work. 212dd313947SDave Martin */ 213dd313947SDave Martin THUMB( .thumb ) 214dd313947SDave Martin THUMB( .align ) 215dd313947SDave Martin THUMB( bx pc ) 216dd313947SDave Martin THUMB( nop ) 217dd313947SDave Martin .arm 218f7dfe3d8SJean Pihet 21946e130d2SJean Pihet b omap3_do_wfi 22046e130d2SJean Pihet 22146e130d2SJean Pihet/* 22246e130d2SJean Pihet * Local variables 22346e130d2SJean Pihet */ 22446e130d2SJean Pihetomap3_do_wfi_sram_addr: 22546e130d2SJean Pihet .word omap3_do_wfi_sram 22646e130d2SJean Pihetkernel_flush: 22746e130d2SJean Pihet .word v7_flush_dcache_all 22846e130d2SJean Pihet 22946e130d2SJean Pihet/* =================================== 23046e130d2SJean Pihet * == WFI instruction => Enter idle == 23146e130d2SJean Pihet * =================================== 23246e130d2SJean Pihet */ 23346e130d2SJean Pihet 23446e130d2SJean Pihet/* 23546e130d2SJean Pihet * Do WFI instruction 23646e130d2SJean Pihet * Includes the resume path for non-OFF modes 23746e130d2SJean Pihet * 23846e130d2SJean Pihet * This code gets copied to internal SRAM and is accessible 23946e130d2SJean Pihet * from both SDRAM and SRAM: 24046e130d2SJean Pihet * - executed from SRAM for non-off modes (omap3_do_wfi_sram), 24146e130d2SJean Pihet * - executed from SDRAM for OFF mode (omap3_do_wfi). 24246e130d2SJean Pihet */ 24346e130d2SJean Pihet .align 3 24446e130d2SJean PihetENTRY(omap3_do_wfi) 2458bd22949SKevin Hilman ldr r4, sdrc_power @ read the SDRC_POWER register 2468bd22949SKevin Hilman ldr r5, [r4] @ read the contents of SDRC_POWER 2478bd22949SKevin Hilman orr r5, r5, #0x40 @ enable self refresh on idle req 2488bd22949SKevin Hilman str r5, [r4] @ write back to SDRC_POWER register 2498bd22949SKevin Hilman 2508bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 2514444d712SSantosh Shilimkar dsb 2524444d712SSantosh Shilimkar dmb 2538bd22949SKevin Hilman 254f7dfe3d8SJean Pihet/* 255f7dfe3d8SJean Pihet * =================================== 256f7dfe3d8SJean Pihet * == WFI instruction => Enter idle == 257f7dfe3d8SJean Pihet * =================================== 258f7dfe3d8SJean Pihet */ 2598bd22949SKevin Hilman wfi @ wait for interrupt 2608bd22949SKevin Hilman 261f7dfe3d8SJean Pihet/* 262f7dfe3d8SJean Pihet * =================================== 263f7dfe3d8SJean Pihet * == Resume path for non-OFF modes == 264f7dfe3d8SJean Pihet * =================================== 265f7dfe3d8SJean Pihet */ 2668bd22949SKevin Hilman nop 2678bd22949SKevin Hilman nop 2688bd22949SKevin Hilman nop 2698bd22949SKevin Hilman nop 2708bd22949SKevin Hilman nop 2718bd22949SKevin Hilman nop 2728bd22949SKevin Hilman nop 2738bd22949SKevin Hilman nop 2748bd22949SKevin Hilman nop 2758bd22949SKevin Hilman nop 2768bd22949SKevin Hilman 27746e130d2SJean Pihet/* 27846e130d2SJean Pihet * This function implements the erratum ID i581 WA: 27946e130d2SJean Pihet * SDRC state restore before accessing the SDRAM 28046e130d2SJean Pihet * 28146e130d2SJean Pihet * Only used at return from non-OFF mode. For OFF 28246e130d2SJean Pihet * mode the ROM code configures the SDRC and 28346e130d2SJean Pihet * the DPLL before calling the restore code directly 28446e130d2SJean Pihet * from DDR. 28546e130d2SJean Pihet */ 28646e130d2SJean Pihet 28746e130d2SJean Pihet/* Make sure SDRC accesses are ok */ 28846e130d2SJean Pihetwait_sdrc_ok: 28946e130d2SJean Pihet 29046e130d2SJean Pihet/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */ 29146e130d2SJean Pihet ldr r4, cm_idlest_ckgen 29246e130d2SJean Pihetwait_dpll3_lock: 29346e130d2SJean Pihet ldr r5, [r4] 29446e130d2SJean Pihet tst r5, #1 29546e130d2SJean Pihet beq wait_dpll3_lock 29646e130d2SJean Pihet 29746e130d2SJean Pihet ldr r4, cm_idlest1_core 29846e130d2SJean Pihetwait_sdrc_ready: 29946e130d2SJean Pihet ldr r5, [r4] 30046e130d2SJean Pihet tst r5, #0x2 30146e130d2SJean Pihet bne wait_sdrc_ready 30246e130d2SJean Pihet /* allow DLL powerdown upon hw idle req */ 30346e130d2SJean Pihet ldr r4, sdrc_power 30446e130d2SJean Pihet ldr r5, [r4] 30546e130d2SJean Pihet bic r5, r5, #0x40 30646e130d2SJean Pihet str r5, [r4] 30746e130d2SJean Pihet 30846e130d2SJean Pihet/* 30946e130d2SJean Pihet * PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a 31046e130d2SJean Pihet * base instead. 31146e130d2SJean Pihet * Be careful not to clobber r7 when maintaing this code. 31246e130d2SJean Pihet */ 31346e130d2SJean Pihet 31446e130d2SJean Pihetis_dll_in_lock_mode: 31546e130d2SJean Pihet /* Is dll in lock mode? */ 31646e130d2SJean Pihet ldr r4, sdrc_dlla_ctrl 31746e130d2SJean Pihet ldr r5, [r4] 31846e130d2SJean Pihet tst r5, #0x4 31946e130d2SJean Pihet bne exit_nonoff_modes @ Return if locked 32046e130d2SJean Pihet /* wait till dll locks */ 32146e130d2SJean Pihet adr r7, kick_counter 32246e130d2SJean Pihetwait_dll_lock_timed: 32346e130d2SJean Pihet ldr r4, wait_dll_lock_counter 32446e130d2SJean Pihet add r4, r4, #1 32546e130d2SJean Pihet str r4, [r7, #wait_dll_lock_counter - kick_counter] 32646e130d2SJean Pihet ldr r4, sdrc_dlla_status 32746e130d2SJean Pihet /* Wait 20uS for lock */ 32846e130d2SJean Pihet mov r6, #8 32946e130d2SJean Pihetwait_dll_lock: 33046e130d2SJean Pihet subs r6, r6, #0x1 33146e130d2SJean Pihet beq kick_dll 33246e130d2SJean Pihet ldr r5, [r4] 33346e130d2SJean Pihet and r5, r5, #0x4 33446e130d2SJean Pihet cmp r5, #0x4 33546e130d2SJean Pihet bne wait_dll_lock 33646e130d2SJean Pihet b exit_nonoff_modes @ Return when locked 33746e130d2SJean Pihet 33846e130d2SJean Pihet /* disable/reenable DLL if not locked */ 33946e130d2SJean Pihetkick_dll: 34046e130d2SJean Pihet ldr r4, sdrc_dlla_ctrl 34146e130d2SJean Pihet ldr r5, [r4] 34246e130d2SJean Pihet mov r6, r5 34346e130d2SJean Pihet bic r6, #(1<<3) @ disable dll 34446e130d2SJean Pihet str r6, [r4] 34546e130d2SJean Pihet dsb 34646e130d2SJean Pihet orr r6, r6, #(1<<3) @ enable dll 34746e130d2SJean Pihet str r6, [r4] 34846e130d2SJean Pihet dsb 34946e130d2SJean Pihet ldr r4, kick_counter 35046e130d2SJean Pihet add r4, r4, #1 35146e130d2SJean Pihet str r4, [r7] @ kick_counter 35246e130d2SJean Pihet b wait_dll_lock_timed 35346e130d2SJean Pihet 35446e130d2SJean Pihetexit_nonoff_modes: 35546e130d2SJean Pihet /* Re-enable C-bit if needed */ 35690625110SSantosh Shilimkar mrc p15, 0, r0, c1, c0, 0 35790625110SSantosh Shilimkar tst r0, #(1 << 2) @ Check C bit enabled? 35890625110SSantosh Shilimkar orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared 35990625110SSantosh Shilimkar mcreq p15, 0, r0, c1, c0, 0 36090625110SSantosh Shilimkar isb 36190625110SSantosh Shilimkar 362f7dfe3d8SJean Pihet/* 363f7dfe3d8SJean Pihet * =================================== 364f7dfe3d8SJean Pihet * == Exit point from non-OFF modes == 365f7dfe3d8SJean Pihet * =================================== 366f7dfe3d8SJean Pihet */ 367857c1b81SRussell King ldmfd sp!, {r4 - r11, pc} @ restore regs and return 368f7dfe3d8SJean Pihet 36946e130d2SJean Pihet/* 37046e130d2SJean Pihet * Local variables 37146e130d2SJean Pihet */ 37246e130d2SJean Pihetsdrc_power: 37346e130d2SJean Pihet .word SDRC_POWER_V 37446e130d2SJean Pihetcm_idlest1_core: 37546e130d2SJean Pihet .word CM_IDLEST1_CORE_V 37646e130d2SJean Pihetcm_idlest_ckgen: 37746e130d2SJean Pihet .word CM_IDLEST_CKGEN_V 37846e130d2SJean Pihetsdrc_dlla_status: 37946e130d2SJean Pihet .word SDRC_DLLA_STATUS_V 38046e130d2SJean Pihetsdrc_dlla_ctrl: 38146e130d2SJean Pihet .word SDRC_DLLA_CTRL_V 38246e130d2SJean Pihet /* 38346e130d2SJean Pihet * When exporting to userspace while the counters are in SRAM, 38446e130d2SJean Pihet * these 2 words need to be at the end to facilitate retrival! 38546e130d2SJean Pihet */ 38646e130d2SJean Pihetkick_counter: 38746e130d2SJean Pihet .word 0 38846e130d2SJean Pihetwait_dll_lock_counter: 38946e130d2SJean Pihet .word 0 39046e130d2SJean Pihet 39146e130d2SJean PihetENTRY(omap3_do_wfi_sz) 39246e130d2SJean Pihet .word . - omap3_do_wfi 39346e130d2SJean Pihet 394f7dfe3d8SJean Pihet 395f7dfe3d8SJean Pihet/* 396f7dfe3d8SJean Pihet * ============================== 397f7dfe3d8SJean Pihet * == Resume path for OFF mode == 398f7dfe3d8SJean Pihet * ============================== 399f7dfe3d8SJean Pihet */ 400f7dfe3d8SJean Pihet 401f7dfe3d8SJean Pihet/* 402f7dfe3d8SJean Pihet * The restore_* functions are called by the ROM code 403f7dfe3d8SJean Pihet * when back from WFI in OFF mode. 404f7dfe3d8SJean Pihet * Cf. the get_*restore_pointer functions. 405f7dfe3d8SJean Pihet * 406f7dfe3d8SJean Pihet * restore_es3: applies to 34xx >= ES3.0 407f7dfe3d8SJean Pihet * restore_3630: applies to 36xx 408f7dfe3d8SJean Pihet * restore: common code for 3xxx 40946e130d2SJean Pihet * 41046e130d2SJean Pihet * Note: when back from CORE and MPU OFF mode we are running 41146e130d2SJean Pihet * from SDRAM, without MMU, without the caches and prediction. 41246e130d2SJean Pihet * Also the SRAM content has been cleared. 413f7dfe3d8SJean Pihet */ 41414c79bbeSKevin HilmanENTRY(omap3_restore_es3) 4150795a75aSTero Kristo ldr r5, pm_prepwstst_core_p 4160795a75aSTero Kristo ldr r4, [r5] 4170795a75aSTero Kristo and r4, r4, #0x3 4180795a75aSTero Kristo cmp r4, #0x0 @ Check if previous power state of CORE is OFF 41946e130d2SJean Pihet bne omap3_restore @ Fall through to OMAP3 common code 4200795a75aSTero Kristo adr r0, es3_sdrc_fix 4210795a75aSTero Kristo ldr r1, sram_base 4220795a75aSTero Kristo ldr r2, es3_sdrc_fix_sz 4230795a75aSTero Kristo mov r2, r2, ror #2 4240795a75aSTero Kristocopy_to_sram: 4250795a75aSTero Kristo ldmia r0!, {r3} @ val = *src 4260795a75aSTero Kristo stmia r1!, {r3} @ *dst = val 4270795a75aSTero Kristo subs r2, r2, #0x1 @ num_words-- 4280795a75aSTero Kristo bne copy_to_sram 4290795a75aSTero Kristo ldr r1, sram_base 4300795a75aSTero Kristo blx r1 43146e130d2SJean Pihet b omap3_restore @ Fall through to OMAP3 common code 43214c79bbeSKevin HilmanENDPROC(omap3_restore_es3) 433458e999eSNishanth Menon 43414c79bbeSKevin HilmanENTRY(omap3_restore_3630) 435458e999eSNishanth Menon ldr r1, pm_prepwstst_core_p 436458e999eSNishanth Menon ldr r2, [r1] 437458e999eSNishanth Menon and r2, r2, #0x3 438458e999eSNishanth Menon cmp r2, #0x0 @ Check if previous power state of CORE is OFF 43946e130d2SJean Pihet bne omap3_restore @ Fall through to OMAP3 common code 440458e999eSNishanth Menon /* Disable RTA before giving control */ 441458e999eSNishanth Menon ldr r1, control_mem_rta 442458e999eSNishanth Menon mov r2, #OMAP36XX_RTA_DISABLE 443458e999eSNishanth Menon str r2, [r1] 44414c79bbeSKevin HilmanENDPROC(omap3_restore_3630) 445f7dfe3d8SJean Pihet 446f7dfe3d8SJean Pihet /* Fall through to common code for the remaining logic */ 447f7dfe3d8SJean Pihet 44814c79bbeSKevin HilmanENTRY(omap3_restore) 449f7dfe3d8SJean Pihet /* 4502637ce30SRussell King * Read the pwstctrl register to check the reason for mpu reset. 4512637ce30SRussell King * This tells us what was lost. 452f7dfe3d8SJean Pihet */ 4538bd22949SKevin Hilman ldr r1, pm_pwstctrl_mpu 4548bd22949SKevin Hilman ldr r2, [r1] 4558bd22949SKevin Hilman and r2, r2, #0x3 4568bd22949SKevin Hilman cmp r2, #0x0 @ Check if target power state was OFF or RET 4578bd22949SKevin Hilman bne logic_l1_restore 458c4236d2eSPeter 'p2' De Schrijver 459c4236d2eSPeter 'p2' De Schrijver ldr r0, l2dis_3630 460c4236d2eSPeter 'p2' De Schrijver cmp r0, #0x1 @ should we disable L2 on 3630? 461c4236d2eSPeter 'p2' De Schrijver bne skipl2dis 462c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r0, c1, c0, 1 463c4236d2eSPeter 'p2' De Schrijver bic r0, r0, #2 @ disable L2 cache 464c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r0, c1, c0, 1 465c4236d2eSPeter 'p2' De Schrijverskipl2dis: 46627d59a4aSTero Kristo ldr r0, control_stat 46727d59a4aSTero Kristo ldr r1, [r0] 46827d59a4aSTero Kristo and r1, #0x700 46927d59a4aSTero Kristo cmp r1, #0x300 47027d59a4aSTero Kristo beq l2_inv_gp 47127d59a4aSTero Kristo mov r0, #40 @ set service ID for PPA 47227d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 47327d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 47427d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 47527d59a4aSTero Kristo mov r6, #0xff 47627d59a4aSTero Kristo adr r3, l2_inv_api_params @ r3 points to dummy parameters 4774444d712SSantosh Shilimkar dsb @ data write barrier 4784444d712SSantosh Shilimkar dmb @ data memory barrier 47976d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 48027d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 48127d59a4aSTero Kristo mov r0, #42 @ set service ID for PPA 48227d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 48327d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 48427d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 48527d59a4aSTero Kristo mov r6, #0xff 486a087cad9STero Kristo ldr r4, scratchpad_base 487a087cad9STero Kristo ldr r3, [r4, #0xBC] @ r3 points to parameters 4884444d712SSantosh Shilimkar dsb @ data write barrier 4894444d712SSantosh Shilimkar dmb @ data memory barrier 49076d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 49127d59a4aSTero Kristo 49279dcfdd4STero Kristo#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 49379dcfdd4STero Kristo /* Restore L2 aux control register */ 49479dcfdd4STero Kristo @ set service ID for PPA 49579dcfdd4STero Kristo mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 49679dcfdd4STero Kristo mov r12, r0 @ copy service ID in r12 49779dcfdd4STero Kristo mov r1, #0 @ set task ID for ROM code in r1 49879dcfdd4STero Kristo mov r2, #4 @ set some flags in r2, r6 49979dcfdd4STero Kristo mov r6, #0xff 50079dcfdd4STero Kristo ldr r4, scratchpad_base 50179dcfdd4STero Kristo ldr r3, [r4, #0xBC] 50279dcfdd4STero Kristo adds r3, r3, #8 @ r3 points to parameters 5034444d712SSantosh Shilimkar dsb @ data write barrier 5044444d712SSantosh Shilimkar dmb @ data memory barrier 50576d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 50679dcfdd4STero Kristo#endif 50727d59a4aSTero Kristo b logic_l1_restore 508bb1c9034SJean Pihet 509dd313947SDave Martin .align 51027d59a4aSTero Kristol2_inv_api_params: 51127d59a4aSTero Kristo .word 0x1, 0x00 51227d59a4aSTero Kristol2_inv_gp: 5138bd22949SKevin Hilman /* Execute smi to invalidate L2 cache */ 514bb1c9034SJean Pihet mov r12, #0x1 @ set up to invalidate L2 51576d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 51627d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 517a087cad9STero Kristo ldr r4, scratchpad_base 518a087cad9STero Kristo ldr r3, [r4,#0xBC] 519a087cad9STero Kristo ldr r0, [r3,#4] 52027d59a4aSTero Kristo mov r12, #0x3 52176d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 52279dcfdd4STero Kristo ldr r4, scratchpad_base 52379dcfdd4STero Kristo ldr r3, [r4,#0xBC] 52479dcfdd4STero Kristo ldr r0, [r3,#12] 52579dcfdd4STero Kristo mov r12, #0x2 52676d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 5278bd22949SKevin Hilmanlogic_l1_restore: 528c4236d2eSPeter 'p2' De Schrijver ldr r1, l2dis_3630 529bb1c9034SJean Pihet cmp r1, #0x1 @ Test if L2 re-enable needed on 3630 530c4236d2eSPeter 'p2' De Schrijver bne skipl2reen 531c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r1, c1, c0, 1 532c4236d2eSPeter 'p2' De Schrijver orr r1, r1, #2 @ re-enable L2 cache 533c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r1, c1, c0, 1 534c4236d2eSPeter 'p2' De Schrijverskipl2reen: 5358bd22949SKevin Hilman 536076f2cc4SRussell King /* Now branch to the common CPU resume function */ 537076f2cc4SRussell King b cpu_resume 53814c79bbeSKevin HilmanENDPROC(omap3_restore) 53946f557cbSSantosh Shilimkar 540076f2cc4SRussell King .ltorg 5411e81bc01SJean Pihet 5421e81bc01SJean Pihet/* 54346e130d2SJean Pihet * Local variables 54446e130d2SJean Pihet */ 54546e130d2SJean Pihetpm_prepwstst_core_p: 54646e130d2SJean Pihet .word PM_PREPWSTST_CORE_P 54746e130d2SJean Pihetpm_pwstctrl_mpu: 54846e130d2SJean Pihet .word PM_PWSTCTRL_MPU_P 54946e130d2SJean Pihetscratchpad_base: 55046e130d2SJean Pihet .word SCRATCHPAD_BASE_P 55146e130d2SJean Pihetsram_base: 55246e130d2SJean Pihet .word SRAM_BASE_P + 0x8000 55346e130d2SJean Pihetcontrol_stat: 55446e130d2SJean Pihet .word CONTROL_STAT 55546e130d2SJean Pihetcontrol_mem_rta: 55646e130d2SJean Pihet .word CONTROL_MEM_RTA_CTRL 55746e130d2SJean Pihetl2dis_3630: 55846e130d2SJean Pihet .word 0 55946e130d2SJean Pihet 56046e130d2SJean Pihet/* 5611e81bc01SJean Pihet * Internal functions 5621e81bc01SJean Pihet */ 5631e81bc01SJean Pihet 56446e130d2SJean Pihet/* 56546e130d2SJean Pihet * This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 56646e130d2SJean Pihet * Copied to and run from SRAM in order to reconfigure the SDRC parameters. 56746e130d2SJean Pihet */ 5681e81bc01SJean Pihet .text 569dd313947SDave Martin .align 3 5701e81bc01SJean PihetENTRY(es3_sdrc_fix) 5711e81bc01SJean Pihet ldr r4, sdrc_syscfg @ get config addr 5721e81bc01SJean Pihet ldr r5, [r4] @ get value 5731e81bc01SJean Pihet tst r5, #0x100 @ is part access blocked 5741e81bc01SJean Pihet it eq 5751e81bc01SJean Pihet biceq r5, r5, #0x100 @ clear bit if set 5761e81bc01SJean Pihet str r5, [r4] @ write back change 5771e81bc01SJean Pihet ldr r4, sdrc_mr_0 @ get config addr 5781e81bc01SJean Pihet ldr r5, [r4] @ get value 5791e81bc01SJean Pihet str r5, [r4] @ write back change 5801e81bc01SJean Pihet ldr r4, sdrc_emr2_0 @ get config addr 5811e81bc01SJean Pihet ldr r5, [r4] @ get value 5821e81bc01SJean Pihet str r5, [r4] @ write back change 5831e81bc01SJean Pihet ldr r4, sdrc_manual_0 @ get config addr 5841e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 5851e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 5861e81bc01SJean Pihet ldr r4, sdrc_mr_1 @ get config addr 5871e81bc01SJean Pihet ldr r5, [r4] @ get value 5881e81bc01SJean Pihet str r5, [r4] @ write back change 5891e81bc01SJean Pihet ldr r4, sdrc_emr2_1 @ get config addr 5901e81bc01SJean Pihet ldr r5, [r4] @ get value 5911e81bc01SJean Pihet str r5, [r4] @ write back change 5921e81bc01SJean Pihet ldr r4, sdrc_manual_1 @ get config addr 5931e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 5941e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 5951e81bc01SJean Pihet bx lr 5961e81bc01SJean Pihet 59746e130d2SJean Pihet/* 59846e130d2SJean Pihet * Local variables 59946e130d2SJean Pihet */ 600dd313947SDave Martin .align 6011e81bc01SJean Pihetsdrc_syscfg: 6021e81bc01SJean Pihet .word SDRC_SYSCONFIG_P 6031e81bc01SJean Pihetsdrc_mr_0: 6041e81bc01SJean Pihet .word SDRC_MR_0_P 6051e81bc01SJean Pihetsdrc_emr2_0: 6061e81bc01SJean Pihet .word SDRC_EMR2_0_P 6071e81bc01SJean Pihetsdrc_manual_0: 6081e81bc01SJean Pihet .word SDRC_MANUAL_0_P 6091e81bc01SJean Pihetsdrc_mr_1: 6101e81bc01SJean Pihet .word SDRC_MR_1_P 6111e81bc01SJean Pihetsdrc_emr2_1: 6121e81bc01SJean Pihet .word SDRC_EMR2_1_P 6131e81bc01SJean Pihetsdrc_manual_1: 6141e81bc01SJean Pihet .word SDRC_MANUAL_1_P 615dd313947SDave MartinENDPROC(es3_sdrc_fix) 6161e81bc01SJean PihetENTRY(es3_sdrc_fix_sz) 6171e81bc01SJean Pihet .word . - es3_sdrc_fix 618