18bd22949SKevin Hilman/* 28bd22949SKevin Hilman * (C) Copyright 2007 38bd22949SKevin Hilman * Texas Instruments 48bd22949SKevin Hilman * Karthik Dasu <karthik-dp@ti.com> 58bd22949SKevin Hilman * 68bd22949SKevin Hilman * (C) Copyright 2004 78bd22949SKevin Hilman * Texas Instruments, <www.ti.com> 88bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 98bd22949SKevin Hilman * 108bd22949SKevin Hilman * This program is free software; you can redistribute it and/or 118bd22949SKevin Hilman * modify it under the terms of the GNU General Public License as 128bd22949SKevin Hilman * published by the Free Software Foundation; either version 2 of 138bd22949SKevin Hilman * the License, or (at your option) any later version. 148bd22949SKevin Hilman * 158bd22949SKevin Hilman * This program is distributed in the hope that it will be useful, 168bd22949SKevin Hilman * but WITHOUT ANY WARRANTY; without even the implied warranty of 178bd22949SKevin Hilman * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 188bd22949SKevin Hilman * GNU General Public License for more details. 198bd22949SKevin Hilman * 208bd22949SKevin Hilman * You should have received a copy of the GNU General Public License 218bd22949SKevin Hilman * along with this program; if not, write to the Free Software 228bd22949SKevin Hilman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 238bd22949SKevin Hilman * MA 02111-1307 USA 248bd22949SKevin Hilman */ 258bd22949SKevin Hilman#include <linux/linkage.h> 268bd22949SKevin Hilman#include <asm/assembler.h> 27b4b36fd9SJean Pihet#include <plat/sram.h> 288bd22949SKevin Hilman#include <mach/io.h> 298bd22949SKevin Hilman 3059fb659bSPaul Walmsley#include "cm2xxx_3xxx.h" 3159fb659bSPaul Walmsley#include "prm2xxx_3xxx.h" 328bd22949SKevin Hilman#include "sdrc.h" 334814ced5SPaul Walmsley#include "control.h" 348bd22949SKevin Hilman 35fe360e1cSJean Pihet/* 36fe360e1cSJean Pihet * Registers access definitions 37fe360e1cSJean Pihet */ 38fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_OFFS 0xc 39fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ 40fe360e1cSJean Pihet (SDRC_SCRATCHPAD_SEM_OFFS) 41fe360e1cSJean Pihet#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ 42fe360e1cSJean Pihet OMAP3430_PM_PREPWSTST 4337903009SAbhijit Pagare#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL 4489139dceSPeter 'p2' De Schrijver#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) 459d93b8a2SPeter 'p2' De Schrijver#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) 46fe360e1cSJean Pihet#define SRAM_BASE_P OMAP3_SRAM_PA 47fe360e1cSJean Pihet#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS 48fe360e1cSJean Pihet#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ 49fe360e1cSJean Pihet OMAP36XX_CONTROL_MEM_RTA_CTRL) 50fe360e1cSJean Pihet 51fe360e1cSJean Pihet/* Move this as correct place is available */ 52fe360e1cSJean Pihet#define SCRATCHPAD_MEM_OFFS 0x310 53fe360e1cSJean Pihet#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ 54fe360e1cSJean Pihet OMAP343X_CONTROL_MEM_WKUP +\ 55fe360e1cSJean Pihet SCRATCHPAD_MEM_OFFS) 568bd22949SKevin Hilman#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 570795a75aSTero Kristo#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) 580795a75aSTero Kristo#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) 590795a75aSTero Kristo#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) 600795a75aSTero Kristo#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) 610795a75aSTero Kristo#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) 620795a75aSTero Kristo#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) 630795a75aSTero Kristo#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) 6489139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 6589139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 668bd22949SKevin Hilman 67dd313947SDave Martin/* 68dd313947SDave Martin * This file needs be built unconditionally as ARM to interoperate correctly 69dd313947SDave Martin * with non-Thumb-2-capable firmware. 70dd313947SDave Martin */ 71dd313947SDave Martin .arm 72a89b6f00SRajendra Nayak 73d3cdfd2aSJean Pihet/* 74d3cdfd2aSJean Pihet * API functions 75d3cdfd2aSJean Pihet */ 76a89b6f00SRajendra Nayak 77f7dfe3d8SJean Pihet/* 78f7dfe3d8SJean Pihet * The "get_*restore_pointer" functions are used to provide a 79f7dfe3d8SJean Pihet * physical restore address where the ROM code jumps while waking 80f7dfe3d8SJean Pihet * up from MPU OFF/OSWR state. 81f7dfe3d8SJean Pihet * The restore pointer is stored into the scratchpad. 82f7dfe3d8SJean Pihet */ 83f7dfe3d8SJean Pihet 84a89b6f00SRajendra Nayak .text 858bd22949SKevin Hilman/* Function call to get the restore pointer for resume from OFF */ 868bd22949SKevin HilmanENTRY(get_restore_pointer) 878bd22949SKevin Hilman stmfd sp!, {lr} @ save registers on stack 888bd22949SKevin Hilman adr r0, restore 898bd22949SKevin Hilman ldmfd sp!, {pc} @ restore regs and return 90dd313947SDave MartinENDPROC(get_restore_pointer) 91dd313947SDave Martin .align 928bd22949SKevin HilmanENTRY(get_restore_pointer_sz) 930795a75aSTero Kristo .word . - get_restore_pointer 941e81bc01SJean Pihet 95458e999eSNishanth Menon .text 96458e999eSNishanth Menon/* Function call to get the restore pointer for 3630 resume from OFF */ 97458e999eSNishanth MenonENTRY(get_omap3630_restore_pointer) 98458e999eSNishanth Menon stmfd sp!, {lr} @ save registers on stack 99458e999eSNishanth Menon adr r0, restore_3630 100458e999eSNishanth Menon ldmfd sp!, {pc} @ restore regs and return 101dd313947SDave MartinENDPROC(get_omap3630_restore_pointer) 102dd313947SDave Martin .align 103458e999eSNishanth MenonENTRY(get_omap3630_restore_pointer_sz) 104458e999eSNishanth Menon .word . - get_omap3630_restore_pointer 1050795a75aSTero Kristo 1060795a75aSTero Kristo .text 1071e81bc01SJean Pihet/* Function call to get the restore pointer for ES3 to resume from OFF */ 1081e81bc01SJean PihetENTRY(get_es3_restore_pointer) 1091e81bc01SJean Pihet stmfd sp!, {lr} @ save registers on stack 1101e81bc01SJean Pihet adr r0, restore_es3 1111e81bc01SJean Pihet ldmfd sp!, {pc} @ restore regs and return 112dd313947SDave MartinENDPROC(get_es3_restore_pointer) 113dd313947SDave Martin .align 1141e81bc01SJean PihetENTRY(get_es3_restore_pointer_sz) 1151e81bc01SJean Pihet .word . - get_es3_restore_pointer 1161e81bc01SJean Pihet 1171e81bc01SJean Pihet .text 118c4236d2eSPeter 'p2' De Schrijver/* 119c4236d2eSPeter 'p2' De Schrijver * L2 cache needs to be toggled for stable OFF mode functionality on 3630. 1201e81bc01SJean Pihet * This function sets up a flag that will allow for this toggling to take 121f7dfe3d8SJean Pihet * place on 3630. Hopefully some version in the future may not need this. 122c4236d2eSPeter 'p2' De Schrijver */ 123c4236d2eSPeter 'p2' De SchrijverENTRY(enable_omap3630_toggle_l2_on_restore) 124c4236d2eSPeter 'p2' De Schrijver stmfd sp!, {lr} @ save registers on stack 125c4236d2eSPeter 'p2' De Schrijver /* Setup so that we will disable and enable l2 */ 126c4236d2eSPeter 'p2' De Schrijver mov r1, #0x1 127dd313947SDave Martin adrl r2, l2dis_3630 @ may be too distant for plain adr 128dd313947SDave Martin str r1, [r2] 129c4236d2eSPeter 'p2' De Schrijver ldmfd sp!, {pc} @ restore regs and return 130dd313947SDave MartinENDPROC(enable_omap3630_toggle_l2_on_restore) 131c4236d2eSPeter 'p2' De Schrijver 132bb1c9034SJean Pihet .text 13327d59a4aSTero Kristo/* Function to call rom code to save secure ram context */ 134b6338bdcSJean Pihet .align 3 13527d59a4aSTero KristoENTRY(save_secure_ram_context) 136857c1b81SRussell King stmfd sp!, {r4 - r11, lr} @ save registers on stack 13727d59a4aSTero Kristo adr r3, api_params @ r3 points to parameters 13827d59a4aSTero Kristo str r0, [r3,#0x4] @ r0 has sdram address 13927d59a4aSTero Kristo ldr r12, high_mask 14027d59a4aSTero Kristo and r3, r3, r12 14127d59a4aSTero Kristo ldr r12, sram_phy_addr_mask 14227d59a4aSTero Kristo orr r3, r3, r12 14327d59a4aSTero Kristo mov r0, #25 @ set service ID for PPA 14427d59a4aSTero Kristo mov r12, r0 @ copy secure service ID in r12 14527d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 146ba50ea7eSKalle Jokiniemi mov r2, #4 @ set some flags in r2, r6 14727d59a4aSTero Kristo mov r6, #0xff 1484444d712SSantosh Shilimkar dsb @ data write barrier 1494444d712SSantosh Shilimkar dmb @ data memory barrier 15076d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 15127d59a4aSTero Kristo nop 15227d59a4aSTero Kristo nop 15327d59a4aSTero Kristo nop 15427d59a4aSTero Kristo nop 155857c1b81SRussell King ldmfd sp!, {r4 - r11, pc} 156dd313947SDave Martin .align 15727d59a4aSTero Kristosram_phy_addr_mask: 15827d59a4aSTero Kristo .word SRAM_BASE_P 15927d59a4aSTero Kristohigh_mask: 16027d59a4aSTero Kristo .word 0xffff 16127d59a4aSTero Kristoapi_params: 16227d59a4aSTero Kristo .word 0x4, 0x0, 0x0, 0x1, 0x1 163dd313947SDave MartinENDPROC(save_secure_ram_context) 16427d59a4aSTero KristoENTRY(save_secure_ram_context_sz) 16527d59a4aSTero Kristo .word . - save_secure_ram_context 16627d59a4aSTero Kristo 1678bd22949SKevin Hilman/* 168f7dfe3d8SJean Pihet * ====================== 169f7dfe3d8SJean Pihet * == Idle entry point == 170f7dfe3d8SJean Pihet * ====================== 171f7dfe3d8SJean Pihet */ 172f7dfe3d8SJean Pihet 173f7dfe3d8SJean Pihet/* 1748bd22949SKevin Hilman * Forces OMAP into idle state 1758bd22949SKevin Hilman * 176f7dfe3d8SJean Pihet * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed 177f7dfe3d8SJean Pihet * and executes the WFI instruction. Calling WFI effectively changes the 178f7dfe3d8SJean Pihet * power domains states to the desired target power states. 1798bd22949SKevin Hilman * 180f7dfe3d8SJean Pihet * 181f7dfe3d8SJean Pihet * Notes: 182bb1c9034SJean Pihet * - this code gets copied to internal SRAM at boot and after wake-up 183bb1c9034SJean Pihet * from OFF mode. The execution pointer in SRAM is _omap_sram_idle. 184f7dfe3d8SJean Pihet * - when the OMAP wakes up it continues at different execution points 185f7dfe3d8SJean Pihet * depending on the low power mode (non-OFF vs OFF modes), 186f7dfe3d8SJean Pihet * cf. 'Resume path for xxx mode' comments. 1878bd22949SKevin Hilman */ 188b6338bdcSJean Pihet .align 3 1898bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend) 190857c1b81SRussell King stmfd sp!, {r4 - r11, lr} @ save registers on stack 191d3cdfd2aSJean Pihet 192f7dfe3d8SJean Pihet /* 193c9749a35SSantosh Shilimkar * r0 contains CPU context save/restore pointer in sdram 194f7dfe3d8SJean Pihet * r1 contains information about saving context: 195f7dfe3d8SJean Pihet * 0 - No context lost 196f7dfe3d8SJean Pihet * 1 - Only L1 and logic lost 197c9749a35SSantosh Shilimkar * 2 - Only L2 lost (Even L1 is retained we clean it along with L2) 198c9749a35SSantosh Shilimkar * 3 - Both L1 and L2 lost and logic lost 199f7dfe3d8SJean Pihet */ 200f7dfe3d8SJean Pihet 201f7dfe3d8SJean Pihet /* Directly jump to WFI is the context save is not required */ 202f7dfe3d8SJean Pihet cmp r1, #0x0 203f7dfe3d8SJean Pihet beq omap3_do_wfi 204f7dfe3d8SJean Pihet 205f7dfe3d8SJean Pihet /* Otherwise fall through to the save context code */ 206f7dfe3d8SJean Pihetsave_context_wfi: 207f7dfe3d8SJean Pihet mov r8, r0 @ Store SDRAM address in r8 208f7dfe3d8SJean Pihet mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register 209f7dfe3d8SJean Pihet mov r4, #0x1 @ Number of parameters for restore call 210f7dfe3d8SJean Pihet stmia r8!, {r4-r5} @ Push parameters for restore call 211f7dfe3d8SJean Pihet mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register 212f7dfe3d8SJean Pihet stmia r8!, {r4-r5} @ Push parameters for restore call 213f7dfe3d8SJean Pihet 214f7dfe3d8SJean Pihet /* 215f7dfe3d8SJean Pihet * jump out to kernel flush routine 216f7dfe3d8SJean Pihet * - reuse that code is better 217f7dfe3d8SJean Pihet * - it executes in a cached space so is faster than refetch per-block 218f7dfe3d8SJean Pihet * - should be faster and will change with kernel 219f7dfe3d8SJean Pihet * - 'might' have to copy address, load and jump to it 22090625110SSantosh Shilimkar * Flush all data from the L1 data cache before disabling 22190625110SSantosh Shilimkar * SCTLR.C bit. 222f7dfe3d8SJean Pihet */ 223f7dfe3d8SJean Pihet ldr r1, kernel_flush 224f7dfe3d8SJean Pihet mov lr, pc 225f7dfe3d8SJean Pihet bx r1 226f7dfe3d8SJean Pihet 22790625110SSantosh Shilimkar /* 22890625110SSantosh Shilimkar * Clear the SCTLR.C bit to prevent further data cache 22990625110SSantosh Shilimkar * allocation. Clearing SCTLR.C would make all the data accesses 23090625110SSantosh Shilimkar * strongly ordered and would not hit the cache. 23190625110SSantosh Shilimkar */ 23290625110SSantosh Shilimkar mrc p15, 0, r0, c1, c0, 0 23390625110SSantosh Shilimkar bic r0, r0, #(1 << 2) @ Disable the C bit 23490625110SSantosh Shilimkar mcr p15, 0, r0, c1, c0, 0 23590625110SSantosh Shilimkar isb 23690625110SSantosh Shilimkar 23790625110SSantosh Shilimkar /* 23890625110SSantosh Shilimkar * Invalidate L1 data cache. Even though only invalidate is 23990625110SSantosh Shilimkar * necessary exported flush API is used here. Doing clean 24090625110SSantosh Shilimkar * on already clean cache would be almost NOP. 241f7dfe3d8SJean Pihet */ 242f7dfe3d8SJean Pihet ldr r1, kernel_flush 243dd313947SDave Martin blx r1 244dd313947SDave Martin /* 245dd313947SDave Martin * The kernel doesn't interwork: v7_flush_dcache_all in particluar will 246dd313947SDave Martin * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. 247dd313947SDave Martin * This sequence switches back to ARM. Note that .align may insert a 248dd313947SDave Martin * nop: bx pc needs to be word-aligned in order to work. 249dd313947SDave Martin */ 250dd313947SDave Martin THUMB( .thumb ) 251dd313947SDave Martin THUMB( .align ) 252dd313947SDave Martin THUMB( bx pc ) 253dd313947SDave Martin THUMB( nop ) 254dd313947SDave Martin .arm 255f7dfe3d8SJean Pihet 256f7dfe3d8SJean Pihetomap3_do_wfi: 2578bd22949SKevin Hilman ldr r4, sdrc_power @ read the SDRC_POWER register 2588bd22949SKevin Hilman ldr r5, [r4] @ read the contents of SDRC_POWER 2598bd22949SKevin Hilman orr r5, r5, #0x40 @ enable self refresh on idle req 2608bd22949SKevin Hilman str r5, [r4] @ write back to SDRC_POWER register 2618bd22949SKevin Hilman 2628bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 2634444d712SSantosh Shilimkar dsb 2644444d712SSantosh Shilimkar dmb 2658bd22949SKevin Hilman 266f7dfe3d8SJean Pihet/* 267f7dfe3d8SJean Pihet * =================================== 268f7dfe3d8SJean Pihet * == WFI instruction => Enter idle == 269f7dfe3d8SJean Pihet * =================================== 270f7dfe3d8SJean Pihet */ 2718bd22949SKevin Hilman wfi @ wait for interrupt 2728bd22949SKevin Hilman 273f7dfe3d8SJean Pihet/* 274f7dfe3d8SJean Pihet * =================================== 275f7dfe3d8SJean Pihet * == Resume path for non-OFF modes == 276f7dfe3d8SJean Pihet * =================================== 277f7dfe3d8SJean Pihet */ 2788bd22949SKevin Hilman nop 2798bd22949SKevin Hilman nop 2808bd22949SKevin Hilman nop 2818bd22949SKevin Hilman nop 2828bd22949SKevin Hilman nop 2838bd22949SKevin Hilman nop 2848bd22949SKevin Hilman nop 2858bd22949SKevin Hilman nop 2868bd22949SKevin Hilman nop 2878bd22949SKevin Hilman nop 28889139dceSPeter 'p2' De Schrijver bl wait_sdrc_ok 2898bd22949SKevin Hilman 29090625110SSantosh Shilimkar mrc p15, 0, r0, c1, c0, 0 29190625110SSantosh Shilimkar tst r0, #(1 << 2) @ Check C bit enabled? 29290625110SSantosh Shilimkar orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared 29390625110SSantosh Shilimkar mcreq p15, 0, r0, c1, c0, 0 29490625110SSantosh Shilimkar isb 29590625110SSantosh Shilimkar 296f7dfe3d8SJean Pihet/* 297f7dfe3d8SJean Pihet * =================================== 298f7dfe3d8SJean Pihet * == Exit point from non-OFF modes == 299f7dfe3d8SJean Pihet * =================================== 300f7dfe3d8SJean Pihet */ 301857c1b81SRussell King ldmfd sp!, {r4 - r11, pc} @ restore regs and return 302f7dfe3d8SJean Pihet 303f7dfe3d8SJean Pihet 304f7dfe3d8SJean Pihet/* 305f7dfe3d8SJean Pihet * ============================== 306f7dfe3d8SJean Pihet * == Resume path for OFF mode == 307f7dfe3d8SJean Pihet * ============================== 308f7dfe3d8SJean Pihet */ 309f7dfe3d8SJean Pihet 310f7dfe3d8SJean Pihet/* 311f7dfe3d8SJean Pihet * The restore_* functions are called by the ROM code 312f7dfe3d8SJean Pihet * when back from WFI in OFF mode. 313f7dfe3d8SJean Pihet * Cf. the get_*restore_pointer functions. 314f7dfe3d8SJean Pihet * 315f7dfe3d8SJean Pihet * restore_es3: applies to 34xx >= ES3.0 316f7dfe3d8SJean Pihet * restore_3630: applies to 36xx 317f7dfe3d8SJean Pihet * restore: common code for 3xxx 318f7dfe3d8SJean Pihet */ 3190795a75aSTero Kristorestore_es3: 3200795a75aSTero Kristo ldr r5, pm_prepwstst_core_p 3210795a75aSTero Kristo ldr r4, [r5] 3220795a75aSTero Kristo and r4, r4, #0x3 3230795a75aSTero Kristo cmp r4, #0x0 @ Check if previous power state of CORE is OFF 3240795a75aSTero Kristo bne restore 3250795a75aSTero Kristo adr r0, es3_sdrc_fix 3260795a75aSTero Kristo ldr r1, sram_base 3270795a75aSTero Kristo ldr r2, es3_sdrc_fix_sz 3280795a75aSTero Kristo mov r2, r2, ror #2 3290795a75aSTero Kristocopy_to_sram: 3300795a75aSTero Kristo ldmia r0!, {r3} @ val = *src 3310795a75aSTero Kristo stmia r1!, {r3} @ *dst = val 3320795a75aSTero Kristo subs r2, r2, #0x1 @ num_words-- 3330795a75aSTero Kristo bne copy_to_sram 3340795a75aSTero Kristo ldr r1, sram_base 3350795a75aSTero Kristo blx r1 336458e999eSNishanth Menon b restore 337458e999eSNishanth Menon 338458e999eSNishanth Menonrestore_3630: 339458e999eSNishanth Menon ldr r1, pm_prepwstst_core_p 340458e999eSNishanth Menon ldr r2, [r1] 341458e999eSNishanth Menon and r2, r2, #0x3 342458e999eSNishanth Menon cmp r2, #0x0 @ Check if previous power state of CORE is OFF 343458e999eSNishanth Menon bne restore 344458e999eSNishanth Menon /* Disable RTA before giving control */ 345458e999eSNishanth Menon ldr r1, control_mem_rta 346458e999eSNishanth Menon mov r2, #OMAP36XX_RTA_DISABLE 347458e999eSNishanth Menon str r2, [r1] 348f7dfe3d8SJean Pihet 349f7dfe3d8SJean Pihet /* Fall through to common code for the remaining logic */ 350f7dfe3d8SJean Pihet 3518bd22949SKevin Hilmanrestore: 352f7dfe3d8SJean Pihet /* 3532637ce30SRussell King * Read the pwstctrl register to check the reason for mpu reset. 3542637ce30SRussell King * This tells us what was lost. 355f7dfe3d8SJean Pihet */ 3568bd22949SKevin Hilman ldr r1, pm_pwstctrl_mpu 3578bd22949SKevin Hilman ldr r2, [r1] 3588bd22949SKevin Hilman and r2, r2, #0x3 3598bd22949SKevin Hilman cmp r2, #0x0 @ Check if target power state was OFF or RET 3608bd22949SKevin Hilman bne logic_l1_restore 361c4236d2eSPeter 'p2' De Schrijver 362c4236d2eSPeter 'p2' De Schrijver ldr r0, l2dis_3630 363c4236d2eSPeter 'p2' De Schrijver cmp r0, #0x1 @ should we disable L2 on 3630? 364c4236d2eSPeter 'p2' De Schrijver bne skipl2dis 365c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r0, c1, c0, 1 366c4236d2eSPeter 'p2' De Schrijver bic r0, r0, #2 @ disable L2 cache 367c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r0, c1, c0, 1 368c4236d2eSPeter 'p2' De Schrijverskipl2dis: 36927d59a4aSTero Kristo ldr r0, control_stat 37027d59a4aSTero Kristo ldr r1, [r0] 37127d59a4aSTero Kristo and r1, #0x700 37227d59a4aSTero Kristo cmp r1, #0x300 37327d59a4aSTero Kristo beq l2_inv_gp 37427d59a4aSTero Kristo mov r0, #40 @ set service ID for PPA 37527d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 37627d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 37727d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 37827d59a4aSTero Kristo mov r6, #0xff 37927d59a4aSTero Kristo adr r3, l2_inv_api_params @ r3 points to dummy parameters 3804444d712SSantosh Shilimkar dsb @ data write barrier 3814444d712SSantosh Shilimkar dmb @ data memory barrier 38276d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 38327d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 38427d59a4aSTero Kristo mov r0, #42 @ set service ID for PPA 38527d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 38627d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 38727d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 38827d59a4aSTero Kristo mov r6, #0xff 389a087cad9STero Kristo ldr r4, scratchpad_base 390a087cad9STero Kristo ldr r3, [r4, #0xBC] @ r3 points to parameters 3914444d712SSantosh Shilimkar dsb @ data write barrier 3924444d712SSantosh Shilimkar dmb @ data memory barrier 39376d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 39427d59a4aSTero Kristo 39579dcfdd4STero Kristo#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 39679dcfdd4STero Kristo /* Restore L2 aux control register */ 39779dcfdd4STero Kristo @ set service ID for PPA 39879dcfdd4STero Kristo mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 39979dcfdd4STero Kristo mov r12, r0 @ copy service ID in r12 40079dcfdd4STero Kristo mov r1, #0 @ set task ID for ROM code in r1 40179dcfdd4STero Kristo mov r2, #4 @ set some flags in r2, r6 40279dcfdd4STero Kristo mov r6, #0xff 40379dcfdd4STero Kristo ldr r4, scratchpad_base 40479dcfdd4STero Kristo ldr r3, [r4, #0xBC] 40579dcfdd4STero Kristo adds r3, r3, #8 @ r3 points to parameters 4064444d712SSantosh Shilimkar dsb @ data write barrier 4074444d712SSantosh Shilimkar dmb @ data memory barrier 40876d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 40979dcfdd4STero Kristo#endif 41027d59a4aSTero Kristo b logic_l1_restore 411bb1c9034SJean Pihet 412dd313947SDave Martin .align 41327d59a4aSTero Kristol2_inv_api_params: 41427d59a4aSTero Kristo .word 0x1, 0x00 41527d59a4aSTero Kristol2_inv_gp: 4168bd22949SKevin Hilman /* Execute smi to invalidate L2 cache */ 417bb1c9034SJean Pihet mov r12, #0x1 @ set up to invalidate L2 41876d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 41927d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 420a087cad9STero Kristo ldr r4, scratchpad_base 421a087cad9STero Kristo ldr r3, [r4,#0xBC] 422a087cad9STero Kristo ldr r0, [r3,#4] 42327d59a4aSTero Kristo mov r12, #0x3 42476d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 42579dcfdd4STero Kristo ldr r4, scratchpad_base 42679dcfdd4STero Kristo ldr r3, [r4,#0xBC] 42779dcfdd4STero Kristo ldr r0, [r3,#12] 42879dcfdd4STero Kristo mov r12, #0x2 42976d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 4308bd22949SKevin Hilmanlogic_l1_restore: 431c4236d2eSPeter 'p2' De Schrijver ldr r1, l2dis_3630 432bb1c9034SJean Pihet cmp r1, #0x1 @ Test if L2 re-enable needed on 3630 433c4236d2eSPeter 'p2' De Schrijver bne skipl2reen 434c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r1, c1, c0, 1 435c4236d2eSPeter 'p2' De Schrijver orr r1, r1, #2 @ re-enable L2 cache 436c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r1, c1, c0, 1 437c4236d2eSPeter 'p2' De Schrijverskipl2reen: 4388bd22949SKevin Hilman 439*076f2cc4SRussell King /* Now branch to the common CPU resume function */ 440*076f2cc4SRussell King b cpu_resume 44146f557cbSSantosh Shilimkar 442*076f2cc4SRussell King .ltorg 4431e81bc01SJean Pihet 4441e81bc01SJean Pihet/* 4451e81bc01SJean Pihet * Internal functions 4461e81bc01SJean Pihet */ 4471e81bc01SJean Pihet 44883521291SJean Pihet/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */ 4491e81bc01SJean Pihet .text 450dd313947SDave Martin .align 3 4511e81bc01SJean PihetENTRY(es3_sdrc_fix) 4521e81bc01SJean Pihet ldr r4, sdrc_syscfg @ get config addr 4531e81bc01SJean Pihet ldr r5, [r4] @ get value 4541e81bc01SJean Pihet tst r5, #0x100 @ is part access blocked 4551e81bc01SJean Pihet it eq 4561e81bc01SJean Pihet biceq r5, r5, #0x100 @ clear bit if set 4571e81bc01SJean Pihet str r5, [r4] @ write back change 4581e81bc01SJean Pihet ldr r4, sdrc_mr_0 @ get config addr 4591e81bc01SJean Pihet ldr r5, [r4] @ get value 4601e81bc01SJean Pihet str r5, [r4] @ write back change 4611e81bc01SJean Pihet ldr r4, sdrc_emr2_0 @ get config addr 4621e81bc01SJean Pihet ldr r5, [r4] @ get value 4631e81bc01SJean Pihet str r5, [r4] @ write back change 4641e81bc01SJean Pihet ldr r4, sdrc_manual_0 @ get config addr 4651e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 4661e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 4671e81bc01SJean Pihet ldr r4, sdrc_mr_1 @ get config addr 4681e81bc01SJean Pihet ldr r5, [r4] @ get value 4691e81bc01SJean Pihet str r5, [r4] @ write back change 4701e81bc01SJean Pihet ldr r4, sdrc_emr2_1 @ get config addr 4711e81bc01SJean Pihet ldr r5, [r4] @ get value 4721e81bc01SJean Pihet str r5, [r4] @ write back change 4731e81bc01SJean Pihet ldr r4, sdrc_manual_1 @ get config addr 4741e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 4751e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 4761e81bc01SJean Pihet bx lr 4771e81bc01SJean Pihet 478dd313947SDave Martin .align 4791e81bc01SJean Pihetsdrc_syscfg: 4801e81bc01SJean Pihet .word SDRC_SYSCONFIG_P 4811e81bc01SJean Pihetsdrc_mr_0: 4821e81bc01SJean Pihet .word SDRC_MR_0_P 4831e81bc01SJean Pihetsdrc_emr2_0: 4841e81bc01SJean Pihet .word SDRC_EMR2_0_P 4851e81bc01SJean Pihetsdrc_manual_0: 4861e81bc01SJean Pihet .word SDRC_MANUAL_0_P 4871e81bc01SJean Pihetsdrc_mr_1: 4881e81bc01SJean Pihet .word SDRC_MR_1_P 4891e81bc01SJean Pihetsdrc_emr2_1: 4901e81bc01SJean Pihet .word SDRC_EMR2_1_P 4911e81bc01SJean Pihetsdrc_manual_1: 4921e81bc01SJean Pihet .word SDRC_MANUAL_1_P 493dd313947SDave MartinENDPROC(es3_sdrc_fix) 4941e81bc01SJean PihetENTRY(es3_sdrc_fix_sz) 4951e81bc01SJean Pihet .word . - es3_sdrc_fix 4961e81bc01SJean Pihet 49783521291SJean Pihet/* 49883521291SJean Pihet * This function implements the erratum ID i581 WA: 49983521291SJean Pihet * SDRC state restore before accessing the SDRAM 50083521291SJean Pihet * 50183521291SJean Pihet * Only used at return from non-OFF mode. For OFF 50283521291SJean Pihet * mode the ROM code configures the SDRC and 50383521291SJean Pihet * the DPLL before calling the restore code directly 50483521291SJean Pihet * from DDR. 50583521291SJean Pihet */ 50683521291SJean Pihet 50789139dceSPeter 'p2' De Schrijver/* Make sure SDRC accesses are ok */ 50889139dceSPeter 'p2' De Schrijverwait_sdrc_ok: 5099d93b8a2SPeter 'p2' De Schrijver 510bb1c9034SJean Pihet/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */ 5119d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest_ckgen 5129d93b8a2SPeter 'p2' De Schrijverwait_dpll3_lock: 51389139dceSPeter 'p2' De Schrijver ldr r5, [r4] 5149d93b8a2SPeter 'p2' De Schrijver tst r5, #1 5159d93b8a2SPeter 'p2' De Schrijver beq wait_dpll3_lock 5169d93b8a2SPeter 'p2' De Schrijver 5179d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest1_core 5189d93b8a2SPeter 'p2' De Schrijverwait_sdrc_ready: 5199d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 5209d93b8a2SPeter 'p2' De Schrijver tst r5, #0x2 5219d93b8a2SPeter 'p2' De Schrijver bne wait_sdrc_ready 5229d93b8a2SPeter 'p2' De Schrijver /* allow DLL powerdown upon hw idle req */ 5238bd22949SKevin Hilman ldr r4, sdrc_power 5248bd22949SKevin Hilman ldr r5, [r4] 5258bd22949SKevin Hilman bic r5, r5, #0x40 5268bd22949SKevin Hilman str r5, [r4] 5279d93b8a2SPeter 'p2' De Schrijver 528dd313947SDave Martin/* 529dd313947SDave Martin * PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a 530dd313947SDave Martin * base instead. 531dd313947SDave Martin * Be careful not to clobber r7 when maintaing this code. 532dd313947SDave Martin */ 533dd313947SDave Martin 534bb1c9034SJean Pihetis_dll_in_lock_mode: 53589139dceSPeter 'p2' De Schrijver /* Is dll in lock mode? */ 53689139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 53789139dceSPeter 'p2' De Schrijver ldr r5, [r4] 53889139dceSPeter 'p2' De Schrijver tst r5, #0x4 539bb1c9034SJean Pihet bxne lr @ Return if locked 54089139dceSPeter 'p2' De Schrijver /* wait till dll locks */ 541dd313947SDave Martin adr r7, kick_counter 5429d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_timed: 5439d93b8a2SPeter 'p2' De Schrijver ldr r4, wait_dll_lock_counter 5449d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 545dd313947SDave Martin str r4, [r7, #wait_dll_lock_counter - kick_counter] 54689139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_status 547bb1c9034SJean Pihet /* Wait 20uS for lock */ 548bb1c9034SJean Pihet mov r6, #8 5499d93b8a2SPeter 'p2' De Schrijverwait_dll_lock: 5509d93b8a2SPeter 'p2' De Schrijver subs r6, r6, #0x1 5519d93b8a2SPeter 'p2' De Schrijver beq kick_dll 55289139dceSPeter 'p2' De Schrijver ldr r5, [r4] 55389139dceSPeter 'p2' De Schrijver and r5, r5, #0x4 55489139dceSPeter 'p2' De Schrijver cmp r5, #0x4 55589139dceSPeter 'p2' De Schrijver bne wait_dll_lock 556bb1c9034SJean Pihet bx lr @ Return when locked 55789139dceSPeter 'p2' De Schrijver 5589d93b8a2SPeter 'p2' De Schrijver /* disable/reenable DLL if not locked */ 5599d93b8a2SPeter 'p2' De Schrijverkick_dll: 5609d93b8a2SPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 5619d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 5629d93b8a2SPeter 'p2' De Schrijver mov r6, r5 563bb1c9034SJean Pihet bic r6, #(1<<3) @ disable dll 5649d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 5659d93b8a2SPeter 'p2' De Schrijver dsb 566bb1c9034SJean Pihet orr r6, r6, #(1<<3) @ enable dll 5679d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 5689d93b8a2SPeter 'p2' De Schrijver dsb 5699d93b8a2SPeter 'p2' De Schrijver ldr r4, kick_counter 5709d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 571dd313947SDave Martin str r4, [r7] @ kick_counter 5729d93b8a2SPeter 'p2' De Schrijver b wait_dll_lock_timed 5739d93b8a2SPeter 'p2' De Schrijver 574dd313947SDave Martin .align 57589139dceSPeter 'p2' De Schrijvercm_idlest1_core: 57689139dceSPeter 'p2' De Schrijver .word CM_IDLEST1_CORE_V 5779d93b8a2SPeter 'p2' De Schrijvercm_idlest_ckgen: 5789d93b8a2SPeter 'p2' De Schrijver .word CM_IDLEST_CKGEN_V 57989139dceSPeter 'p2' De Schrijversdrc_dlla_status: 58089139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_STATUS_V 58189139dceSPeter 'p2' De Schrijversdrc_dlla_ctrl: 58289139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_CTRL_V 5830795a75aSTero Kristopm_prepwstst_core_p: 5840795a75aSTero Kristo .word PM_PREPWSTST_CORE_P 5858bd22949SKevin Hilmanpm_pwstctrl_mpu: 5868bd22949SKevin Hilman .word PM_PWSTCTRL_MPU_P 5878bd22949SKevin Hilmanscratchpad_base: 5888bd22949SKevin Hilman .word SCRATCHPAD_BASE_P 5890795a75aSTero Kristosram_base: 5900795a75aSTero Kristo .word SRAM_BASE_P + 0x8000 5918bd22949SKevin Hilmansdrc_power: 5928bd22949SKevin Hilman .word SDRC_POWER_V 59327d59a4aSTero Kristocontrol_stat: 59427d59a4aSTero Kristo .word CONTROL_STAT 595458e999eSNishanth Menoncontrol_mem_rta: 596458e999eSNishanth Menon .word CONTROL_MEM_RTA_CTRL 5970bd40535SRichard Woodruffkernel_flush: 5980bd40535SRichard Woodruff .word v7_flush_dcache_all 599c4236d2eSPeter 'p2' De Schrijverl2dis_3630: 600c4236d2eSPeter 'p2' De Schrijver .word 0 6019d93b8a2SPeter 'p2' De Schrijver /* 6029d93b8a2SPeter 'p2' De Schrijver * When exporting to userspace while the counters are in SRAM, 6039d93b8a2SPeter 'p2' De Schrijver * these 2 words need to be at the end to facilitate retrival! 6049d93b8a2SPeter 'p2' De Schrijver */ 6059d93b8a2SPeter 'p2' De Schrijverkick_counter: 6069d93b8a2SPeter 'p2' De Schrijver .word 0 6079d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_counter: 6089d93b8a2SPeter 'p2' De Schrijver .word 0 609dd313947SDave MartinENDPROC(omap34xx_cpu_suspend) 610f7dfe3d8SJean Pihet 6118bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend_sz) 6128bd22949SKevin Hilman .word . - omap34xx_cpu_suspend 613