1/* 2 * linux/arch/arm/mach-omap2/sleep.S 3 * 4 * (C) Copyright 2004 5 * Texas Instruments, <www.ti.com> 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * 8 * (C) Copyright 2006 Nokia Corporation 9 * Fixed idle loop sleep 10 * Igor Stoppa <igor.stoppa@nokia.com> 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#include <linux/linkage.h> 29#include <asm/assembler.h> 30#include <mach/io.h> 31 32#include <plat/omap24xx.h> 33 34#include "sdrc.h" 35 36/* First address of reserved address space? apparently valid for OMAP2 & 3 */ 37#define A_SDRC0_V (0xC0000000) 38 39 .text 40 41/* 42 * Forces OMAP into idle state 43 * 44 * omap24xx_idle_loop_suspend() - This bit of code just executes the WFI 45 * for normal idles. 46 * 47 * Note: This code get's copied to internal SRAM at boot. When the OMAP 48 * wakes up it continues execution at the point it went to sleep. 49 */ 50 .align 3 51ENTRY(omap24xx_idle_loop_suspend) 52 stmfd sp!, {r0, lr} @ save registers on stack 53 mov r0, #0 @ clear for mcr setup 54 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 55 ldmfd sp!, {r0, pc} @ restore regs and return 56 57ENTRY(omap24xx_idle_loop_suspend_sz) 58 .word . - omap24xx_idle_loop_suspend 59 60/* 61 * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing 62 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore 63 * SDRC. 64 * 65 * Input: 66 * R0 : DLL ctrl value pre-Sleep 67 * R1 : SDRC_DLLA_CTRL 68 * R2 : SDRC_POWER 69 * 70 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on 71 * when we get called, but the DLL probably isn't. We will wait a bit more in 72 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even 73 * if in unlocked mode. 74 * 75 * For less than 242x-ES2.2 upon wake from a sleep mode where the external 76 * oscillator was stopped, a timing bug exists where a non-stabilized 12MHz 77 * clock can pass into the PRCM can cause problems at DSP and IVA. 78 * To work around this the code will switch to the 32kHz source prior to sleep. 79 * Post sleep we will shift back to using the DPLL. Apparently, 80 * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait 81 * 3x12MHz + 3x32kHz clocks for a full switch. 82 * 83 * The DLL load value is not kept in RETENTION or OFF. It needs to be restored 84 * at wake 85 */ 86 .align 3 87ENTRY(omap24xx_cpu_suspend) 88 stmfd sp!, {r0 - r12, lr} @ save registers on stack 89 mov r3, #0x0 @ clear for mcr call 90 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished 91 nop 92 nop 93 ldr r4, [r2] @ read SDRC_POWER 94 orr r4, r4, #0x40 @ enable self refresh on idle req 95 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock) 96 str r4, [r2] @ make it so 97 nop 98 mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt 99 nop 100loop: 101 subs r5, r5, #0x1 @ awake, wait just a bit 102 bne loop 103 104 /* The DPLL has to be on before we take the DDR out of self refresh */ 105 bic r4, r4, #0x40 @ now clear self refresh bit. 106 str r4, [r2] @ write to SDRC_POWER 107 ldr r4, A_SDRC0 @ make a clock happen 108 ldr r4, [r4] @ read A_SDRC0 109 nop @ start auto refresh only after clk ok 110 movs r0, r0 @ see if DDR or SDR 111 strne r0, [r1] @ rewrite DLLA to force DLL reload 112 addne r1, r1, #0x8 @ move to DLLB 113 strne r0, [r1] @ rewrite DLLB to force DLL reload 114 115 mov r5, #0x1000 116loop2: 117 subs r5, r5, #0x1 118 bne loop2 119 /* resume*/ 120 ldmfd sp!, {r0 - r12, pc} @ restore regs and return 121 122A_SDRC0: 123 .word A_SDRC0_V 124 125ENTRY(omap24xx_cpu_suspend_sz) 126 .word . - omap24xx_cpu_suspend 127