1 /* 2 * SMS/SDRC (SDRAM controller) common code for OMAP2/3 3 * 4 * Copyright (C) 2005, 2008 Texas Instruments Inc. 5 * Copyright (C) 2005, 2008 Nokia Corporation 6 * 7 * Tony Lindgren <tony@atomide.com> 8 * Paul Walmsley 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/device.h> 20 #include <linux/list.h> 21 #include <linux/errno.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 26 #include <mach/common.h> 27 #include <mach/clock.h> 28 #include <mach/sram.h> 29 30 #include "prm.h" 31 32 #include <mach/sdrc.h> 33 #include "sdrc.h" 34 35 static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1; 36 37 void __iomem *omap2_sdrc_base; 38 void __iomem *omap2_sms_base; 39 40 /* SDRC_POWER register bits */ 41 #define SDRC_POWER_EXTCLKDIS_SHIFT 3 42 #define SDRC_POWER_PWDENA_SHIFT 2 43 #define SDRC_POWER_PAGEPOLICY_SHIFT 0 44 45 /** 46 * omap2_sdrc_get_params - return SDRC register values for a given clock rate 47 * @r: SDRC clock rate (in Hz) 48 * @sdrc_cs0: chip select 0 ram timings ** 49 * @sdrc_cs1: chip select 1 ram timings ** 50 * 51 * Return pre-calculated values for the SDRC_ACTIM_CTRLA, 52 * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01] 53 * structs,for a given SDRC clock rate 'r'. 54 * These parameters control various timing delays in the SDRAM controller 55 * that are expressed in terms of the number of SDRC clock cycles to 56 * wait; hence the clock rate dependency. 57 * 58 * Supports 2 different timing parameters for both chip selects. 59 * 60 * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending. 61 * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size 62 * as sdrc_init_params_cs_0. 63 * 64 * Fills in the struct omap_sdrc_params * for each chip select. 65 * Returns 0 upon success or -1 upon failure. 66 */ 67 int omap2_sdrc_get_params(unsigned long r, 68 struct omap_sdrc_params **sdrc_cs0, 69 struct omap_sdrc_params **sdrc_cs1) 70 { 71 struct omap_sdrc_params *sp0, *sp1; 72 73 if (!sdrc_init_params_cs0) 74 return -1; 75 76 sp0 = sdrc_init_params_cs0; 77 sp1 = sdrc_init_params_cs1; 78 79 while (sp0->rate && sp0->rate != r) { 80 sp0++; 81 if (sdrc_init_params_cs1) 82 sp1++; 83 } 84 85 if (!sp0->rate) 86 return -1; 87 88 *sdrc_cs0 = sp0; 89 *sdrc_cs1 = sp1; 90 return 0; 91 } 92 93 94 void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) 95 { 96 omap2_sdrc_base = omap2_globals->sdrc; 97 omap2_sms_base = omap2_globals->sms; 98 } 99 100 /** 101 * omap2_sdrc_init - initialize SMS, SDRC devices on boot 102 * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params 103 * Support for 2 chip selects timings 104 * 105 * Turn on smart idle modes for SDRAM scheduler and controller. 106 * Program a known-good configuration for the SDRC to deal with buggy 107 * bootloaders. 108 */ 109 void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 110 struct omap_sdrc_params *sdrc_cs1) 111 { 112 u32 l; 113 114 l = sms_read_reg(SMS_SYSCONFIG); 115 l &= ~(0x3 << 3); 116 l |= (0x2 << 3); 117 sms_write_reg(l, SMS_SYSCONFIG); 118 119 l = sdrc_read_reg(SDRC_SYSCONFIG); 120 l &= ~(0x3 << 3); 121 l |= (0x2 << 3); 122 sdrc_write_reg(l, SDRC_SYSCONFIG); 123 124 sdrc_init_params_cs0 = sdrc_cs0; 125 sdrc_init_params_cs1 = sdrc_cs1; 126 127 /* XXX Enable SRFRONIDLEREQ here also? */ 128 /* 129 * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA 130 * can cause random memory corruption 131 */ 132 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | 133 (1 << SDRC_POWER_PAGEPOLICY_SHIFT); 134 sdrc_write_reg(l, SDRC_POWER); 135 } 136