1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * DRA7xx PRM instance offset macros 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Generated by code originally written by: 8 * Paul Walmsley (paul@pwsan.com) 9 * Rajendra Nayak (rnayak@ti.com) 10 * Benoit Cousson (b-cousson@ti.com) 11 * 12 * This file is automatically generated from the OMAP hardware databases. 13 * We respectfully ask that any modifications to this file be coordinated 14 * with the public linux-omap@vger.kernel.org mailing list and the 15 * authors above to ensure that the autogeneration scripts are kept 16 * up-to-date with the file contents. 17 */ 18 19 #ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H 20 #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H 21 22 #include "prcm-common.h" 23 #include "prm44xx_54xx.h" 24 #include "prm.h" 25 26 #define DRA7XX_PRM_BASE 0x4ae06000 27 28 #define DRA7XX_PRM_REGADDR(inst, reg) \ 29 OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg)) 30 31 32 /* PRM instances */ 33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000 34 #define DRA7XX_PRM_CKGEN_INST 0x0100 35 #define DRA7XX_PRM_MPU_INST 0x0300 36 #define DRA7XX_PRM_DSP1_INST 0x0400 37 #define DRA7XX_PRM_IPU_INST 0x0500 38 #define DRA7XX_PRM_COREAON_INST 0x0628 39 #define DRA7XX_PRM_CORE_INST 0x0700 40 #define DRA7XX_PRM_IVA_INST 0x0f00 41 #define DRA7XX_PRM_CAM_INST 0x1000 42 #define DRA7XX_PRM_DSS_INST 0x1100 43 #define DRA7XX_PRM_GPU_INST 0x1200 44 #define DRA7XX_PRM_L3INIT_INST 0x1300 45 #define DRA7XX_PRM_L4PER_INST 0x1400 46 #define DRA7XX_PRM_CUSTEFUSE_INST 0x1600 47 #define DRA7XX_PRM_WKUPAON_INST 0x1724 48 #define DRA7XX_PRM_WKUPAON_CM_INST 0x1800 49 #define DRA7XX_PRM_EMU_INST 0x1900 50 #define DRA7XX_PRM_EMU_CM_INST 0x1a00 51 #define DRA7XX_PRM_DSP2_INST 0x1b00 52 #define DRA7XX_PRM_EVE1_INST 0x1b40 53 #define DRA7XX_PRM_EVE2_INST 0x1b80 54 #define DRA7XX_PRM_EVE3_INST 0x1bc0 55 #define DRA7XX_PRM_EVE4_INST 0x1c00 56 #define DRA7XX_PRM_RTC_INST 0x1c60 57 #define DRA7XX_PRM_VPE_INST 0x1c80 58 #define DRA7XX_PRM_DEVICE_INST 0x1d00 59 #define DRA7XX_PRM_INSTR_INST 0x1f00 60 61 /* PRM clockdomain register offsets (from instance start) */ 62 #define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 63 #define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 64 65 /* PRM */ 66 67 /* PRM.OCP_SOCKET_PRM register offsets */ 68 #define DRA7XX_REVISION_PRM_OFFSET 0x0000 69 #define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010 70 #define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 71 #define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018 72 #define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c 73 #define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020 74 #define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028 75 #define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030 76 #define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038 77 #define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 78 #define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040) 79 #define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044 80 #define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048 81 #define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c 82 #define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050 83 #define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054 84 #define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058 85 #define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c 86 #define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060 87 #define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064 88 #define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068 89 #define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c 90 #define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070 91 #define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4 92 #define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8 93 #define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec 94 #define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4 95 96 /* PRM.CKGEN_PRM register offsets */ 97 #define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000 98 #define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000) 99 #define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 100 #define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008) 101 #define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c 102 #define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c) 103 #define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010 104 #define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010) 105 #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014 106 #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014) 107 #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018 108 #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018) 109 #define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c 110 #define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c) 111 #define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020 112 #define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020) 113 #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024 114 #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024) 115 #define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028 116 #define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028) 117 #define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c 118 #define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c) 119 #define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030 120 #define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030) 121 #define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034 122 #define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034) 123 #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038 124 #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038) 125 #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040 126 #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040) 127 #define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044 128 #define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044) 129 #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048 130 #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048) 131 #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c 132 #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c) 133 #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050 134 #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050) 135 #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054 136 #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054) 137 #define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058 138 #define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058) 139 #define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c 140 #define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c) 141 #define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060 142 #define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060) 143 #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064 144 #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064) 145 #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068 146 #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068) 147 #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c 148 #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c) 149 #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070 150 #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070) 151 #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074 152 #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074) 153 #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078 154 #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078) 155 #define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080 156 #define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080) 157 #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084 158 #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084) 159 #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088 160 #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088) 161 #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c 162 #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c) 163 #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090 164 #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090) 165 #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094 166 #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094) 167 #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098 168 #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098) 169 #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c 170 #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c) 171 #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0 172 #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0) 173 #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4 174 #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4) 175 #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8 176 #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8) 177 #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac 178 #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac) 179 #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0 180 #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0) 181 #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4 182 #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4) 183 #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8 184 #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8) 185 #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc 186 #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc) 187 #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0 188 #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0) 189 #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4 190 #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4) 191 #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8 192 #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8) 193 #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc 194 #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc) 195 #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0 196 #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0) 197 #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4 198 #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4) 199 #define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8 200 #define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8) 201 #define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc 202 #define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc) 203 #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0 204 #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0) 205 206 /* PRM.MPU_PRM register offsets */ 207 #define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 208 #define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004 209 #define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 210 211 /* PRM.DSP1_PRM register offsets */ 212 #define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000 213 #define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004 214 #define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010 215 #define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014 216 #define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024 217 218 /* PRM.IPU_PRM register offsets */ 219 #define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000 220 #define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004 221 #define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010 222 #define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014 223 #define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024 224 #define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050 225 #define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054 226 #define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058 227 #define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c 228 #define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060 229 #define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064 230 #define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068 231 #define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c 232 #define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070 233 #define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074 234 #define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078 235 #define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c 236 #define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080 237 #define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084 238 239 /* PRM.COREAON_PRM register offsets */ 240 #define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000 241 #define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004 242 #define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010 243 #define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014 244 #define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030 245 #define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034 246 #define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040 247 #define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044 248 #define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050 249 #define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054 250 #define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084 251 #define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094 252 #define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4 253 #define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4 254 255 /* PRM.CORE_PRM register offsets */ 256 #define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000 257 #define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004 258 #define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024 259 #define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c 260 #define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034 261 #define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050 262 #define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054 263 #define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058 264 #define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c 265 #define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060 266 #define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064 267 #define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c 268 #define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070 269 #define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074 270 #define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078 271 #define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c 272 #define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080 273 #define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084 274 #define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c 275 #define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094 276 #define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c 277 #define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4 278 #define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac 279 #define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4 280 #define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc 281 #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4 282 #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc 283 #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4 284 #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc 285 #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4 286 #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc 287 #define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210 288 #define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214 289 #define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224 290 #define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324 291 #define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424 292 #define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c 293 #define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434 294 #define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c 295 #define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444 296 #define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524 297 #define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 298 #define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c 299 #define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634 300 #define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c 301 #define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644 302 #define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c 303 #define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654 304 #define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c 305 #define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664 306 #define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c 307 #define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674 308 #define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c 309 #define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684 310 #define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c 311 #define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694 312 #define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c 313 #define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4 314 #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac 315 #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4 316 #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc 317 #define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4 318 #define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724 319 #define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c 320 #define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744 321 322 /* PRM.IVA_PRM register offsets */ 323 #define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000 324 #define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004 325 #define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010 326 #define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014 327 #define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024 328 #define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c 329 330 /* PRM.CAM_PRM register offsets */ 331 #define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000 332 #define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004 333 #define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020 334 #define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024 335 #define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028 336 #define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c 337 #define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030 338 #define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034 339 #define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c 340 #define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044 341 #define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c 342 343 /* PRM.DSS_PRM register offsets */ 344 #define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000 345 #define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004 346 #define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020 347 #define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 348 #define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028 349 #define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034 350 #define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c 351 352 /* PRM.GPU_PRM register offsets */ 353 #define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000 354 #define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004 355 #define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024 356 357 /* PRM.L3INIT_PRM register offsets */ 358 #define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 359 #define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 360 #define DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET 0x0010 361 #define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 362 #define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c 363 #define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 364 #define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 365 #define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040 366 #define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044 367 #define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048 368 #define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c 369 #define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050 370 #define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054 371 #define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c 372 #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c 373 #define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 374 #define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 375 #define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0 376 #define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4 377 #define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8 378 #define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc 379 #define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4 380 #define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 381 #define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec 382 #define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0 383 #define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4 384 385 /* PRM.L4PER_PRM register offsets */ 386 #define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 387 #define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004 388 #define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c 389 #define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014 390 #define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c 391 #define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024 392 #define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028 393 #define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c 394 #define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030 395 #define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034 396 #define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038 397 #define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c 398 #define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040 399 #define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044 400 #define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048 401 #define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c 402 #define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050 403 #define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054 404 #define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c 405 #define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 406 #define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 407 #define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 408 #define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c 409 #define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 410 #define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 411 #define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 412 #define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c 413 #define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 414 #define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 415 #define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c 416 #define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094 417 #define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c 418 #define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 419 #define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 420 #define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 421 #define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac 422 #define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 423 #define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 424 #define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 425 #define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc 426 #define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0 427 #define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4 428 #define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8 429 #define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc 430 #define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0 431 #define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4 432 #define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8 433 #define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc 434 #define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 435 #define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 436 #define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 437 #define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc 438 #define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 439 #define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 440 #define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 441 #define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c 442 #define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110 443 #define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114 444 #define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118 445 #define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c 446 #define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120 447 #define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124 448 #define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128 449 #define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c 450 #define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130 451 #define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134 452 #define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138 453 #define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c 454 #define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 455 #define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 456 #define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 457 #define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c 458 #define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 459 #define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 460 #define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 461 #define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c 462 #define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160 463 #define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164 464 #define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168 465 #define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c 466 #define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170 467 #define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174 468 #define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178 469 #define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c 470 #define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180 471 #define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184 472 #define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188 473 #define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c 474 #define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190 475 #define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194 476 #define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198 477 #define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c 478 #define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 479 #define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac 480 #define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 481 #define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc 482 #define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 483 #define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc 484 #define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0 485 #define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4 486 #define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc 487 #define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0 488 #define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4 489 #define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8 490 #define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec 491 #define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0 492 #define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4 493 #define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc 494 495 /* PRM.CUSTEFUSE_PRM register offsets */ 496 #define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000 497 #define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004 498 #define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024 499 500 /* PRM.WKUPAON_PRM register offsets */ 501 #define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000 502 #define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004 503 #define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008 504 #define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c 505 #define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010 506 #define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014 507 #define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018 508 #define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c 509 #define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020 510 #define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024 511 #define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028 512 #define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030 513 #define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040 514 #define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054 515 #define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058 516 #define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c 517 #define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060 518 #define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064 519 #define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068 520 #define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c 521 #define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080 522 #define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090 523 #define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098 524 #define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0 525 #define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8 526 #define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0 527 #define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8 528 529 /* PRM.WKUPAON_CM register offsets */ 530 #define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 531 #define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 532 #define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020) 533 #define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 534 #define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028) 535 #define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 536 #define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030) 537 #define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 538 #define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038) 539 #define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 540 #define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040) 541 #define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 542 #define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048) 543 #define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 544 #define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050) 545 #define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 546 #define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060) 547 #define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 548 #define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078) 549 #define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080 550 #define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080) 551 #define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088 552 #define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088) 553 #define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 554 #define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090) 555 #define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 556 #define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098) 557 #define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0 558 #define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0) 559 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0 560 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0) 561 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8 562 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8) 563 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0 564 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0) 565 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8 566 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8) 567 #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0 568 #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0) 569 #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8 570 #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8) 571 572 /* PRM.EMU_PRM register offsets */ 573 #define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 574 #define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004 575 #define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 576 577 /* PRM.EMU_CM register offsets */ 578 #define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 579 #define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004 580 #define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004) 581 #define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 582 #define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c 583 #define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c) 584 585 /* PRM.DSP2_PRM register offsets */ 586 #define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000 587 #define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004 588 #define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010 589 #define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014 590 #define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024 591 592 /* PRM.EVE1_PRM register offsets */ 593 #define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000 594 #define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004 595 #define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010 596 #define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014 597 #define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020 598 #define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024 599 600 /* PRM.EVE2_PRM register offsets */ 601 #define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000 602 #define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004 603 #define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010 604 #define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014 605 #define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020 606 #define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024 607 608 /* PRM.EVE3_PRM register offsets */ 609 #define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000 610 #define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004 611 #define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010 612 #define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014 613 #define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020 614 #define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024 615 616 /* PRM.EVE4_PRM register offsets */ 617 #define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000 618 #define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004 619 #define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010 620 #define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014 621 #define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020 622 #define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024 623 624 /* PRM.RTC_PRM register offsets */ 625 #define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000 626 #define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004 627 628 /* PRM.VPE_PRM register offsets */ 629 #define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000 630 #define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004 631 #define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020 632 #define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024 633 634 /* PRM.DEVICE_PRM register offsets */ 635 #define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000 636 #define DRA7XX_PRM_RSTST_OFFSET 0x0004 637 #define DRA7XX_PRM_RSTTIME_OFFSET 0x0008 638 #define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c 639 #define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010 640 #define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014 641 #define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018 642 #define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c 643 #define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020 644 #define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 645 #define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 646 #define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c 647 #define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030 648 #define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 649 #define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 650 #define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c 651 #define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc 652 #define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0 653 #define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4 654 #define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8 655 #define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc 656 #define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0 657 #define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4 658 #define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8 659 #define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc 660 #define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0 661 #define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4 662 #define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8 663 #define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec 664 #define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0 665 #define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4 666 #define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8 667 #define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc 668 #define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100 669 #define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110 670 #define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114 671 #define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118 672 #define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c 673 #define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120 674 #define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124 675 #define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128 676 #define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c 677 #define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130 678 #define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134 679 680 #endif 681