xref: /linux/arch/arm/mach-omap2/prm44xx.h (revision d198b514bd9e94930ee0b9ca1cad0a51f5e29608)
1c1294045SRajendra Nayak /*
2c1294045SRajendra Nayak  * OMAP44xx PRM instance offset macros
3c1294045SRajendra Nayak  *
479328706SBenoit Cousson  * Copyright (C) 2009-2010 Texas Instruments, Inc.
579328706SBenoit Cousson  * Copyright (C) 2009-2010 Nokia Corporation
6c1294045SRajendra Nayak  *
7c1294045SRajendra Nayak  * Paul Walmsley (paul@pwsan.com)
8c1294045SRajendra Nayak  * Rajendra Nayak (rnayak@ti.com)
9c1294045SRajendra Nayak  * Benoit Cousson (b-cousson@ti.com)
10c1294045SRajendra Nayak  *
11c1294045SRajendra Nayak  * This file is automatically generated from the OMAP hardware databases.
12c1294045SRajendra Nayak  * We respectfully ask that any modifications to this file be coordinated
13c1294045SRajendra Nayak  * with the public linux-omap@vger.kernel.org mailing list and the
14c1294045SRajendra Nayak  * authors above to ensure that the autogeneration scripts are kept
15c1294045SRajendra Nayak  * up-to-date with the file contents.
16c1294045SRajendra Nayak  *
17c1294045SRajendra Nayak  * This program is free software; you can redistribute it and/or modify
18c1294045SRajendra Nayak  * it under the terms of the GNU General Public License version 2 as
19c1294045SRajendra Nayak  * published by the Free Software Foundation.
20*d198b514SPaul Walmsley  *
21*d198b514SPaul Walmsley  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
22*d198b514SPaul Walmsley  *     or "OMAP4430".
23c1294045SRajendra Nayak  */
24c1294045SRajendra Nayak 
25c1294045SRajendra Nayak #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
26c1294045SRajendra Nayak #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
27c1294045SRajendra Nayak 
28*d198b514SPaul Walmsley #include "prcm-common.h"
29*d198b514SPaul Walmsley 
30*d198b514SPaul Walmsley #define OMAP4430_PRM_BASE		0x4a306000
31*d198b514SPaul Walmsley 
32*d198b514SPaul Walmsley #define OMAP44XX_PRM_REGADDR(module, reg)				\
33*d198b514SPaul Walmsley 	OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE +	(module) + (reg))
34*d198b514SPaul Walmsley 
35*d198b514SPaul Walmsley 
36*d198b514SPaul Walmsley /* PRM instances */
37*d198b514SPaul Walmsley #define OMAP4430_PRM_OCP_SOCKET_MOD	0x0000
38*d198b514SPaul Walmsley #define OMAP4430_PRM_CKGEN_MOD		0x0100
39*d198b514SPaul Walmsley #define OMAP4430_PRM_MPU_MOD		0x0300
40*d198b514SPaul Walmsley #define OMAP4430_PRM_TESLA_MOD		0x0400
41*d198b514SPaul Walmsley #define OMAP4430_PRM_ABE_MOD		0x0500
42*d198b514SPaul Walmsley #define OMAP4430_PRM_ALWAYS_ON_MOD	0x0600
43*d198b514SPaul Walmsley #define OMAP4430_PRM_CORE_MOD		0x0700
44*d198b514SPaul Walmsley #define OMAP4430_PRM_IVAHD_MOD		0x0f00
45*d198b514SPaul Walmsley #define OMAP4430_PRM_CAM_MOD		0x1000
46*d198b514SPaul Walmsley #define OMAP4430_PRM_DSS_MOD		0x1100
47*d198b514SPaul Walmsley #define OMAP4430_PRM_GFX_MOD		0x1200
48*d198b514SPaul Walmsley #define OMAP4430_PRM_L3INIT_MOD		0x1300
49*d198b514SPaul Walmsley #define OMAP4430_PRM_L4PER_MOD		0x1400
50*d198b514SPaul Walmsley #define OMAP4430_PRM_CEFUSE_MOD		0x1600
51*d198b514SPaul Walmsley #define OMAP4430_PRM_WKUP_MOD		0x1700
52*d198b514SPaul Walmsley #define OMAP4430_PRM_WKUP_CM_MOD	0x1800
53*d198b514SPaul Walmsley #define OMAP4430_PRM_EMU_MOD		0x1900
54*d198b514SPaul Walmsley #define OMAP4430_PRM_EMU_CM_MOD		0x1a00
55*d198b514SPaul Walmsley #define OMAP4430_PRM_DEVICE_MOD		0x1b00
56*d198b514SPaul Walmsley #define OMAP4430_PRM_INSTR_MOD		0x1f00
57*d198b514SPaul Walmsley 
58*d198b514SPaul Walmsley 
59*d198b514SPaul Walmsley /* OMAP4 specific register offsets */
60*d198b514SPaul Walmsley #define OMAP4_RM_RSTCTRL				0x0000
61*d198b514SPaul Walmsley #define OMAP4_RM_RSTTIME				0x0004
62*d198b514SPaul Walmsley #define OMAP4_RM_RSTST					0x0008
63*d198b514SPaul Walmsley #define OMAP4_PM_PWSTCTRL				0x0000
64*d198b514SPaul Walmsley #define OMAP4_PM_PWSTST					0x0004
65*d198b514SPaul Walmsley 
66c1294045SRajendra Nayak 
67c1294045SRajendra Nayak /* PRM */
68c1294045SRajendra Nayak 
69c1294045SRajendra Nayak /* PRM.OCP_SOCKET_PRM register offsets */
702339ea99SRajendra Nayak #define OMAP4_REVISION_PRM_OFFSET			0x0000
71c1294045SRajendra Nayak #define OMAP4430_REVISION_PRM				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000)
722339ea99SRajendra Nayak #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET			0x0010
73c1294045SRajendra Nayak #define OMAP4430_PRM_IRQSTATUS_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010)
742339ea99SRajendra Nayak #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET		0x0014
75c1294045SRajendra Nayak #define OMAP4430_PRM_IRQSTATUS_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014)
762339ea99SRajendra Nayak #define OMAP4_PRM_IRQENABLE_MPU_OFFSET			0x0018
77c1294045SRajendra Nayak #define OMAP4430_PRM_IRQENABLE_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018)
782339ea99SRajendra Nayak #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET		0x001c
79c1294045SRajendra Nayak #define OMAP4430_PRM_IRQENABLE_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c)
802339ea99SRajendra Nayak #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET		0x0020
81c1294045SRajendra Nayak #define OMAP4430_PRM_IRQSTATUS_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020)
822339ea99SRajendra Nayak #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET		0x0028
83c1294045SRajendra Nayak #define OMAP4430_PRM_IRQENABLE_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028)
842339ea99SRajendra Nayak #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET		0x0030
85c1294045SRajendra Nayak #define OMAP4430_PRM_IRQSTATUS_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
862339ea99SRajendra Nayak #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET		0x0038
87c1294045SRajendra Nayak #define OMAP4430_PRM_IRQENABLE_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
88fdd4f409SRajendra Nayak #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET		0x0040
89fdd4f409SRajendra Nayak #define OMAP4430_CM_PRM_PROFILING_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
90c1294045SRajendra Nayak 
91c1294045SRajendra Nayak /* PRM.CKGEN_PRM register offsets */
922339ea99SRajendra Nayak #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET		0x0000
93c1294045SRajendra Nayak #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
942339ea99SRajendra Nayak #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET			0x0008
95c1294045SRajendra Nayak #define OMAP4430_CM_L4_WKUP_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
962339ea99SRajendra Nayak #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET		0x000c
97c1294045SRajendra Nayak #define OMAP4430_CM_ABE_PLL_REF_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c)
982339ea99SRajendra Nayak #define OMAP4_CM_SYS_CLKSEL_OFFSET			0x0010
99c1294045SRajendra Nayak #define OMAP4430_CM_SYS_CLKSEL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010)
100c1294045SRajendra Nayak 
101c1294045SRajendra Nayak /* PRM.MPU_PRM register offsets */
1022339ea99SRajendra Nayak #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET			0x0000
103c1294045SRajendra Nayak #define OMAP4430_PM_MPU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000)
1042339ea99SRajendra Nayak #define OMAP4_PM_MPU_PWRSTST_OFFSET			0x0004
105c1294045SRajendra Nayak #define OMAP4430_PM_MPU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004)
1062339ea99SRajendra Nayak #define OMAP4_RM_MPU_RSTST_OFFSET			0x0014
107c1294045SRajendra Nayak #define OMAP4430_RM_MPU_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014)
1082339ea99SRajendra Nayak #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
109c1294045SRajendra Nayak #define OMAP4430_RM_MPU_MPU_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024)
110c1294045SRajendra Nayak 
111c1294045SRajendra Nayak /* PRM.TESLA_PRM register offsets */
1122339ea99SRajendra Nayak #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET			0x0000
113c1294045SRajendra Nayak #define OMAP4430_PM_TESLA_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000)
1142339ea99SRajendra Nayak #define OMAP4_PM_TESLA_PWRSTST_OFFSET			0x0004
115c1294045SRajendra Nayak #define OMAP4430_PM_TESLA_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004)
1162339ea99SRajendra Nayak #define OMAP4_RM_TESLA_RSTCTRL_OFFSET			0x0010
117c1294045SRajendra Nayak #define OMAP4430_RM_TESLA_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010)
1182339ea99SRajendra Nayak #define OMAP4_RM_TESLA_RSTST_OFFSET			0x0014
119c1294045SRajendra Nayak #define OMAP4430_RM_TESLA_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014)
1202339ea99SRajendra Nayak #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET		0x0024
121c1294045SRajendra Nayak #define OMAP4430_RM_TESLA_TESLA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024)
122c1294045SRajendra Nayak 
123c1294045SRajendra Nayak /* PRM.ABE_PRM register offsets */
1242339ea99SRajendra Nayak #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET			0x0000
125c1294045SRajendra Nayak #define OMAP4430_PM_ABE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000)
1262339ea99SRajendra Nayak #define OMAP4_PM_ABE_PWRSTST_OFFSET			0x0004
127c1294045SRajendra Nayak #define OMAP4430_PM_ABE_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004)
1282339ea99SRajendra Nayak #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET		0x002c
129c1294045SRajendra Nayak #define OMAP4430_RM_ABE_AESS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c)
1302339ea99SRajendra Nayak #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET			0x0030
131c1294045SRajendra Nayak #define OMAP4430_PM_ABE_PDM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030)
1322339ea99SRajendra Nayak #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET			0x0034
133c1294045SRajendra Nayak #define OMAP4430_RM_ABE_PDM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034)
1342339ea99SRajendra Nayak #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET			0x0038
135c1294045SRajendra Nayak #define OMAP4430_PM_ABE_DMIC_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038)
1362339ea99SRajendra Nayak #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET		0x003c
137c1294045SRajendra Nayak #define OMAP4430_RM_ABE_DMIC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c)
1382339ea99SRajendra Nayak #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET			0x0040
139c1294045SRajendra Nayak #define OMAP4430_PM_ABE_MCASP_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040)
1402339ea99SRajendra Nayak #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET		0x0044
141c1294045SRajendra Nayak #define OMAP4430_RM_ABE_MCASP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044)
1422339ea99SRajendra Nayak #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET		0x0048
143c1294045SRajendra Nayak #define OMAP4430_PM_ABE_MCBSP1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048)
1442339ea99SRajendra Nayak #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET		0x004c
145c1294045SRajendra Nayak #define OMAP4430_RM_ABE_MCBSP1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c)
1462339ea99SRajendra Nayak #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET		0x0050
147c1294045SRajendra Nayak #define OMAP4430_PM_ABE_MCBSP2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050)
1482339ea99SRajendra Nayak #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET		0x0054
149c1294045SRajendra Nayak #define OMAP4430_RM_ABE_MCBSP2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054)
1502339ea99SRajendra Nayak #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET		0x0058
151c1294045SRajendra Nayak #define OMAP4430_PM_ABE_MCBSP3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058)
1522339ea99SRajendra Nayak #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET		0x005c
153c1294045SRajendra Nayak #define OMAP4430_RM_ABE_MCBSP3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c)
1542339ea99SRajendra Nayak #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET		0x0060
155c1294045SRajendra Nayak #define OMAP4430_PM_ABE_SLIMBUS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060)
1562339ea99SRajendra Nayak #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET		0x0064
157c1294045SRajendra Nayak #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064)
1582339ea99SRajendra Nayak #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET		0x0068
159c1294045SRajendra Nayak #define OMAP4430_PM_ABE_TIMER5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068)
1602339ea99SRajendra Nayak #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET		0x006c
161c1294045SRajendra Nayak #define OMAP4430_RM_ABE_TIMER5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c)
1622339ea99SRajendra Nayak #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET		0x0070
163c1294045SRajendra Nayak #define OMAP4430_PM_ABE_TIMER6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070)
1642339ea99SRajendra Nayak #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET		0x0074
165c1294045SRajendra Nayak #define OMAP4430_RM_ABE_TIMER6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074)
1662339ea99SRajendra Nayak #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET		0x0078
167c1294045SRajendra Nayak #define OMAP4430_PM_ABE_TIMER7_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078)
1682339ea99SRajendra Nayak #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET		0x007c
169c1294045SRajendra Nayak #define OMAP4430_RM_ABE_TIMER7_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c)
1702339ea99SRajendra Nayak #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET		0x0080
171c1294045SRajendra Nayak #define OMAP4430_PM_ABE_TIMER8_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080)
1722339ea99SRajendra Nayak #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET		0x0084
173c1294045SRajendra Nayak #define OMAP4430_RM_ABE_TIMER8_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084)
1742339ea99SRajendra Nayak #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET			0x0088
175c1294045SRajendra Nayak #define OMAP4430_PM_ABE_WDT3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088)
1762339ea99SRajendra Nayak #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET		0x008c
177c1294045SRajendra Nayak #define OMAP4430_RM_ABE_WDT3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c)
178c1294045SRajendra Nayak 
179c1294045SRajendra Nayak /* PRM.ALWAYS_ON_PRM register offsets */
1802339ea99SRajendra Nayak #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET		0x0024
181c1294045SRajendra Nayak #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024)
1822339ea99SRajendra Nayak #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET		0x0028
183c1294045SRajendra Nayak #define OMAP4430_PM_ALWON_SR_MPU_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028)
1842339ea99SRajendra Nayak #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET		0x002c
185c1294045SRajendra Nayak #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c)
1862339ea99SRajendra Nayak #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET		0x0030
187c1294045SRajendra Nayak #define OMAP4430_PM_ALWON_SR_IVA_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030)
1882339ea99SRajendra Nayak #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET		0x0034
189c1294045SRajendra Nayak #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034)
1902339ea99SRajendra Nayak #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET		0x0038
191c1294045SRajendra Nayak #define OMAP4430_PM_ALWON_SR_CORE_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038)
1922339ea99SRajendra Nayak #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET		0x003c
193c1294045SRajendra Nayak #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c)
194c1294045SRajendra Nayak 
195c1294045SRajendra Nayak /* PRM.CORE_PRM register offsets */
1962339ea99SRajendra Nayak #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET			0x0000
197c1294045SRajendra Nayak #define OMAP4430_PM_CORE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000)
1982339ea99SRajendra Nayak #define OMAP4_PM_CORE_PWRSTST_OFFSET			0x0004
199c1294045SRajendra Nayak #define OMAP4430_PM_CORE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004)
2002339ea99SRajendra Nayak #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET		0x0024
201c1294045SRajendra Nayak #define OMAP4430_RM_L3_1_L3_1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024)
2022339ea99SRajendra Nayak #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET		0x0124
203c1294045SRajendra Nayak #define OMAP4430_RM_L3_2_L3_2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124)
2042339ea99SRajendra Nayak #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET		0x012c
205c1294045SRajendra Nayak #define OMAP4430_RM_L3_2_GPMC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c)
2062339ea99SRajendra Nayak #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET		0x0134
207c1294045SRajendra Nayak #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134)
2082339ea99SRajendra Nayak #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET			0x0210
209c1294045SRajendra Nayak #define OMAP4430_RM_DUCATI_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210)
2102339ea99SRajendra Nayak #define OMAP4_RM_DUCATI_RSTST_OFFSET			0x0214
211c1294045SRajendra Nayak #define OMAP4430_RM_DUCATI_RSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214)
2122339ea99SRajendra Nayak #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET		0x0224
213c1294045SRajendra Nayak #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224)
2142339ea99SRajendra Nayak #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET		0x0324
215c1294045SRajendra Nayak #define OMAP4430_RM_SDMA_SDMA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324)
2162339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET		0x0424
217c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_DMM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424)
2182339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET		0x042c
219c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c)
2202339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET		0x0434
221c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434)
2222339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET		0x043c
223c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c)
2242339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET		0x0444
225c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_DLL_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444)
2262339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET		0x0454
227c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454)
2282339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET		0x045c
229c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c)
2302339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET		0x0464
231c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464)
2322339ea99SRajendra Nayak #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET		0x0524
233c1294045SRajendra Nayak #define OMAP4430_RM_D2D_SAD2D_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524)
2342339ea99SRajendra Nayak #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET		0x052c
235c1294045SRajendra Nayak #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c)
2362339ea99SRajendra Nayak #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET		0x0534
237c1294045SRajendra Nayak #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534)
2382339ea99SRajendra Nayak #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET		0x0624
239c1294045SRajendra Nayak #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624)
2402339ea99SRajendra Nayak #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET		0x062c
241c1294045SRajendra Nayak #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c)
2422339ea99SRajendra Nayak #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET		0x0634
243c1294045SRajendra Nayak #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634)
2442339ea99SRajendra Nayak #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET		0x063c
245c1294045SRajendra Nayak #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c)
2462339ea99SRajendra Nayak #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET		0x0724
247c1294045SRajendra Nayak #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724)
2482339ea99SRajendra Nayak #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET	0x072c
249c1294045SRajendra Nayak #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c)
2502339ea99SRajendra Nayak #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET		0x0744
251c1294045SRajendra Nayak #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744)
252c1294045SRajendra Nayak 
253c1294045SRajendra Nayak /* PRM.IVAHD_PRM register offsets */
2542339ea99SRajendra Nayak #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET			0x0000
255c1294045SRajendra Nayak #define OMAP4430_PM_IVAHD_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000)
2562339ea99SRajendra Nayak #define OMAP4_PM_IVAHD_PWRSTST_OFFSET			0x0004
257c1294045SRajendra Nayak #define OMAP4430_PM_IVAHD_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004)
2582339ea99SRajendra Nayak #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET			0x0010
259c1294045SRajendra Nayak #define OMAP4430_RM_IVAHD_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010)
2602339ea99SRajendra Nayak #define OMAP4_RM_IVAHD_RSTST_OFFSET			0x0014
261c1294045SRajendra Nayak #define OMAP4430_RM_IVAHD_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014)
2622339ea99SRajendra Nayak #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET		0x0024
263c1294045SRajendra Nayak #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024)
2642339ea99SRajendra Nayak #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET		0x002c
265c1294045SRajendra Nayak #define OMAP4430_RM_IVAHD_SL2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c)
266c1294045SRajendra Nayak 
267c1294045SRajendra Nayak /* PRM.CAM_PRM register offsets */
2682339ea99SRajendra Nayak #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET			0x0000
269c1294045SRajendra Nayak #define OMAP4430_PM_CAM_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000)
2702339ea99SRajendra Nayak #define OMAP4_PM_CAM_PWRSTST_OFFSET			0x0004
271c1294045SRajendra Nayak #define OMAP4430_PM_CAM_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004)
2722339ea99SRajendra Nayak #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET			0x0024
273c1294045SRajendra Nayak #define OMAP4430_RM_CAM_ISS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024)
2742339ea99SRajendra Nayak #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET		0x002c
275c1294045SRajendra Nayak #define OMAP4430_RM_CAM_FDIF_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c)
276c1294045SRajendra Nayak 
277c1294045SRajendra Nayak /* PRM.DSS_PRM register offsets */
2782339ea99SRajendra Nayak #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET			0x0000
279c1294045SRajendra Nayak #define OMAP4430_PM_DSS_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000)
2802339ea99SRajendra Nayak #define OMAP4_PM_DSS_PWRSTST_OFFSET			0x0004
281c1294045SRajendra Nayak #define OMAP4430_PM_DSS_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004)
2822339ea99SRajendra Nayak #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET			0x0020
283c1294045SRajendra Nayak #define OMAP4430_PM_DSS_DSS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020)
2842339ea99SRajendra Nayak #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
285c1294045SRajendra Nayak #define OMAP4430_RM_DSS_DSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024)
2862339ea99SRajendra Nayak #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET		0x002c
287c1294045SRajendra Nayak #define OMAP4430_RM_DSS_DEISS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c)
288c1294045SRajendra Nayak 
289c1294045SRajendra Nayak /* PRM.GFX_PRM register offsets */
2902339ea99SRajendra Nayak #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET			0x0000
291c1294045SRajendra Nayak #define OMAP4430_PM_GFX_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000)
2922339ea99SRajendra Nayak #define OMAP4_PM_GFX_PWRSTST_OFFSET			0x0004
293c1294045SRajendra Nayak #define OMAP4430_PM_GFX_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004)
2942339ea99SRajendra Nayak #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET			0x0024
295c1294045SRajendra Nayak #define OMAP4430_RM_GFX_GFX_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024)
296c1294045SRajendra Nayak 
297c1294045SRajendra Nayak /* PRM.L3INIT_PRM register offsets */
2982339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET		0x0000
299c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000)
3002339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_PWRSTST_OFFSET			0x0004
301c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004)
3022339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET		0x0028
303c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_MMC1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028)
3042339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET		0x002c
305c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_MMC1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c)
3062339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET		0x0030
307c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_MMC2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030)
3082339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET		0x0034
309c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_MMC2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034)
3102339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET		0x0038
311c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_HSI_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038)
3122339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET		0x003c
313c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_HSI_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c)
3142339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET		0x0040
315c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040)
3162339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET		0x0044
317c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044)
3182339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET		0x0058
319c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058)
3202339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET		0x005c
321c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c)
3222339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET		0x0060
323c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060)
3242339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET		0x0064
325c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064)
3262339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET		0x0068
327c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068)
3282339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET		0x006c
329c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c)
3302339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET		0x007c
331c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_P1500_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c)
3322339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET		0x0084
333c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_EMAC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084)
3342339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET		0x0088
335c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_SATA_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088)
3362339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET		0x008c
337c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_SATA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c)
3382339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET		0x0094
339c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094)
3402339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET		0x0098
341c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_PCIESS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098)
3422339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET		0x009c
343c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c)
3442339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET		0x00ac
345c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac)
3462339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET		0x00c0
347c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_XHPI_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0)
3482339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET		0x00c4
349c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_XHPI_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4)
3502339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET		0x00c8
351c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_MMC6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8)
3522339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET		0x00cc
353c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_MMC6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc)
3542339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET	0x00d0
355c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0)
3562339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET	0x00d4
357c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4)
3582339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET	0x00e4
359c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4)
360c1294045SRajendra Nayak 
361c1294045SRajendra Nayak /* PRM.L4PER_PRM register offsets */
3622339ea99SRajendra Nayak #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET			0x0000
363c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000)
3642339ea99SRajendra Nayak #define OMAP4_PM_L4PER_PWRSTST_OFFSET			0x0004
365c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004)
3662339ea99SRajendra Nayak #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET		0x0024
367c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_ADC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024)
3682339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET		0x0028
369c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028)
3702339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET		0x002c
371c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c)
3722339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET		0x0030
373c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030)
3742339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET		0x0034
375c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034)
3762339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET		0x0038
377c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038)
3782339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET		0x003c
379c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c)
3802339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET		0x0040
381c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040)
3822339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET		0x0044
383c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044)
3842339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET		0x0048
385c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048)
3862339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET		0x004c
387c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c)
3882339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET		0x0050
389c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050)
3902339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET		0x0054
391c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054)
3922339ea99SRajendra Nayak #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET		0x005c
393c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_ELM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c)
3942339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET		0x0060
395c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_GPIO2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060)
3962339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET		0x0064
397c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_GPIO2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064)
3982339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET		0x0068
399c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_GPIO3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068)
4002339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET		0x006c
401c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_GPIO3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c)
4022339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET		0x0070
403c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_GPIO4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070)
4042339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET		0x0074
405c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_GPIO4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074)
4062339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET		0x0078
407c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_GPIO5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078)
4082339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET		0x007c
409c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_GPIO5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c)
4102339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET		0x0080
411c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_GPIO6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080)
4122339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET		0x0084
413c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_GPIO6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084)
4142339ea99SRajendra Nayak #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET		0x008c
415c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c)
4162339ea99SRajendra Nayak #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET		0x0090
417c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_HECC1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090)
4182339ea99SRajendra Nayak #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET		0x0094
419c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_HECC1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094)
4202339ea99SRajendra Nayak #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET		0x0098
421c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_HECC2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098)
4222339ea99SRajendra Nayak #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET		0x009c
423c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_HECC2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c)
4242339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET		0x00a0
425c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_I2C1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0)
4262339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET		0x00a4
427c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_I2C1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4)
4282339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET		0x00a8
429c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_I2C2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8)
4302339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET		0x00ac
431c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_I2C2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac)
4322339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET		0x00b0
433c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_I2C3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0)
4342339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET		0x00b4
435c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_I2C3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4)
4362339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET		0x00b8
437c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_I2C4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8)
4382339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET		0x00bc
439c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_I2C4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc)
4402339ea99SRajendra Nayak #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET		0x00c0
441c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_L4_PER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0)
4422339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET		0x00d0
443c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCASP2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0)
4442339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET		0x00d4
445c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCASP2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4)
4462339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET		0x00d8
447c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCASP3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8)
4482339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET		0x00dc
449c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCASP3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc)
4502339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET		0x00e0
451c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCBSP4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0)
4522339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET		0x00e4
453c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4)
4542339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET		0x00ec
455c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MGATE_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec)
4562339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET		0x00f0
457c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCSPI1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0)
4582339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET		0x00f4
459c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4)
4602339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET		0x00f8
461c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCSPI2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8)
4622339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET		0x00fc
463c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc)
4642339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET		0x0100
465c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCSPI3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100)
4662339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET		0x0104
467c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104)
4682339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET		0x0108
469c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCSPI4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108)
4702339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET		0x010c
471c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c)
4722339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET		0x0120
473c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MMCSD3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120)
4742339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET		0x0124
475c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124)
4762339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET		0x0128
477c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MMCSD4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128)
4782339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET		0x012c
479c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c)
4802339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET		0x0134
481c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134)
4822339ea99SRajendra Nayak #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET		0x0138
483c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138)
4842339ea99SRajendra Nayak #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET		0x013c
485c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c)
4862339ea99SRajendra Nayak #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET		0x0140
487c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_UART1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140)
4882339ea99SRajendra Nayak #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET		0x0144
489c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_UART1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144)
4902339ea99SRajendra Nayak #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET		0x0148
491c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_UART2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148)
4922339ea99SRajendra Nayak #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET		0x014c
493c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_UART2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c)
4942339ea99SRajendra Nayak #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET		0x0150
495c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_UART3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150)
4962339ea99SRajendra Nayak #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET		0x0154
497c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_UART3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154)
4982339ea99SRajendra Nayak #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET		0x0158
499c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_UART4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158)
5002339ea99SRajendra Nayak #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET		0x015c
501c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_UART4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c)
5022339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET		0x0160
503c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MMCSD5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160)
5042339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET		0x0164
505c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164)
5062339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET		0x0168
507c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_I2C5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168)
5082339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET		0x016c
509c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_I2C5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c)
5102339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET		0x01a4
511c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_AES1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4)
5122339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET		0x01ac
513c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_AES2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac)
5142339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET		0x01b4
515c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4)
5162339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET		0x01bc
517c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc)
5182339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET		0x01c4
519c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_RNG_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4)
5202339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET		0x01cc
521c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc)
5222339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET		0x01dc
523c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc)
524c1294045SRajendra Nayak 
525c1294045SRajendra Nayak /* PRM.CEFUSE_PRM register offsets */
5262339ea99SRajendra Nayak #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET		0x0000
527c1294045SRajendra Nayak #define OMAP4430_PM_CEFUSE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000)
5282339ea99SRajendra Nayak #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET			0x0004
529c1294045SRajendra Nayak #define OMAP4430_PM_CEFUSE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004)
5302339ea99SRajendra Nayak #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET		0x0024
531c1294045SRajendra Nayak #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024)
532c1294045SRajendra Nayak 
533c1294045SRajendra Nayak /* PRM.WKUP_PRM register offsets */
5342339ea99SRajendra Nayak #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET		0x0024
535c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024)
5362339ea99SRajendra Nayak #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET		0x002c
537c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_WDT1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c)
5382339ea99SRajendra Nayak #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET			0x0030
539c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_WDT2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030)
5402339ea99SRajendra Nayak #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET		0x0034
541c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_WDT2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034)
5422339ea99SRajendra Nayak #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET		0x0038
543c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_GPIO1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038)
5442339ea99SRajendra Nayak #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET		0x003c
545c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_GPIO1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c)
5462339ea99SRajendra Nayak #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET		0x0040
547c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_TIMER1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040)
5482339ea99SRajendra Nayak #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET		0x0044
549c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_TIMER1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044)
5502339ea99SRajendra Nayak #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET		0x0048
551c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_TIMER12_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048)
5522339ea99SRajendra Nayak #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET		0x004c
553c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_TIMER12_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c)
5542339ea99SRajendra Nayak #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET		0x0054
555c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054)
5562339ea99SRajendra Nayak #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET			0x0058
557c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_USIM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058)
5582339ea99SRajendra Nayak #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET		0x005c
559c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_USIM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c)
5602339ea99SRajendra Nayak #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET		0x0064
561c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_SARRAM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064)
5622339ea99SRajendra Nayak #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET		0x0078
563c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078)
5642339ea99SRajendra Nayak #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET		0x007c
565c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c)
5662339ea99SRajendra Nayak #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET			0x0080
567c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_RTC_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080)
5682339ea99SRajendra Nayak #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET		0x0084
569c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_RTC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084)
570c1294045SRajendra Nayak 
571c1294045SRajendra Nayak /* PRM.WKUP_CM register offsets */
5722339ea99SRajendra Nayak #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
573c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000)
5742339ea99SRajendra Nayak #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x0020
575c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020)
5762339ea99SRajendra Nayak #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x0028
577c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_WDT1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028)
5782339ea99SRajendra Nayak #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET		0x0030
579c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_WDT2_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030)
5802339ea99SRajendra Nayak #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET		0x0038
581c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038)
5822339ea99SRajendra Nayak #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x0040
583c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040)
5842339ea99SRajendra Nayak #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET		0x0048
585c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048)
5862339ea99SRajendra Nayak #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET		0x0050
587c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050)
5882339ea99SRajendra Nayak #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET		0x0058
589c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_USIM_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058)
5902339ea99SRajendra Nayak #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET		0x0060
591c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060)
5922339ea99SRajendra Nayak #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET		0x0078
593c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078)
5942339ea99SRajendra Nayak #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET		0x0080
595c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_RTC_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080)
5962339ea99SRajendra Nayak #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET		0x0088
597c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088)
598c1294045SRajendra Nayak 
599c1294045SRajendra Nayak /* PRM.EMU_PRM register offsets */
6002339ea99SRajendra Nayak #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET			0x0000
601c1294045SRajendra Nayak #define OMAP4430_PM_EMU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000)
6022339ea99SRajendra Nayak #define OMAP4_PM_EMU_PWRSTST_OFFSET			0x0004
603c1294045SRajendra Nayak #define OMAP4430_PM_EMU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004)
6042339ea99SRajendra Nayak #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET		0x0024
605c1294045SRajendra Nayak #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024)
606c1294045SRajendra Nayak 
607c1294045SRajendra Nayak /* PRM.EMU_CM register offsets */
6082339ea99SRajendra Nayak #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET			0x0000
609c1294045SRajendra Nayak #define OMAP4430_CM_EMU_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000)
6102339ea99SRajendra Nayak #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET			0x0008
611c1294045SRajendra Nayak #define OMAP4430_CM_EMU_DYNAMICDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008)
6122339ea99SRajendra Nayak #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET		0x0020
613c1294045SRajendra Nayak #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020)
614c1294045SRajendra Nayak 
615c1294045SRajendra Nayak /* PRM.DEVICE_PRM register offsets */
6162339ea99SRajendra Nayak #define OMAP4_PRM_RSTCTRL_OFFSET			0x0000
617c1294045SRajendra Nayak #define OMAP4430_PRM_RSTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000)
6182339ea99SRajendra Nayak #define OMAP4_PRM_RSTST_OFFSET				0x0004
619c1294045SRajendra Nayak #define OMAP4430_PRM_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004)
6202339ea99SRajendra Nayak #define OMAP4_PRM_RSTTIME_OFFSET			0x0008
621c1294045SRajendra Nayak #define OMAP4430_PRM_RSTTIME				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008)
6222339ea99SRajendra Nayak #define OMAP4_PRM_CLKREQCTRL_OFFSET			0x000c
623c1294045SRajendra Nayak #define OMAP4430_PRM_CLKREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c)
6242339ea99SRajendra Nayak #define OMAP4_PRM_VOLTCTRL_OFFSET			0x0010
625c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010)
6262339ea99SRajendra Nayak #define OMAP4_PRM_PWRREQCTRL_OFFSET			0x0014
627c1294045SRajendra Nayak #define OMAP4430_PRM_PWRREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014)
6282339ea99SRajendra Nayak #define OMAP4_PRM_PSCON_COUNT_OFFSET			0x0018
629c1294045SRajendra Nayak #define OMAP4430_PRM_PSCON_COUNT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018)
6302339ea99SRajendra Nayak #define OMAP4_PRM_IO_COUNT_OFFSET			0x001c
631c1294045SRajendra Nayak #define OMAP4430_PRM_IO_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c)
6322339ea99SRajendra Nayak #define OMAP4_PRM_IO_PMCTRL_OFFSET			0x0020
633c1294045SRajendra Nayak #define OMAP4430_PRM_IO_PMCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020)
6342339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET		0x0024
635c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_WARMRESET		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024)
6362339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET		0x0028
637c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_CORE_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028)
6382339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET		0x002c
639c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_MPU_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c)
6402339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET		0x0030
641c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_IVA_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030)
6422339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET	0x0034
643c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034)
6442339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET	0x0038
645c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038)
6462339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET	0x003c
647c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c)
6482339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET			0x0040
649c1294045SRajendra Nayak #define OMAP4430_PRM_VP_CORE_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040)
6502339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_STATUS_OFFSET			0x0044
651c1294045SRajendra Nayak #define OMAP4430_PRM_VP_CORE_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044)
6522339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET		0x0048
653c1294045SRajendra Nayak #define OMAP4430_PRM_VP_CORE_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048)
6542339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET		0x004c
655c1294045SRajendra Nayak #define OMAP4430_PRM_VP_CORE_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c)
6562339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET		0x0050
657c1294045SRajendra Nayak #define OMAP4430_PRM_VP_CORE_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050)
6582339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET		0x0054
659c1294045SRajendra Nayak #define OMAP4430_PRM_VP_CORE_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054)
6602339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET			0x0058
661c1294045SRajendra Nayak #define OMAP4430_PRM_VP_MPU_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058)
6622339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_STATUS_OFFSET			0x005c
663c1294045SRajendra Nayak #define OMAP4430_PRM_VP_MPU_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c)
6642339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET		0x0060
665c1294045SRajendra Nayak #define OMAP4430_PRM_VP_MPU_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060)
6662339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET			0x0064
667c1294045SRajendra Nayak #define OMAP4430_PRM_VP_MPU_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064)
6682339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET		0x0068
669c1294045SRajendra Nayak #define OMAP4430_PRM_VP_MPU_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068)
6702339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET		0x006c
671c1294045SRajendra Nayak #define OMAP4430_PRM_VP_MPU_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c)
6722339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET			0x0070
673c1294045SRajendra Nayak #define OMAP4430_PRM_VP_IVA_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070)
6742339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_STATUS_OFFSET			0x0074
675c1294045SRajendra Nayak #define OMAP4430_PRM_VP_IVA_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074)
6762339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET		0x0078
677c1294045SRajendra Nayak #define OMAP4430_PRM_VP_IVA_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078)
6782339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET			0x007c
679c1294045SRajendra Nayak #define OMAP4430_PRM_VP_IVA_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c)
6802339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET		0x0080
681c1294045SRajendra Nayak #define OMAP4430_PRM_VP_IVA_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080)
6822339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET		0x0084
683c1294045SRajendra Nayak #define OMAP4430_PRM_VP_IVA_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084)
6842339ea99SRajendra Nayak #define OMAP4_PRM_VC_SMPS_SA_OFFSET			0x0088
685c1294045SRajendra Nayak #define OMAP4430_PRM_VC_SMPS_SA				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088)
6862339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET		0x008c
687c1294045SRajendra Nayak #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c)
6882339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET		0x0090
689c1294045SRajendra Nayak #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090)
6902339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET		0x0094
691c1294045SRajendra Nayak #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094)
6922339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET		0x0098
693c1294045SRajendra Nayak #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098)
6942339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET		0x009c
695c1294045SRajendra Nayak #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c)
6962339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET			0x00a0
697c1294045SRajendra Nayak #define OMAP4430_PRM_VC_VAL_BYPASS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0)
6982339ea99SRajendra Nayak #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET			0x00a4
699c1294045SRajendra Nayak #define OMAP4430_PRM_VC_CFG_CHANNEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4)
7002339ea99SRajendra Nayak #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET		0x00a8
701c1294045SRajendra Nayak #define OMAP4430_PRM_VC_CFG_I2C_MODE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8)
7022339ea99SRajendra Nayak #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET			0x00ac
703c1294045SRajendra Nayak #define OMAP4430_PRM_VC_CFG_I2C_CLK			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac)
7042339ea99SRajendra Nayak #define OMAP4_PRM_SRAM_COUNT_OFFSET			0x00b0
705c1294045SRajendra Nayak #define OMAP4430_PRM_SRAM_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0)
7062339ea99SRajendra Nayak #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET		0x00b4
707c1294045SRajendra Nayak #define OMAP4430_PRM_SRAM_WKUP_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4)
7082339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET		0x00b8
709c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8)
7102339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET		0x00bc
711c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc)
7122339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET		0x00c0
713c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0)
7142339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET		0x00c4
715c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4)
7162339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET		0x00c8
717c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8)
7182339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET		0x00cc
719c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc)
7202339ea99SRajendra Nayak #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET		0x00d0
721c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_ABB_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0)
7222339ea99SRajendra Nayak #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET		0x00d4
723c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_ABB_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4)
7242339ea99SRajendra Nayak #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET		0x00d8
725c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_ABB_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
7262339ea99SRajendra Nayak #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET		0x00dc
727c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_ABB_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
728fdd4f409SRajendra Nayak #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET		0x00e0
729fdd4f409SRajendra Nayak #define OMAP4430_PRM_LDO_BANDGAP_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
7302339ea99SRajendra Nayak #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET		0x00e4
731c1294045SRajendra Nayak #define OMAP4430_PRM_DEVICE_OFF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
7322339ea99SRajendra Nayak #define OMAP4_PRM_PHASE1_CNDP_OFFSET			0x00e8
733c1294045SRajendra Nayak #define OMAP4430_PRM_PHASE1_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8)
7342339ea99SRajendra Nayak #define OMAP4_PRM_PHASE2A_CNDP_OFFSET			0x00ec
735c1294045SRajendra Nayak #define OMAP4430_PRM_PHASE2A_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec)
7362339ea99SRajendra Nayak #define OMAP4_PRM_PHASE2B_CNDP_OFFSET			0x00f0
737c1294045SRajendra Nayak #define OMAP4430_PRM_PHASE2B_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
7382339ea99SRajendra Nayak #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET			0x00f4
739c1294045SRajendra Nayak #define OMAP4430_PRM_MODEM_IF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
740fdd4f409SRajendra Nayak #define OMAP4_PRM_VC_ERRST_OFFSET			0x00f8
741fdd4f409SRajendra Nayak #define OMAP4430_PRM_VC_ERRST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8)
742c1294045SRajendra Nayak 
743*d198b514SPaul Walmsley /* Function prototypes */
744*d198b514SPaul Walmsley # ifndef __ASSEMBLER__
745c1294045SRajendra Nayak 
746*d198b514SPaul Walmsley extern u32 omap4_prm_read_mod_reg(s16 module, u16 idx);
747*d198b514SPaul Walmsley extern void omap4_prm_write_mod_reg(u32 val, s16 module, u16 idx);
748*d198b514SPaul Walmsley extern u32 omap4_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
749*d198b514SPaul Walmsley extern u32 omap4_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
750*d198b514SPaul Walmsley extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
751*d198b514SPaul Walmsley extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
752*d198b514SPaul Walmsley extern u32 omap4_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
753*d198b514SPaul Walmsley extern u32 omap4_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
754c1294045SRajendra Nayak 
755*d198b514SPaul Walmsley extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
756*d198b514SPaul Walmsley extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
757*d198b514SPaul Walmsley extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
758c1294045SRajendra Nayak 
759*d198b514SPaul Walmsley # endif
760c1294045SRajendra Nayak 
761c1294045SRajendra Nayak #endif
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