xref: /linux/arch/arm/mach-omap2/prm44xx.h (revision 2339ea99cc6bb6a6d36d02c641e21dc950f50360)
1c1294045SRajendra Nayak /*
2c1294045SRajendra Nayak  * OMAP44xx PRM instance offset macros
3c1294045SRajendra Nayak  *
479328706SBenoit Cousson  * Copyright (C) 2009-2010 Texas Instruments, Inc.
579328706SBenoit Cousson  * Copyright (C) 2009-2010 Nokia Corporation
6c1294045SRajendra Nayak  *
7c1294045SRajendra Nayak  * Paul Walmsley (paul@pwsan.com)
8c1294045SRajendra Nayak  * Rajendra Nayak (rnayak@ti.com)
9c1294045SRajendra Nayak  * Benoit Cousson (b-cousson@ti.com)
10c1294045SRajendra Nayak  *
11c1294045SRajendra Nayak  * This file is automatically generated from the OMAP hardware databases.
12c1294045SRajendra Nayak  * We respectfully ask that any modifications to this file be coordinated
13c1294045SRajendra Nayak  * with the public linux-omap@vger.kernel.org mailing list and the
14c1294045SRajendra Nayak  * authors above to ensure that the autogeneration scripts are kept
15c1294045SRajendra Nayak  * up-to-date with the file contents.
16c1294045SRajendra Nayak  *
17c1294045SRajendra Nayak  * This program is free software; you can redistribute it and/or modify
18c1294045SRajendra Nayak  * it under the terms of the GNU General Public License version 2 as
19c1294045SRajendra Nayak  * published by the Free Software Foundation.
20c1294045SRajendra Nayak  */
21c1294045SRajendra Nayak 
22c1294045SRajendra Nayak #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
23c1294045SRajendra Nayak #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
24c1294045SRajendra Nayak 
25c1294045SRajendra Nayak 
26c1294045SRajendra Nayak /* PRM */
27c1294045SRajendra Nayak 
28c1294045SRajendra Nayak /* PRM.OCP_SOCKET_PRM register offsets */
29*2339ea99SRajendra Nayak #define OMAP4_REVISION_PRM_OFFSET			0x0000
30c1294045SRajendra Nayak #define OMAP4430_REVISION_PRM				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000)
31*2339ea99SRajendra Nayak #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET			0x0010
32c1294045SRajendra Nayak #define OMAP4430_PRM_IRQSTATUS_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010)
33*2339ea99SRajendra Nayak #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET		0x0014
34c1294045SRajendra Nayak #define OMAP4430_PRM_IRQSTATUS_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014)
35*2339ea99SRajendra Nayak #define OMAP4_PRM_IRQENABLE_MPU_OFFSET			0x0018
36c1294045SRajendra Nayak #define OMAP4430_PRM_IRQENABLE_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018)
37*2339ea99SRajendra Nayak #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET		0x001c
38c1294045SRajendra Nayak #define OMAP4430_PRM_IRQENABLE_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c)
39*2339ea99SRajendra Nayak #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET		0x0020
40c1294045SRajendra Nayak #define OMAP4430_PRM_IRQSTATUS_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020)
41*2339ea99SRajendra Nayak #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET		0x0028
42c1294045SRajendra Nayak #define OMAP4430_PRM_IRQENABLE_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028)
43*2339ea99SRajendra Nayak #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET		0x0030
44c1294045SRajendra Nayak #define OMAP4430_PRM_IRQSTATUS_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
45*2339ea99SRajendra Nayak #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET		0x0038
46c1294045SRajendra Nayak #define OMAP4430_PRM_IRQENABLE_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
47*2339ea99SRajendra Nayak #define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET		0x0040
48c1294045SRajendra Nayak #define OMAP4430_PRM_PRM_PROFILING_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
49c1294045SRajendra Nayak 
50c1294045SRajendra Nayak /* PRM.CKGEN_PRM register offsets */
51*2339ea99SRajendra Nayak #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET		0x0000
52c1294045SRajendra Nayak #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
53*2339ea99SRajendra Nayak #define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET		0x0004
54c1294045SRajendra Nayak #define OMAP4430_CM_DPLL_SYS_REF_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004)
55*2339ea99SRajendra Nayak #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET			0x0008
56c1294045SRajendra Nayak #define OMAP4430_CM_L4_WKUP_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
57*2339ea99SRajendra Nayak #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET		0x000c
58c1294045SRajendra Nayak #define OMAP4430_CM_ABE_PLL_REF_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c)
59*2339ea99SRajendra Nayak #define OMAP4_CM_SYS_CLKSEL_OFFSET			0x0010
60c1294045SRajendra Nayak #define OMAP4430_CM_SYS_CLKSEL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010)
61c1294045SRajendra Nayak 
62c1294045SRajendra Nayak /* PRM.MPU_PRM register offsets */
63*2339ea99SRajendra Nayak #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET			0x0000
64c1294045SRajendra Nayak #define OMAP4430_PM_MPU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000)
65*2339ea99SRajendra Nayak #define OMAP4_PM_MPU_PWRSTST_OFFSET			0x0004
66c1294045SRajendra Nayak #define OMAP4430_PM_MPU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004)
67*2339ea99SRajendra Nayak #define OMAP4_RM_MPU_RSTST_OFFSET			0x0014
68c1294045SRajendra Nayak #define OMAP4430_RM_MPU_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014)
69*2339ea99SRajendra Nayak #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
70c1294045SRajendra Nayak #define OMAP4430_RM_MPU_MPU_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024)
71c1294045SRajendra Nayak 
72c1294045SRajendra Nayak /* PRM.TESLA_PRM register offsets */
73*2339ea99SRajendra Nayak #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET			0x0000
74c1294045SRajendra Nayak #define OMAP4430_PM_TESLA_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000)
75*2339ea99SRajendra Nayak #define OMAP4_PM_TESLA_PWRSTST_OFFSET			0x0004
76c1294045SRajendra Nayak #define OMAP4430_PM_TESLA_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004)
77*2339ea99SRajendra Nayak #define OMAP4_RM_TESLA_RSTCTRL_OFFSET			0x0010
78c1294045SRajendra Nayak #define OMAP4430_RM_TESLA_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010)
79*2339ea99SRajendra Nayak #define OMAP4_RM_TESLA_RSTST_OFFSET			0x0014
80c1294045SRajendra Nayak #define OMAP4430_RM_TESLA_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014)
81*2339ea99SRajendra Nayak #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET		0x0024
82c1294045SRajendra Nayak #define OMAP4430_RM_TESLA_TESLA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024)
83c1294045SRajendra Nayak 
84c1294045SRajendra Nayak /* PRM.ABE_PRM register offsets */
85*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET			0x0000
86c1294045SRajendra Nayak #define OMAP4430_PM_ABE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000)
87*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_PWRSTST_OFFSET			0x0004
88c1294045SRajendra Nayak #define OMAP4430_PM_ABE_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004)
89*2339ea99SRajendra Nayak #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET		0x002c
90c1294045SRajendra Nayak #define OMAP4430_RM_ABE_AESS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c)
91*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET			0x0030
92c1294045SRajendra Nayak #define OMAP4430_PM_ABE_PDM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030)
93*2339ea99SRajendra Nayak #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET			0x0034
94c1294045SRajendra Nayak #define OMAP4430_RM_ABE_PDM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034)
95*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET			0x0038
96c1294045SRajendra Nayak #define OMAP4430_PM_ABE_DMIC_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038)
97*2339ea99SRajendra Nayak #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET		0x003c
98c1294045SRajendra Nayak #define OMAP4430_RM_ABE_DMIC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c)
99*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET			0x0040
100c1294045SRajendra Nayak #define OMAP4430_PM_ABE_MCASP_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040)
101*2339ea99SRajendra Nayak #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET		0x0044
102c1294045SRajendra Nayak #define OMAP4430_RM_ABE_MCASP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044)
103*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET		0x0048
104c1294045SRajendra Nayak #define OMAP4430_PM_ABE_MCBSP1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048)
105*2339ea99SRajendra Nayak #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET		0x004c
106c1294045SRajendra Nayak #define OMAP4430_RM_ABE_MCBSP1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c)
107*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET		0x0050
108c1294045SRajendra Nayak #define OMAP4430_PM_ABE_MCBSP2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050)
109*2339ea99SRajendra Nayak #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET		0x0054
110c1294045SRajendra Nayak #define OMAP4430_RM_ABE_MCBSP2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054)
111*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET		0x0058
112c1294045SRajendra Nayak #define OMAP4430_PM_ABE_MCBSP3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058)
113*2339ea99SRajendra Nayak #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET		0x005c
114c1294045SRajendra Nayak #define OMAP4430_RM_ABE_MCBSP3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c)
115*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET		0x0060
116c1294045SRajendra Nayak #define OMAP4430_PM_ABE_SLIMBUS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060)
117*2339ea99SRajendra Nayak #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET		0x0064
118c1294045SRajendra Nayak #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064)
119*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET		0x0068
120c1294045SRajendra Nayak #define OMAP4430_PM_ABE_TIMER5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068)
121*2339ea99SRajendra Nayak #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET		0x006c
122c1294045SRajendra Nayak #define OMAP4430_RM_ABE_TIMER5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c)
123*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET		0x0070
124c1294045SRajendra Nayak #define OMAP4430_PM_ABE_TIMER6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070)
125*2339ea99SRajendra Nayak #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET		0x0074
126c1294045SRajendra Nayak #define OMAP4430_RM_ABE_TIMER6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074)
127*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET		0x0078
128c1294045SRajendra Nayak #define OMAP4430_PM_ABE_TIMER7_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078)
129*2339ea99SRajendra Nayak #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET		0x007c
130c1294045SRajendra Nayak #define OMAP4430_RM_ABE_TIMER7_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c)
131*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET		0x0080
132c1294045SRajendra Nayak #define OMAP4430_PM_ABE_TIMER8_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080)
133*2339ea99SRajendra Nayak #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET		0x0084
134c1294045SRajendra Nayak #define OMAP4430_RM_ABE_TIMER8_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084)
135*2339ea99SRajendra Nayak #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET			0x0088
136c1294045SRajendra Nayak #define OMAP4430_PM_ABE_WDT3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088)
137*2339ea99SRajendra Nayak #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET		0x008c
138c1294045SRajendra Nayak #define OMAP4430_RM_ABE_WDT3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c)
139c1294045SRajendra Nayak 
140c1294045SRajendra Nayak /* PRM.ALWAYS_ON_PRM register offsets */
141*2339ea99SRajendra Nayak #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET		0x0024
142c1294045SRajendra Nayak #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024)
143*2339ea99SRajendra Nayak #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET		0x0028
144c1294045SRajendra Nayak #define OMAP4430_PM_ALWON_SR_MPU_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028)
145*2339ea99SRajendra Nayak #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET		0x002c
146c1294045SRajendra Nayak #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c)
147*2339ea99SRajendra Nayak #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET		0x0030
148c1294045SRajendra Nayak #define OMAP4430_PM_ALWON_SR_IVA_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030)
149*2339ea99SRajendra Nayak #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET		0x0034
150c1294045SRajendra Nayak #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034)
151*2339ea99SRajendra Nayak #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET		0x0038
152c1294045SRajendra Nayak #define OMAP4430_PM_ALWON_SR_CORE_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038)
153*2339ea99SRajendra Nayak #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET		0x003c
154c1294045SRajendra Nayak #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c)
155c1294045SRajendra Nayak 
156c1294045SRajendra Nayak /* PRM.CORE_PRM register offsets */
157*2339ea99SRajendra Nayak #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET			0x0000
158c1294045SRajendra Nayak #define OMAP4430_PM_CORE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000)
159*2339ea99SRajendra Nayak #define OMAP4_PM_CORE_PWRSTST_OFFSET			0x0004
160c1294045SRajendra Nayak #define OMAP4430_PM_CORE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004)
161*2339ea99SRajendra Nayak #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET		0x0024
162c1294045SRajendra Nayak #define OMAP4430_RM_L3_1_L3_1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024)
163*2339ea99SRajendra Nayak #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET		0x0124
164c1294045SRajendra Nayak #define OMAP4430_RM_L3_2_L3_2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124)
165*2339ea99SRajendra Nayak #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET		0x012c
166c1294045SRajendra Nayak #define OMAP4430_RM_L3_2_GPMC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c)
167*2339ea99SRajendra Nayak #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET		0x0134
168c1294045SRajendra Nayak #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134)
169*2339ea99SRajendra Nayak #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET			0x0210
170c1294045SRajendra Nayak #define OMAP4430_RM_DUCATI_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210)
171*2339ea99SRajendra Nayak #define OMAP4_RM_DUCATI_RSTST_OFFSET			0x0214
172c1294045SRajendra Nayak #define OMAP4430_RM_DUCATI_RSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214)
173*2339ea99SRajendra Nayak #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET		0x0224
174c1294045SRajendra Nayak #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224)
175*2339ea99SRajendra Nayak #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET		0x0324
176c1294045SRajendra Nayak #define OMAP4430_RM_SDMA_SDMA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324)
177*2339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET		0x0424
178c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_DMM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424)
179*2339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET		0x042c
180c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c)
181*2339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET		0x0434
182c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434)
183*2339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET		0x043c
184c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c)
185*2339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET		0x0444
186c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_DLL_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444)
187*2339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET		0x0454
188c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454)
189*2339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET		0x045c
190c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c)
191*2339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET		0x0464
192c1294045SRajendra Nayak #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464)
193*2339ea99SRajendra Nayak #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET		0x0524
194c1294045SRajendra Nayak #define OMAP4430_RM_D2D_SAD2D_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524)
195*2339ea99SRajendra Nayak #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET		0x052c
196c1294045SRajendra Nayak #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c)
197*2339ea99SRajendra Nayak #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET		0x0534
198c1294045SRajendra Nayak #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534)
199*2339ea99SRajendra Nayak #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET		0x0624
200c1294045SRajendra Nayak #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624)
201*2339ea99SRajendra Nayak #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET		0x062c
202c1294045SRajendra Nayak #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c)
203*2339ea99SRajendra Nayak #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET		0x0634
204c1294045SRajendra Nayak #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634)
205*2339ea99SRajendra Nayak #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET		0x063c
206c1294045SRajendra Nayak #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c)
207*2339ea99SRajendra Nayak #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET		0x0724
208c1294045SRajendra Nayak #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724)
209*2339ea99SRajendra Nayak #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET	0x072c
210c1294045SRajendra Nayak #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c)
211*2339ea99SRajendra Nayak #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET		0x0744
212c1294045SRajendra Nayak #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744)
213c1294045SRajendra Nayak 
214c1294045SRajendra Nayak /* PRM.IVAHD_PRM register offsets */
215*2339ea99SRajendra Nayak #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET			0x0000
216c1294045SRajendra Nayak #define OMAP4430_PM_IVAHD_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000)
217*2339ea99SRajendra Nayak #define OMAP4_PM_IVAHD_PWRSTST_OFFSET			0x0004
218c1294045SRajendra Nayak #define OMAP4430_PM_IVAHD_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004)
219*2339ea99SRajendra Nayak #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET			0x0010
220c1294045SRajendra Nayak #define OMAP4430_RM_IVAHD_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010)
221*2339ea99SRajendra Nayak #define OMAP4_RM_IVAHD_RSTST_OFFSET			0x0014
222c1294045SRajendra Nayak #define OMAP4430_RM_IVAHD_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014)
223*2339ea99SRajendra Nayak #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET		0x0024
224c1294045SRajendra Nayak #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024)
225*2339ea99SRajendra Nayak #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET		0x002c
226c1294045SRajendra Nayak #define OMAP4430_RM_IVAHD_SL2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c)
227c1294045SRajendra Nayak 
228c1294045SRajendra Nayak /* PRM.CAM_PRM register offsets */
229*2339ea99SRajendra Nayak #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET			0x0000
230c1294045SRajendra Nayak #define OMAP4430_PM_CAM_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000)
231*2339ea99SRajendra Nayak #define OMAP4_PM_CAM_PWRSTST_OFFSET			0x0004
232c1294045SRajendra Nayak #define OMAP4430_PM_CAM_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004)
233*2339ea99SRajendra Nayak #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET			0x0024
234c1294045SRajendra Nayak #define OMAP4430_RM_CAM_ISS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024)
235*2339ea99SRajendra Nayak #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET		0x002c
236c1294045SRajendra Nayak #define OMAP4430_RM_CAM_FDIF_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c)
237c1294045SRajendra Nayak 
238c1294045SRajendra Nayak /* PRM.DSS_PRM register offsets */
239*2339ea99SRajendra Nayak #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET			0x0000
240c1294045SRajendra Nayak #define OMAP4430_PM_DSS_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000)
241*2339ea99SRajendra Nayak #define OMAP4_PM_DSS_PWRSTST_OFFSET			0x0004
242c1294045SRajendra Nayak #define OMAP4430_PM_DSS_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004)
243*2339ea99SRajendra Nayak #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET			0x0020
244c1294045SRajendra Nayak #define OMAP4430_PM_DSS_DSS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020)
245*2339ea99SRajendra Nayak #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
246c1294045SRajendra Nayak #define OMAP4430_RM_DSS_DSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024)
247*2339ea99SRajendra Nayak #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET		0x002c
248c1294045SRajendra Nayak #define OMAP4430_RM_DSS_DEISS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c)
249c1294045SRajendra Nayak 
250c1294045SRajendra Nayak /* PRM.GFX_PRM register offsets */
251*2339ea99SRajendra Nayak #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET			0x0000
252c1294045SRajendra Nayak #define OMAP4430_PM_GFX_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000)
253*2339ea99SRajendra Nayak #define OMAP4_PM_GFX_PWRSTST_OFFSET			0x0004
254c1294045SRajendra Nayak #define OMAP4430_PM_GFX_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004)
255*2339ea99SRajendra Nayak #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET			0x0024
256c1294045SRajendra Nayak #define OMAP4430_RM_GFX_GFX_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024)
257c1294045SRajendra Nayak 
258c1294045SRajendra Nayak /* PRM.L3INIT_PRM register offsets */
259*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET		0x0000
260c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000)
261*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_PWRSTST_OFFSET			0x0004
262c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004)
263*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET		0x0028
264c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_MMC1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028)
265*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET		0x002c
266c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_MMC1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c)
267*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET		0x0030
268c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_MMC2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030)
269*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET		0x0034
270c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_MMC2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034)
271*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET		0x0038
272c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_HSI_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038)
273*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET		0x003c
274c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_HSI_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c)
275*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET		0x0040
276c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040)
277*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET		0x0044
278c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044)
279*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET		0x0058
280c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058)
281*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET		0x005c
282c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c)
283*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET		0x0060
284c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060)
285*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET		0x0064
286c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064)
287*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET		0x0068
288c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068)
289*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET		0x006c
290c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c)
291*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET		0x007c
292c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_P1500_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c)
293*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET		0x0084
294c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_EMAC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084)
295*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET		0x0088
296c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_SATA_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088)
297*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET		0x008c
298c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_SATA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c)
299*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET		0x0094
300c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094)
301*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET		0x0098
302c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_PCIESS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098)
303*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET		0x009c
304c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c)
305*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET		0x00ac
306c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac)
307*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET		0x00c0
308c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_XHPI_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0)
309*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET		0x00c4
310c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_XHPI_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4)
311*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET		0x00c8
312c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_MMC6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8)
313*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET		0x00cc
314c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_MMC6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc)
315*2339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET	0x00d0
316c1294045SRajendra Nayak #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0)
317*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET	0x00d4
318c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4)
319*2339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET	0x00e4
320c1294045SRajendra Nayak #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4)
321c1294045SRajendra Nayak 
322c1294045SRajendra Nayak /* PRM.L4PER_PRM register offsets */
323*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET			0x0000
324c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000)
325*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_PWRSTST_OFFSET			0x0004
326c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004)
327*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET		0x0024
328c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_ADC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024)
329*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET		0x0028
330c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028)
331*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET		0x002c
332c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c)
333*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET		0x0030
334c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030)
335*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET		0x0034
336c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034)
337*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET		0x0038
338c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038)
339*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET		0x003c
340c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c)
341*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET		0x0040
342c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040)
343*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET		0x0044
344c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044)
345*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET		0x0048
346c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048)
347*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET		0x004c
348c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c)
349*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET		0x0050
350c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050)
351*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET		0x0054
352c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054)
353*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET		0x005c
354c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_ELM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c)
355*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET		0x0060
356c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_GPIO2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060)
357*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET		0x0064
358c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_GPIO2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064)
359*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET		0x0068
360c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_GPIO3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068)
361*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET		0x006c
362c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_GPIO3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c)
363*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET		0x0070
364c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_GPIO4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070)
365*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET		0x0074
366c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_GPIO4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074)
367*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET		0x0078
368c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_GPIO5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078)
369*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET		0x007c
370c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_GPIO5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c)
371*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET		0x0080
372c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_GPIO6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080)
373*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET		0x0084
374c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_GPIO6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084)
375*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET		0x008c
376c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c)
377*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET		0x0090
378c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_HECC1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090)
379*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET		0x0094
380c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_HECC1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094)
381*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET		0x0098
382c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_HECC2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098)
383*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET		0x009c
384c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_HECC2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c)
385*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET		0x00a0
386c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_I2C1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0)
387*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET		0x00a4
388c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_I2C1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4)
389*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET		0x00a8
390c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_I2C2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8)
391*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET		0x00ac
392c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_I2C2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac)
393*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET		0x00b0
394c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_I2C3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0)
395*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET		0x00b4
396c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_I2C3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4)
397*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET		0x00b8
398c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_I2C4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8)
399*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET		0x00bc
400c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_I2C4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc)
401*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET		0x00c0
402c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_L4_PER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0)
403*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET		0x00d0
404c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCASP2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0)
405*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET		0x00d4
406c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCASP2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4)
407*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET		0x00d8
408c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCASP3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8)
409*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET		0x00dc
410c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCASP3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc)
411*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET		0x00e0
412c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCBSP4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0)
413*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET		0x00e4
414c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4)
415*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET		0x00ec
416c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MGATE_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec)
417*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET		0x00f0
418c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCSPI1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0)
419*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET		0x00f4
420c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4)
421*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET		0x00f8
422c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCSPI2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8)
423*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET		0x00fc
424c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc)
425*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET		0x0100
426c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCSPI3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100)
427*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET		0x0104
428c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104)
429*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET		0x0108
430c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MCSPI4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108)
431*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET		0x010c
432c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c)
433*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET		0x0120
434c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MMCSD3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120)
435*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET		0x0124
436c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124)
437*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET		0x0128
438c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MMCSD4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128)
439*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET		0x012c
440c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c)
441*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET		0x0134
442c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134)
443*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET		0x0138
444c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138)
445*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET		0x013c
446c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c)
447*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET		0x0140
448c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_UART1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140)
449*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET		0x0144
450c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_UART1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144)
451*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET		0x0148
452c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_UART2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148)
453*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET		0x014c
454c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_UART2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c)
455*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET		0x0150
456c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_UART3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150)
457*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET		0x0154
458c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_UART3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154)
459*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET		0x0158
460c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_UART4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158)
461*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET		0x015c
462c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_UART4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c)
463*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET		0x0160
464c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_MMCSD5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160)
465*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET		0x0164
466c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164)
467*2339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET		0x0168
468c1294045SRajendra Nayak #define OMAP4430_PM_L4PER_I2C5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168)
469*2339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET		0x016c
470c1294045SRajendra Nayak #define OMAP4430_RM_L4PER_I2C5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c)
471*2339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET		0x01a4
472c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_AES1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4)
473*2339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET		0x01ac
474c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_AES2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac)
475*2339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET		0x01b4
476c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4)
477*2339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET		0x01bc
478c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc)
479*2339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET		0x01c4
480c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_RNG_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4)
481*2339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET		0x01cc
482c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc)
483*2339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET		0x01dc
484c1294045SRajendra Nayak #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc)
485c1294045SRajendra Nayak 
486c1294045SRajendra Nayak /* PRM.CEFUSE_PRM register offsets */
487*2339ea99SRajendra Nayak #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET		0x0000
488c1294045SRajendra Nayak #define OMAP4430_PM_CEFUSE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000)
489*2339ea99SRajendra Nayak #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET			0x0004
490c1294045SRajendra Nayak #define OMAP4430_PM_CEFUSE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004)
491*2339ea99SRajendra Nayak #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET		0x0024
492c1294045SRajendra Nayak #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024)
493c1294045SRajendra Nayak 
494c1294045SRajendra Nayak /* PRM.WKUP_PRM register offsets */
495*2339ea99SRajendra Nayak #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET		0x0024
496c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024)
497*2339ea99SRajendra Nayak #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET		0x002c
498c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_WDT1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c)
499*2339ea99SRajendra Nayak #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET			0x0030
500c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_WDT2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030)
501*2339ea99SRajendra Nayak #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET		0x0034
502c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_WDT2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034)
503*2339ea99SRajendra Nayak #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET		0x0038
504c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_GPIO1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038)
505*2339ea99SRajendra Nayak #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET		0x003c
506c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_GPIO1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c)
507*2339ea99SRajendra Nayak #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET		0x0040
508c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_TIMER1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040)
509*2339ea99SRajendra Nayak #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET		0x0044
510c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_TIMER1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044)
511*2339ea99SRajendra Nayak #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET		0x0048
512c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_TIMER12_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048)
513*2339ea99SRajendra Nayak #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET		0x004c
514c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_TIMER12_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c)
515*2339ea99SRajendra Nayak #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET		0x0054
516c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054)
517*2339ea99SRajendra Nayak #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET			0x0058
518c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_USIM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058)
519*2339ea99SRajendra Nayak #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET		0x005c
520c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_USIM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c)
521*2339ea99SRajendra Nayak #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET		0x0064
522c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_SARRAM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064)
523*2339ea99SRajendra Nayak #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET		0x0078
524c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078)
525*2339ea99SRajendra Nayak #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET		0x007c
526c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c)
527*2339ea99SRajendra Nayak #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET			0x0080
528c1294045SRajendra Nayak #define OMAP4430_PM_WKUP_RTC_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080)
529*2339ea99SRajendra Nayak #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET		0x0084
530c1294045SRajendra Nayak #define OMAP4430_RM_WKUP_RTC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084)
531c1294045SRajendra Nayak 
532c1294045SRajendra Nayak /* PRM.WKUP_CM register offsets */
533*2339ea99SRajendra Nayak #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
534c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000)
535*2339ea99SRajendra Nayak #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x0020
536c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020)
537*2339ea99SRajendra Nayak #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x0028
538c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_WDT1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028)
539*2339ea99SRajendra Nayak #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET		0x0030
540c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_WDT2_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030)
541*2339ea99SRajendra Nayak #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET		0x0038
542c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038)
543*2339ea99SRajendra Nayak #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x0040
544c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040)
545*2339ea99SRajendra Nayak #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET		0x0048
546c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048)
547*2339ea99SRajendra Nayak #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET		0x0050
548c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050)
549*2339ea99SRajendra Nayak #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET		0x0058
550c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_USIM_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058)
551*2339ea99SRajendra Nayak #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET		0x0060
552c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060)
553*2339ea99SRajendra Nayak #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET		0x0078
554c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078)
555*2339ea99SRajendra Nayak #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET		0x0080
556c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_RTC_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080)
557*2339ea99SRajendra Nayak #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET		0x0088
558c1294045SRajendra Nayak #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088)
559c1294045SRajendra Nayak 
560c1294045SRajendra Nayak /* PRM.EMU_PRM register offsets */
561*2339ea99SRajendra Nayak #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET			0x0000
562c1294045SRajendra Nayak #define OMAP4430_PM_EMU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000)
563*2339ea99SRajendra Nayak #define OMAP4_PM_EMU_PWRSTST_OFFSET			0x0004
564c1294045SRajendra Nayak #define OMAP4430_PM_EMU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004)
565*2339ea99SRajendra Nayak #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET		0x0024
566c1294045SRajendra Nayak #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024)
567c1294045SRajendra Nayak 
568c1294045SRajendra Nayak /* PRM.EMU_CM register offsets */
569*2339ea99SRajendra Nayak #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET			0x0000
570c1294045SRajendra Nayak #define OMAP4430_CM_EMU_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000)
571*2339ea99SRajendra Nayak #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET			0x0008
572c1294045SRajendra Nayak #define OMAP4430_CM_EMU_DYNAMICDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008)
573*2339ea99SRajendra Nayak #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET		0x0020
574c1294045SRajendra Nayak #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020)
575c1294045SRajendra Nayak 
576c1294045SRajendra Nayak /* PRM.DEVICE_PRM register offsets */
577*2339ea99SRajendra Nayak #define OMAP4_PRM_RSTCTRL_OFFSET			0x0000
578c1294045SRajendra Nayak #define OMAP4430_PRM_RSTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000)
579*2339ea99SRajendra Nayak #define OMAP4_PRM_RSTST_OFFSET				0x0004
580c1294045SRajendra Nayak #define OMAP4430_PRM_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004)
581*2339ea99SRajendra Nayak #define OMAP4_PRM_RSTTIME_OFFSET			0x0008
582c1294045SRajendra Nayak #define OMAP4430_PRM_RSTTIME				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008)
583*2339ea99SRajendra Nayak #define OMAP4_PRM_CLKREQCTRL_OFFSET			0x000c
584c1294045SRajendra Nayak #define OMAP4430_PRM_CLKREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c)
585*2339ea99SRajendra Nayak #define OMAP4_PRM_VOLTCTRL_OFFSET			0x0010
586c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010)
587*2339ea99SRajendra Nayak #define OMAP4_PRM_PWRREQCTRL_OFFSET			0x0014
588c1294045SRajendra Nayak #define OMAP4430_PRM_PWRREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014)
589*2339ea99SRajendra Nayak #define OMAP4_PRM_PSCON_COUNT_OFFSET			0x0018
590c1294045SRajendra Nayak #define OMAP4430_PRM_PSCON_COUNT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018)
591*2339ea99SRajendra Nayak #define OMAP4_PRM_IO_COUNT_OFFSET			0x001c
592c1294045SRajendra Nayak #define OMAP4430_PRM_IO_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c)
593*2339ea99SRajendra Nayak #define OMAP4_PRM_IO_PMCTRL_OFFSET			0x0020
594c1294045SRajendra Nayak #define OMAP4430_PRM_IO_PMCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020)
595*2339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET		0x0024
596c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_WARMRESET		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024)
597*2339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET		0x0028
598c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_CORE_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028)
599*2339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET		0x002c
600c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_MPU_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c)
601*2339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET		0x0030
602c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_IVA_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030)
603*2339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET	0x0034
604c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034)
605*2339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET	0x0038
606c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038)
607*2339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET	0x003c
608c1294045SRajendra Nayak #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c)
609*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET			0x0040
610c1294045SRajendra Nayak #define OMAP4430_PRM_VP_CORE_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040)
611*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_STATUS_OFFSET			0x0044
612c1294045SRajendra Nayak #define OMAP4430_PRM_VP_CORE_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044)
613*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET		0x0048
614c1294045SRajendra Nayak #define OMAP4430_PRM_VP_CORE_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048)
615*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET		0x004c
616c1294045SRajendra Nayak #define OMAP4430_PRM_VP_CORE_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c)
617*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET		0x0050
618c1294045SRajendra Nayak #define OMAP4430_PRM_VP_CORE_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050)
619*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET		0x0054
620c1294045SRajendra Nayak #define OMAP4430_PRM_VP_CORE_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054)
621*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET			0x0058
622c1294045SRajendra Nayak #define OMAP4430_PRM_VP_MPU_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058)
623*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_STATUS_OFFSET			0x005c
624c1294045SRajendra Nayak #define OMAP4430_PRM_VP_MPU_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c)
625*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET		0x0060
626c1294045SRajendra Nayak #define OMAP4430_PRM_VP_MPU_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060)
627*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET			0x0064
628c1294045SRajendra Nayak #define OMAP4430_PRM_VP_MPU_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064)
629*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET		0x0068
630c1294045SRajendra Nayak #define OMAP4430_PRM_VP_MPU_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068)
631*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET		0x006c
632c1294045SRajendra Nayak #define OMAP4430_PRM_VP_MPU_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c)
633*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET			0x0070
634c1294045SRajendra Nayak #define OMAP4430_PRM_VP_IVA_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070)
635*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_STATUS_OFFSET			0x0074
636c1294045SRajendra Nayak #define OMAP4430_PRM_VP_IVA_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074)
637*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET		0x0078
638c1294045SRajendra Nayak #define OMAP4430_PRM_VP_IVA_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078)
639*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET			0x007c
640c1294045SRajendra Nayak #define OMAP4430_PRM_VP_IVA_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c)
641*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET		0x0080
642c1294045SRajendra Nayak #define OMAP4430_PRM_VP_IVA_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080)
643*2339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET		0x0084
644c1294045SRajendra Nayak #define OMAP4430_PRM_VP_IVA_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084)
645*2339ea99SRajendra Nayak #define OMAP4_PRM_VC_SMPS_SA_OFFSET			0x0088
646c1294045SRajendra Nayak #define OMAP4430_PRM_VC_SMPS_SA				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088)
647*2339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET		0x008c
648c1294045SRajendra Nayak #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c)
649*2339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET		0x0090
650c1294045SRajendra Nayak #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090)
651*2339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET		0x0094
652c1294045SRajendra Nayak #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094)
653*2339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET		0x0098
654c1294045SRajendra Nayak #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098)
655*2339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET		0x009c
656c1294045SRajendra Nayak #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c)
657*2339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET			0x00a0
658c1294045SRajendra Nayak #define OMAP4430_PRM_VC_VAL_BYPASS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0)
659*2339ea99SRajendra Nayak #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET			0x00a4
660c1294045SRajendra Nayak #define OMAP4430_PRM_VC_CFG_CHANNEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4)
661*2339ea99SRajendra Nayak #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET		0x00a8
662c1294045SRajendra Nayak #define OMAP4430_PRM_VC_CFG_I2C_MODE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8)
663*2339ea99SRajendra Nayak #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET			0x00ac
664c1294045SRajendra Nayak #define OMAP4430_PRM_VC_CFG_I2C_CLK			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac)
665*2339ea99SRajendra Nayak #define OMAP4_PRM_SRAM_COUNT_OFFSET			0x00b0
666c1294045SRajendra Nayak #define OMAP4430_PRM_SRAM_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0)
667*2339ea99SRajendra Nayak #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET		0x00b4
668c1294045SRajendra Nayak #define OMAP4430_PRM_SRAM_WKUP_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4)
669*2339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET		0x00b8
670c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8)
671*2339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET		0x00bc
672c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc)
673*2339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET		0x00c0
674c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0)
675*2339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET		0x00c4
676c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4)
677*2339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET		0x00c8
678c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8)
679*2339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET		0x00cc
680c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc)
681*2339ea99SRajendra Nayak #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET		0x00d0
682c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_ABB_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0)
683*2339ea99SRajendra Nayak #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET		0x00d4
684c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_ABB_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4)
685*2339ea99SRajendra Nayak #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET		0x00d8
686c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_ABB_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
687*2339ea99SRajendra Nayak #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET		0x00dc
688c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_ABB_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
689*2339ea99SRajendra Nayak #define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET		0x00e0
690c1294045SRajendra Nayak #define OMAP4430_PRM_LDO_BANDGAP_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
691*2339ea99SRajendra Nayak #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET		0x00e4
692c1294045SRajendra Nayak #define OMAP4430_PRM_DEVICE_OFF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
693*2339ea99SRajendra Nayak #define OMAP4_PRM_PHASE1_CNDP_OFFSET			0x00e8
694c1294045SRajendra Nayak #define OMAP4430_PRM_PHASE1_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8)
695*2339ea99SRajendra Nayak #define OMAP4_PRM_PHASE2A_CNDP_OFFSET			0x00ec
696c1294045SRajendra Nayak #define OMAP4430_PRM_PHASE2A_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec)
697*2339ea99SRajendra Nayak #define OMAP4_PRM_PHASE2B_CNDP_OFFSET			0x00f0
698c1294045SRajendra Nayak #define OMAP4430_PRM_PHASE2B_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
699*2339ea99SRajendra Nayak #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET			0x00f4
700c1294045SRajendra Nayak #define OMAP4430_PRM_MODEM_IF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
701c1294045SRajendra Nayak 
70279328706SBenoit Cousson /*
70379328706SBenoit Cousson  * PRCM_MPU
70479328706SBenoit Cousson  *
70579328706SBenoit Cousson  * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
70679328706SBenoit Cousson  * point of view the PRCM_MPU is a single entity. It shares the same
70779328706SBenoit Cousson  * programming model as the global PRCM and thus can be assimilate as two new
70879328706SBenoit Cousson  * MOD inside the PRCM
70979328706SBenoit Cousson  */
710c1294045SRajendra Nayak 
71179328706SBenoit Cousson /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
712*2339ea99SRajendra Nayak #define OMAP4_REVISION_PRCM_OFFSET			0x0000
71379328706SBenoit Cousson #define OMAP4430_REVISION_PRCM				OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000)
714c1294045SRajendra Nayak 
71579328706SBenoit Cousson /* PRCM_MPU.DEVICE_PRM register offsets */
716*2339ea99SRajendra Nayak #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET			0x0000
71779328706SBenoit Cousson #define OMAP4430_PRCM_MPU_PRM_RSTST			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
718c1294045SRajendra Nayak 
71979328706SBenoit Cousson /* PRCM_MPU.CPU0 register offsets */
720*2339ea99SRajendra Nayak #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET			0x0000
72179328706SBenoit Cousson #define OMAP4430_PM_CPU0_PWRSTCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000)
722*2339ea99SRajendra Nayak #define OMAP4_PM_CPU0_PWRSTST_OFFSET			0x0004
72379328706SBenoit Cousson #define OMAP4430_PM_CPU0_PWRSTST			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004)
724*2339ea99SRajendra Nayak #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET		0x0008
72579328706SBenoit Cousson #define OMAP4430_RM_CPU0_CPU0_CONTEXT			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008)
726*2339ea99SRajendra Nayak #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET		0x000c
72779328706SBenoit Cousson #define OMAP4430_RM_CPU0_CPU0_RSTCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c)
728*2339ea99SRajendra Nayak #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET			0x0010
72979328706SBenoit Cousson #define OMAP4430_RM_CPU0_CPU0_RSTST			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010)
730*2339ea99SRajendra Nayak #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET		0x0014
73179328706SBenoit Cousson #define OMAP4430_CM_CPU0_CPU0_CLKCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014)
732*2339ea99SRajendra Nayak #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET			0x0018
73379328706SBenoit Cousson #define OMAP4430_CM_CPU0_CLKSTCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018)
734c1294045SRajendra Nayak 
73579328706SBenoit Cousson /* PRCM_MPU.CPU1 register offsets */
736*2339ea99SRajendra Nayak #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET			0x0000
73779328706SBenoit Cousson #define OMAP4430_PM_CPU1_PWRSTCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000)
738*2339ea99SRajendra Nayak #define OMAP4_PM_CPU1_PWRSTST_OFFSET			0x0004
73979328706SBenoit Cousson #define OMAP4430_PM_CPU1_PWRSTST			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004)
740*2339ea99SRajendra Nayak #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET		0x0008
74179328706SBenoit Cousson #define OMAP4430_RM_CPU1_CPU1_CONTEXT			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008)
742*2339ea99SRajendra Nayak #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET		0x000c
74379328706SBenoit Cousson #define OMAP4430_RM_CPU1_CPU1_RSTCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c)
744*2339ea99SRajendra Nayak #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET			0x0010
74579328706SBenoit Cousson #define OMAP4430_RM_CPU1_CPU1_RSTST			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010)
746*2339ea99SRajendra Nayak #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET		0x0014
74779328706SBenoit Cousson #define OMAP4430_CM_CPU1_CPU1_CLKCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014)
748*2339ea99SRajendra Nayak #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET			0x0018
74979328706SBenoit Cousson #define OMAP4430_CM_CPU1_CLKSTCTRL			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018)
750c1294045SRajendra Nayak #endif
751