1 /* 2 * OMAP4 PRM module functions 3 * 4 * Copyright (C) 2011 Texas Instruments, Inc. 5 * Copyright (C) 2010 Nokia Corporation 6 * Benoît Cousson 7 * Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/delay.h> 16 #include <linux/errno.h> 17 #include <linux/err.h> 18 #include <linux/io.h> 19 20 #include "common.h" 21 #include <plat/cpu.h> 22 #include <plat/prcm.h> 23 24 #include "vp.h" 25 #include "prm44xx.h" 26 #include "prm-regbits-44xx.h" 27 #include "prcm44xx.h" 28 #include "prminst44xx.h" 29 30 static const struct omap_prcm_irq omap4_prcm_irqs[] = { 31 OMAP_PRCM_IRQ("wkup", 0, 0), 32 OMAP_PRCM_IRQ("io", 9, 1), 33 }; 34 35 static struct omap_prcm_irq_setup omap4_prcm_irq_setup = { 36 .ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, 37 .mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET, 38 .nr_regs = 2, 39 .irqs = omap4_prcm_irqs, 40 .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs), 41 .irq = OMAP44XX_IRQ_PRCM, 42 .read_pending_irqs = &omap44xx_prm_read_pending_irqs, 43 .ocp_barrier = &omap44xx_prm_ocp_barrier, 44 .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen, 45 .restore_irqen = &omap44xx_prm_restore_irqen, 46 }; 47 48 /* PRM low-level functions */ 49 50 /* Read a register in a CM/PRM instance in the PRM module */ 51 u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) 52 { 53 return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg)); 54 } 55 56 /* Write into a register in a CM/PRM instance in the PRM module */ 57 void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) 58 { 59 __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg)); 60 } 61 62 /* Read-modify-write a register in a PRM module. Caller must lock */ 63 u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) 64 { 65 u32 v; 66 67 v = omap4_prm_read_inst_reg(inst, reg); 68 v &= ~mask; 69 v |= bits; 70 omap4_prm_write_inst_reg(v, inst, reg); 71 72 return v; 73 } 74 75 /* PRM VP */ 76 77 /* 78 * struct omap4_vp - OMAP4 VP register access description. 79 * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP 80 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg 81 */ 82 struct omap4_vp { 83 u32 irqstatus_mpu; 84 u32 tranxdone_status; 85 }; 86 87 static struct omap4_vp omap4_vp[] = { 88 [OMAP4_VP_VDD_MPU_ID] = { 89 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET, 90 .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK, 91 }, 92 [OMAP4_VP_VDD_IVA_ID] = { 93 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, 94 .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK, 95 }, 96 [OMAP4_VP_VDD_CORE_ID] = { 97 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, 98 .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK, 99 }, 100 }; 101 102 u32 omap4_prm_vp_check_txdone(u8 vp_id) 103 { 104 struct omap4_vp *vp = &omap4_vp[vp_id]; 105 u32 irqstatus; 106 107 irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 108 OMAP4430_PRM_OCP_SOCKET_INST, 109 vp->irqstatus_mpu); 110 return irqstatus & vp->tranxdone_status; 111 } 112 113 void omap4_prm_vp_clear_txdone(u8 vp_id) 114 { 115 struct omap4_vp *vp = &omap4_vp[vp_id]; 116 117 omap4_prminst_write_inst_reg(vp->tranxdone_status, 118 OMAP4430_PRM_PARTITION, 119 OMAP4430_PRM_OCP_SOCKET_INST, 120 vp->irqstatus_mpu); 121 }; 122 123 u32 omap4_prm_vcvp_read(u8 offset) 124 { 125 return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 126 OMAP4430_PRM_DEVICE_INST, offset); 127 } 128 129 void omap4_prm_vcvp_write(u32 val, u8 offset) 130 { 131 omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, 132 OMAP4430_PRM_DEVICE_INST, offset); 133 } 134 135 u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) 136 { 137 return omap4_prminst_rmw_inst_reg_bits(mask, bits, 138 OMAP4430_PRM_PARTITION, 139 OMAP4430_PRM_DEVICE_INST, 140 offset); 141 } 142 143 static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs) 144 { 145 u32 mask, st; 146 147 /* XXX read mask from RAM? */ 148 mask = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqen_offs); 149 st = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqst_offs); 150 151 return mask & st; 152 } 153 154 /** 155 * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events 156 * @events: ptr to two consecutive u32s, preallocated by caller 157 * 158 * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM 159 * MPU IRQs, and store the result into the two u32s pointed to by @events. 160 * No return value. 161 */ 162 void omap44xx_prm_read_pending_irqs(unsigned long *events) 163 { 164 events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET, 165 OMAP4_PRM_IRQSTATUS_MPU_OFFSET); 166 167 events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET, 168 OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); 169 } 170 171 /** 172 * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete 173 * 174 * Force any buffered writes to the PRM IP block to complete. Needed 175 * by the PRM IRQ handler, which reads and writes directly to the IP 176 * block, to avoid race conditions after acknowledging or clearing IRQ 177 * bits. No return value. 178 */ 179 void omap44xx_prm_ocp_barrier(void) 180 { 181 omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, 182 OMAP4_REVISION_PRM_OFFSET); 183 } 184 185 /** 186 * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs 187 * @saved_mask: ptr to a u32 array to save IRQENABLE bits 188 * 189 * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to 190 * @saved_mask. @saved_mask must be allocated by the caller. 191 * Intended to be used in the PRM interrupt handler suspend callback. 192 * The OCP barrier is needed to ensure the write to disable PRM 193 * interrupts reaches the PRM before returning; otherwise, spurious 194 * interrupts might occur. No return value. 195 */ 196 void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) 197 { 198 saved_mask[0] = 199 omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, 200 OMAP4_PRM_IRQSTATUS_MPU_OFFSET); 201 saved_mask[1] = 202 omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, 203 OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); 204 205 omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST, 206 OMAP4_PRM_IRQENABLE_MPU_OFFSET); 207 omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST, 208 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); 209 210 /* OCP barrier */ 211 omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, 212 OMAP4_REVISION_PRM_OFFSET); 213 } 214 215 /** 216 * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args 217 * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously 218 * 219 * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from 220 * @saved_mask. Intended to be used in the PRM interrupt handler resume 221 * callback to restore values saved by omap44xx_prm_save_and_clear_irqen(). 222 * No OCP barrier should be needed here; any pending PRM interrupts will fire 223 * once the writes reach the PRM. No return value. 224 */ 225 void omap44xx_prm_restore_irqen(u32 *saved_mask) 226 { 227 omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_DEVICE_INST, 228 OMAP4_PRM_IRQENABLE_MPU_OFFSET); 229 omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_DEVICE_INST, 230 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); 231 } 232 233 static int __init omap4xxx_prcm_init(void) 234 { 235 if (cpu_is_omap44xx()) 236 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); 237 return 0; 238 } 239 subsys_initcall(omap4xxx_prcm_init); 240