1234f0c4cSRajendra Nayak /* 2234f0c4cSRajendra Nayak * OMAP44xx Power Management register bits 3234f0c4cSRajendra Nayak * 4568997cfSRajendra Nayak * Copyright (C) 2009-2010 Texas Instruments, Inc. 5568997cfSRajendra Nayak * Copyright (C) 2009-2010 Nokia Corporation 6234f0c4cSRajendra Nayak * 7234f0c4cSRajendra Nayak * Paul Walmsley (paul@pwsan.com) 8234f0c4cSRajendra Nayak * Rajendra Nayak (rnayak@ti.com) 9234f0c4cSRajendra Nayak * Benoit Cousson (b-cousson@ti.com) 10234f0c4cSRajendra Nayak * 11234f0c4cSRajendra Nayak * This file is automatically generated from the OMAP hardware databases. 12234f0c4cSRajendra Nayak * We respectfully ask that any modifications to this file be coordinated 13234f0c4cSRajendra Nayak * with the public linux-omap@vger.kernel.org mailing list and the 14234f0c4cSRajendra Nayak * authors above to ensure that the autogeneration scripts are kept 15234f0c4cSRajendra Nayak * up-to-date with the file contents. 16234f0c4cSRajendra Nayak * 17234f0c4cSRajendra Nayak * This program is free software; you can redistribute it and/or modify 18234f0c4cSRajendra Nayak * it under the terms of the GNU General Public License version 2 as 19234f0c4cSRajendra Nayak * published by the Free Software Foundation. 20234f0c4cSRajendra Nayak */ 21234f0c4cSRajendra Nayak 22234f0c4cSRajendra Nayak #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 23234f0c4cSRajendra Nayak #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 24234f0c4cSRajendra Nayak 25568997cfSRajendra Nayak #define OMAP4430_C2C_RST_SHIFT 10 26568997cfSRajendra Nayak #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) 27568997cfSRajendra Nayak #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) 28568997cfSRajendra Nayak #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) 2956ef28acSRajendra Nayak #define OMAP4430_DATA_SHIFT 16 30568997cfSRajendra Nayak #define OMAP4430_ERRORGAIN_MASK (0xff << 16) 31568997cfSRajendra Nayak #define OMAP4430_ERROROFFSET_MASK (0xff << 24) 3256ef28acSRajendra Nayak #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 33568997cfSRajendra Nayak #define OMAP4430_FORCEUPDATE_MASK (1 << 1) 3456ef28acSRajendra Nayak #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 3556ef28acSRajendra Nayak #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 36568997cfSRajendra Nayak #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) 37568997cfSRajendra Nayak #define OMAP4430_HSMCODE_MASK (0x7 << 0) 38*102bcb6eSTony Lindgren #define OMAP4430_SRMODEEN_MASK (1 << 4) 39568997cfSRajendra Nayak #define OMAP4430_HSMODEEN_MASK (1 << 3) 4056ef28acSRajendra Nayak #define OMAP4430_HSSCLL_SHIFT 24 4156ef28acSRajendra Nayak #define OMAP4430_ICEPICK_RST_SHIFT 9 42568997cfSRajendra Nayak #define OMAP4430_INITVDD_MASK (1 << 2) 43568997cfSRajendra Nayak #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) 44568997cfSRajendra Nayak #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 45568997cfSRajendra Nayak #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) 4656ef28acSRajendra Nayak #define OMAP4430_LOGICRETSTATE_SHIFT 2 47568997cfSRajendra Nayak #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) 4856ef28acSRajendra Nayak #define OMAP4430_LOGICSTATEST_SHIFT 2 49568997cfSRajendra Nayak #define OMAP4430_LOGICSTATEST_MASK (1 << 2) 50568997cfSRajendra Nayak #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) 51568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) 5256ef28acSRajendra Nayak #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 53568997cfSRajendra Nayak #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) 5456ef28acSRajendra Nayak #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 5556ef28acSRajendra Nayak #define OMAP4430_MPU_WDT_RST_SHIFT 3 56568997cfSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) 57568997cfSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) 58568997cfSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) 5956ef28acSRajendra Nayak #define OMAP4430_OFF_SHIFT 0 6056ef28acSRajendra Nayak #define OMAP4430_ON_SHIFT 24 61568997cfSRajendra Nayak #define OMAP4430_ON_MASK (0xff << 24) 6256ef28acSRajendra Nayak #define OMAP4430_ONLP_SHIFT 16 6356ef28acSRajendra Nayak #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 6456ef28acSRajendra Nayak #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 6556ef28acSRajendra Nayak #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 6656ef28acSRajendra Nayak #define OMAP4430_REGADDR_SHIFT 8 6756ef28acSRajendra Nayak #define OMAP4430_RET_SHIFT 8 68568997cfSRajendra Nayak #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) 6956ef28acSRajendra Nayak #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 70568997cfSRajendra Nayak #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) 7156ef28acSRajendra Nayak #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 72568997cfSRajendra Nayak #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) 7356ef28acSRajendra Nayak #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 74568997cfSRajendra Nayak #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) 7556ef28acSRajendra Nayak #define OMAP4430_SCLH_SHIFT 0 7656ef28acSRajendra Nayak #define OMAP4430_SCLL_SHIFT 8 7756ef28acSRajendra Nayak #define OMAP4430_SECURE_WDT_RST_SHIFT 4 7856ef28acSRajendra Nayak #define OMAP4430_SLAVEADDR_SHIFT 0 7956ef28acSRajendra Nayak #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 8056ef28acSRajendra Nayak #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 8156ef28acSRajendra Nayak #define OMAP4430_TIMEOUT_SHIFT 0 82568997cfSRajendra Nayak #define OMAP4430_TIMEOUTEN_MASK (1 << 3) 83568997cfSRajendra Nayak #define OMAP4430_VALID_MASK (1 << 24) 8456ef28acSRajendra Nayak #define OMAP4430_VDDMAX_SHIFT 24 8556ef28acSRajendra Nayak #define OMAP4430_VDDMIN_SHIFT 16 8656ef28acSRajendra Nayak #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 8756ef28acSRajendra Nayak #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 8856ef28acSRajendra Nayak #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 89568997cfSRajendra Nayak #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) 90568997cfSRajendra Nayak #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) 91568997cfSRajendra Nayak #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) 92568997cfSRajendra Nayak #define OMAP4430_VPENABLE_MASK (1 << 0) 93568997cfSRajendra Nayak #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) 94568997cfSRajendra Nayak #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) 95568997cfSRajendra Nayak #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) 96568997cfSRajendra Nayak #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) 9756ef28acSRajendra Nayak #define OMAP4430_VSTEPMAX_SHIFT 0 9856ef28acSRajendra Nayak #define OMAP4430_VSTEPMIN_SHIFT 0 99568997cfSRajendra Nayak #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) 10056ef28acSRajendra Nayak #define OMAP4430_WUCLK_STATUS_SHIFT 9 101568997cfSRajendra Nayak #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) 102234f0c4cSRajendra Nayak #endif 103