xref: /linux/arch/arm/mach-omap2/prm-regbits-44xx.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2234f0c4cSRajendra Nayak /*
3234f0c4cSRajendra Nayak  * OMAP44xx Power Management register bits
4234f0c4cSRajendra Nayak  *
5568997cfSRajendra Nayak  * Copyright (C) 2009-2010 Texas Instruments, Inc.
6568997cfSRajendra Nayak  * Copyright (C) 2009-2010 Nokia Corporation
7234f0c4cSRajendra Nayak  *
8234f0c4cSRajendra Nayak  * Paul Walmsley (paul@pwsan.com)
9234f0c4cSRajendra Nayak  * Rajendra Nayak (rnayak@ti.com)
10234f0c4cSRajendra Nayak  * Benoit Cousson (b-cousson@ti.com)
11234f0c4cSRajendra Nayak  *
12234f0c4cSRajendra Nayak  * This file is automatically generated from the OMAP hardware databases.
13234f0c4cSRajendra Nayak  * We respectfully ask that any modifications to this file be coordinated
14234f0c4cSRajendra Nayak  * with the public linux-omap@vger.kernel.org mailing list and the
15234f0c4cSRajendra Nayak  * authors above to ensure that the autogeneration scripts are kept
16234f0c4cSRajendra Nayak  * up-to-date with the file contents.
17234f0c4cSRajendra Nayak  */
18234f0c4cSRajendra Nayak 
19234f0c4cSRajendra Nayak #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
20234f0c4cSRajendra Nayak #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
21234f0c4cSRajendra Nayak 
22568997cfSRajendra Nayak #define OMAP4430_C2C_RST_SHIFT						10
23568997cfSRajendra Nayak #define OMAP4430_CMDRA_VDD_CORE_L_MASK					(0xff << 0)
24568997cfSRajendra Nayak #define OMAP4430_CMDRA_VDD_IVA_L_MASK					(0xff << 8)
25568997cfSRajendra Nayak #define OMAP4430_CMDRA_VDD_MPU_L_MASK					(0xff << 16)
2656ef28acSRajendra Nayak #define OMAP4430_DATA_SHIFT						16
27568997cfSRajendra Nayak #define OMAP4430_ERRORGAIN_MASK						(0xff << 16)
28568997cfSRajendra Nayak #define OMAP4430_ERROROFFSET_MASK					(0xff << 24)
2956ef28acSRajendra Nayak #define OMAP4430_EXTERNAL_WARM_RST_SHIFT				5
30568997cfSRajendra Nayak #define OMAP4430_FORCEUPDATE_MASK					(1 << 1)
3156ef28acSRajendra Nayak #define OMAP4430_GLOBAL_COLD_RST_SHIFT					0
3256ef28acSRajendra Nayak #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT				1
33568997cfSRajendra Nayak #define OMAP4430_GLOBAL_WUEN_MASK					(1 << 16)
34568997cfSRajendra Nayak #define OMAP4430_HSMCODE_MASK						(0x7 << 0)
35102bcb6eSTony Lindgren #define OMAP4430_SRMODEEN_MASK						(1 << 4)
36568997cfSRajendra Nayak #define OMAP4430_HSMODEEN_MASK						(1 << 3)
3756ef28acSRajendra Nayak #define OMAP4430_HSSCLL_SHIFT						24
3856ef28acSRajendra Nayak #define OMAP4430_ICEPICK_RST_SHIFT					9
39568997cfSRajendra Nayak #define OMAP4430_INITVDD_MASK						(1 << 2)
40568997cfSRajendra Nayak #define OMAP4430_INITVOLTAGE_MASK					(0xff << 8)
41568997cfSRajendra Nayak #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT				24
42568997cfSRajendra Nayak #define OMAP4430_LASTPOWERSTATEENTERED_MASK				(0x3 << 24)
4356ef28acSRajendra Nayak #define OMAP4430_LOGICRETSTATE_SHIFT					2
44568997cfSRajendra Nayak #define OMAP4430_LOGICRETSTATE_MASK					(1 << 2)
4556ef28acSRajendra Nayak #define OMAP4430_LOGICSTATEST_SHIFT					2
46568997cfSRajendra Nayak #define OMAP4430_LOGICSTATEST_MASK					(1 << 2)
47568997cfSRajendra Nayak #define OMAP4430_LOSTCONTEXT_DFF_MASK					(1 << 0)
48568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_AESSMEM_MASK					(1 << 8)
4956ef28acSRajendra Nayak #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT				4
50568997cfSRajendra Nayak #define OMAP4430_LOWPOWERSTATECHANGE_MASK				(1 << 4)
5156ef28acSRajendra Nayak #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT				2
5256ef28acSRajendra Nayak #define OMAP4430_MPU_WDT_RST_SHIFT					3
53568997cfSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK				(0x3 << 24)
54568997cfSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK				(1 << 12)
55568997cfSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_STATEST_MASK				(0x3 << 12)
5656ef28acSRajendra Nayak #define OMAP4430_OFF_SHIFT						0
5756ef28acSRajendra Nayak #define OMAP4430_ON_SHIFT						24
58568997cfSRajendra Nayak #define OMAP4430_ON_MASK						(0xff << 24)
5956ef28acSRajendra Nayak #define OMAP4430_ONLP_SHIFT						16
6056ef28acSRajendra Nayak #define OMAP4430_RAMP_DOWN_COUNT_SHIFT					16
6156ef28acSRajendra Nayak #define OMAP4430_RAMP_UP_COUNT_SHIFT					0
6256ef28acSRajendra Nayak #define OMAP4430_RAMP_UP_PRESCAL_SHIFT					8
6356ef28acSRajendra Nayak #define OMAP4430_REGADDR_SHIFT						8
6456ef28acSRajendra Nayak #define OMAP4430_RET_SHIFT						8
65568997cfSRajendra Nayak #define OMAP4430_RST_GLOBAL_WARM_SW_MASK				(1 << 0)
6656ef28acSRajendra Nayak #define OMAP4430_SA_VDD_CORE_L_SHIFT					0
67568997cfSRajendra Nayak #define OMAP4430_SA_VDD_CORE_L_0_6_MASK					(0x7f << 0)
6856ef28acSRajendra Nayak #define OMAP4430_SA_VDD_IVA_L_SHIFT					8
69568997cfSRajendra Nayak #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK			(0x7f << 8)
7056ef28acSRajendra Nayak #define OMAP4430_SA_VDD_MPU_L_SHIFT					16
71568997cfSRajendra Nayak #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK			(0x7f << 16)
7256ef28acSRajendra Nayak #define OMAP4430_SCLH_SHIFT						0
7356ef28acSRajendra Nayak #define OMAP4430_SCLL_SHIFT						8
7456ef28acSRajendra Nayak #define OMAP4430_SECURE_WDT_RST_SHIFT					4
7556ef28acSRajendra Nayak #define OMAP4430_SLAVEADDR_SHIFT					0
7656ef28acSRajendra Nayak #define OMAP4430_SMPSWAITTIMEMAX_SHIFT					8
7756ef28acSRajendra Nayak #define OMAP4430_SMPSWAITTIMEMIN_SHIFT					8
7856ef28acSRajendra Nayak #define OMAP4430_TIMEOUT_SHIFT						0
79568997cfSRajendra Nayak #define OMAP4430_TIMEOUTEN_MASK						(1 << 3)
80568997cfSRajendra Nayak #define OMAP4430_VALID_MASK						(1 << 24)
8156ef28acSRajendra Nayak #define OMAP4430_VDDMAX_SHIFT						24
8256ef28acSRajendra Nayak #define OMAP4430_VDDMIN_SHIFT						16
8356ef28acSRajendra Nayak #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT				8
8456ef28acSRajendra Nayak #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT				7
8556ef28acSRajendra Nayak #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT				6
86568997cfSRajendra Nayak #define OMAP4430_VOLRA_VDD_CORE_L_MASK					(0xff << 0)
87568997cfSRajendra Nayak #define OMAP4430_VOLRA_VDD_IVA_L_MASK					(0xff << 8)
88568997cfSRajendra Nayak #define OMAP4430_VOLRA_VDD_MPU_L_MASK					(0xff << 16)
89568997cfSRajendra Nayak #define OMAP4430_VPENABLE_MASK						(1 << 0)
90568997cfSRajendra Nayak #define OMAP4430_VPVOLTAGE_MASK						(0xff << 0)
91568997cfSRajendra Nayak #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK				(1 << 21)
92568997cfSRajendra Nayak #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK				(1 << 29)
93568997cfSRajendra Nayak #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK				(1 << 5)
9456ef28acSRajendra Nayak #define OMAP4430_VSTEPMAX_SHIFT						0
9556ef28acSRajendra Nayak #define OMAP4430_VSTEPMIN_SHIFT						0
96568997cfSRajendra Nayak #define OMAP4430_WUCLK_CTRL_MASK					(1 << 8)
9756ef28acSRajendra Nayak #define OMAP4430_WUCLK_STATUS_SHIFT					9
98568997cfSRajendra Nayak #define OMAP4430_WUCLK_STATUS_MASK					(1 << 9)
99234f0c4cSRajendra Nayak #endif
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