1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * AM33XX PRM_XXX register bits 4 * 5 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H 9 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H 10 11 #include "prm.h" 12 13 #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) 14 #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) 15 #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) 16 #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) 17 #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) 18 #define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) 19 #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) 20 #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) 21 #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) 22 #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 23 #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) 24 #define AM33XX_LOGICRETSTATE_MASK (1 << 2) 25 #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) 26 #define AM33XX_LOGICSTATEST_SHIFT 2 27 #define AM33XX_LOGICSTATEST_MASK (1 << 2) 28 #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 29 #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) 30 #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) 31 #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) 32 #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) 33 #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) 34 #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) 35 #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) 36 #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) 37 #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) 38 #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) 39 #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) 40 #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) 41 #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) 42 #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) 43 #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) 44 #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) 45 #endif 46