1 /* 2 * OMAP54XX Power domains framework 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * Abhijit Pagare (abhijitpagare@ti.com) 7 * Benoit Cousson (b-cousson@ti.com) 8 * Paul Walmsley (paul@pwsan.com) 9 * 10 * This file is automatically generated from the OMAP hardware databases. 11 * We respectfully ask that any modifications to this file be coordinated 12 * with the public linux-omap@vger.kernel.org mailing list and the 13 * authors above to ensure that the autogeneration scripts are kept 14 * up-to-date with the file contents. 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as 18 * published by the Free Software Foundation. 19 */ 20 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 24 #include "powerdomain.h" 25 26 #include "prcm-common.h" 27 #include "prcm44xx.h" 28 #include "prm54xx.h" 29 #include "prcm_mpu54xx.h" 30 31 /* core_54xx_pwrdm: CORE power domain */ 32 static struct powerdomain core_54xx_pwrdm = { 33 .name = "core_pwrdm", 34 .voltdm = { .name = "core" }, 35 .prcm_offs = OMAP54XX_PRM_CORE_INST, 36 .prcm_partition = OMAP54XX_PRM_PARTITION, 37 .pwrsts = PWRSTS_RET_ON, 38 .pwrsts_logic_ret = PWRSTS_RET, 39 .banks = 5, 40 .pwrsts_mem_ret = { 41 [0] = PWRSTS_OFF_RET, /* core_nret_bank */ 42 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 43 [2] = PWRSTS_OFF_RET, /* core_other_bank */ 44 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ 45 [4] = PWRSTS_OFF_RET, /* ipu_unicache */ 46 }, 47 .pwrsts_mem_on = { 48 [0] = PWRSTS_OFF_RET, /* core_nret_bank */ 49 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 50 [2] = PWRSTS_OFF_RET, /* core_other_bank */ 51 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ 52 [4] = PWRSTS_OFF_RET, /* ipu_unicache */ 53 }, 54 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 55 }; 56 57 /* abe_54xx_pwrdm: Audio back end power domain */ 58 static struct powerdomain abe_54xx_pwrdm = { 59 .name = "abe_pwrdm", 60 .voltdm = { .name = "core" }, 61 .prcm_offs = OMAP54XX_PRM_ABE_INST, 62 .prcm_partition = OMAP54XX_PRM_PARTITION, 63 .pwrsts = PWRSTS_OFF_RET_ON, 64 .pwrsts_logic_ret = PWRSTS_OFF, 65 .banks = 2, 66 .pwrsts_mem_ret = { 67 [0] = PWRSTS_OFF_RET, /* aessmem */ 68 [1] = PWRSTS_OFF_RET, /* periphmem */ 69 }, 70 .pwrsts_mem_on = { 71 [0] = PWRSTS_OFF_RET, /* aessmem */ 72 [1] = PWRSTS_OFF_RET, /* periphmem */ 73 }, 74 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 75 }; 76 77 /* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */ 78 static struct powerdomain coreaon_54xx_pwrdm = { 79 .name = "coreaon_pwrdm", 80 .voltdm = { .name = "core" }, 81 .prcm_offs = OMAP54XX_PRM_COREAON_INST, 82 .prcm_partition = OMAP54XX_PRM_PARTITION, 83 .pwrsts = PWRSTS_ON, 84 }; 85 86 /* dss_54xx_pwrdm: Display subsystem power domain */ 87 static struct powerdomain dss_54xx_pwrdm = { 88 .name = "dss_pwrdm", 89 .voltdm = { .name = "core" }, 90 .prcm_offs = OMAP54XX_PRM_DSS_INST, 91 .prcm_partition = OMAP54XX_PRM_PARTITION, 92 .pwrsts = PWRSTS_OFF_RET_ON, 93 .pwrsts_logic_ret = PWRSTS_OFF, 94 .banks = 1, 95 .pwrsts_mem_ret = { 96 [0] = PWRSTS_OFF_RET, /* dss_mem */ 97 }, 98 .pwrsts_mem_on = { 99 [0] = PWRSTS_OFF_RET, /* dss_mem */ 100 }, 101 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 102 }; 103 104 /* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ 105 static struct powerdomain cpu0_54xx_pwrdm = { 106 .name = "cpu0_pwrdm", 107 .voltdm = { .name = "mpu" }, 108 .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST, 109 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, 110 .pwrsts = PWRSTS_RET_ON, 111 .pwrsts_logic_ret = PWRSTS_RET, 112 .banks = 1, 113 .pwrsts_mem_ret = { 114 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ 115 }, 116 .pwrsts_mem_on = { 117 [0] = PWRSTS_ON, /* cpu0_l1 */ 118 }, 119 }; 120 121 /* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ 122 static struct powerdomain cpu1_54xx_pwrdm = { 123 .name = "cpu1_pwrdm", 124 .voltdm = { .name = "mpu" }, 125 .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST, 126 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, 127 .pwrsts = PWRSTS_RET_ON, 128 .pwrsts_logic_ret = PWRSTS_RET, 129 .banks = 1, 130 .pwrsts_mem_ret = { 131 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ 132 }, 133 .pwrsts_mem_on = { 134 [0] = PWRSTS_ON, /* cpu1_l1 */ 135 }, 136 }; 137 138 /* emu_54xx_pwrdm: Emulation power domain */ 139 static struct powerdomain emu_54xx_pwrdm = { 140 .name = "emu_pwrdm", 141 .voltdm = { .name = "wkup" }, 142 .prcm_offs = OMAP54XX_PRM_EMU_INST, 143 .prcm_partition = OMAP54XX_PRM_PARTITION, 144 .pwrsts = PWRSTS_OFF_ON, 145 .banks = 1, 146 .pwrsts_mem_ret = { 147 [0] = PWRSTS_OFF_RET, /* emu_bank */ 148 }, 149 .pwrsts_mem_on = { 150 [0] = PWRSTS_OFF_RET, /* emu_bank */ 151 }, 152 }; 153 154 /* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */ 155 static struct powerdomain mpu_54xx_pwrdm = { 156 .name = "mpu_pwrdm", 157 .voltdm = { .name = "mpu" }, 158 .prcm_offs = OMAP54XX_PRM_MPU_INST, 159 .prcm_partition = OMAP54XX_PRM_PARTITION, 160 .pwrsts = PWRSTS_RET_ON, 161 .pwrsts_logic_ret = PWRSTS_RET, 162 .banks = 2, 163 .pwrsts_mem_ret = { 164 [0] = PWRSTS_OFF_RET, /* mpu_l2 */ 165 [1] = PWRSTS_RET, /* mpu_ram */ 166 }, 167 .pwrsts_mem_on = { 168 [0] = PWRSTS_OFF_RET, /* mpu_l2 */ 169 [1] = PWRSTS_OFF_RET, /* mpu_ram */ 170 }, 171 }; 172 173 /* custefuse_54xx_pwrdm: Customer efuse controller power domain */ 174 static struct powerdomain custefuse_54xx_pwrdm = { 175 .name = "custefuse_pwrdm", 176 .voltdm = { .name = "core" }, 177 .prcm_offs = OMAP54XX_PRM_CUSTEFUSE_INST, 178 .prcm_partition = OMAP54XX_PRM_PARTITION, 179 .pwrsts = PWRSTS_OFF_ON, 180 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 181 }; 182 183 /* dsp_54xx_pwrdm: Tesla processor power domain */ 184 static struct powerdomain dsp_54xx_pwrdm = { 185 .name = "dsp_pwrdm", 186 .voltdm = { .name = "mm" }, 187 .prcm_offs = OMAP54XX_PRM_DSP_INST, 188 .prcm_partition = OMAP54XX_PRM_PARTITION, 189 .pwrsts = PWRSTS_OFF_RET_ON, 190 .pwrsts_logic_ret = PWRSTS_OFF_RET, 191 .banks = 3, 192 .pwrsts_mem_ret = { 193 [0] = PWRSTS_OFF_RET, /* dsp_edma */ 194 [1] = PWRSTS_OFF_RET, /* dsp_l1 */ 195 [2] = PWRSTS_OFF_RET, /* dsp_l2 */ 196 }, 197 .pwrsts_mem_on = { 198 [0] = PWRSTS_OFF_RET, /* dsp_edma */ 199 [1] = PWRSTS_OFF_RET, /* dsp_l1 */ 200 [2] = PWRSTS_OFF_RET, /* dsp_l2 */ 201 }, 202 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 203 }; 204 205 /* cam_54xx_pwrdm: Camera subsystem power domain */ 206 static struct powerdomain cam_54xx_pwrdm = { 207 .name = "cam_pwrdm", 208 .voltdm = { .name = "core" }, 209 .prcm_offs = OMAP54XX_PRM_CAM_INST, 210 .prcm_partition = OMAP54XX_PRM_PARTITION, 211 .pwrsts = PWRSTS_OFF_ON, 212 .banks = 1, 213 .pwrsts_mem_ret = { 214 [0] = PWRSTS_OFF_RET, /* cam_mem */ 215 }, 216 .pwrsts_mem_on = { 217 [0] = PWRSTS_OFF_RET, /* cam_mem */ 218 }, 219 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 220 }; 221 222 /* l3init_54xx_pwrdm: L3 initators pheripherals power domain */ 223 static struct powerdomain l3init_54xx_pwrdm = { 224 .name = "l3init_pwrdm", 225 .voltdm = { .name = "core" }, 226 .prcm_offs = OMAP54XX_PRM_L3INIT_INST, 227 .prcm_partition = OMAP54XX_PRM_PARTITION, 228 .pwrsts = PWRSTS_RET_ON, 229 .pwrsts_logic_ret = PWRSTS_OFF_RET, 230 .banks = 2, 231 .pwrsts_mem_ret = { 232 [0] = PWRSTS_OFF_RET, /* l3init_bank1 */ 233 [1] = PWRSTS_OFF_RET, /* l3init_bank2 */ 234 }, 235 .pwrsts_mem_on = { 236 [0] = PWRSTS_OFF_RET, /* l3init_bank1 */ 237 [1] = PWRSTS_OFF_RET, /* l3init_bank2 */ 238 }, 239 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 240 }; 241 242 /* gpu_54xx_pwrdm: 3D accelerator power domain */ 243 static struct powerdomain gpu_54xx_pwrdm = { 244 .name = "gpu_pwrdm", 245 .voltdm = { .name = "mm" }, 246 .prcm_offs = OMAP54XX_PRM_GPU_INST, 247 .prcm_partition = OMAP54XX_PRM_PARTITION, 248 .pwrsts = PWRSTS_OFF_ON, 249 .banks = 1, 250 .pwrsts_mem_ret = { 251 [0] = PWRSTS_OFF_RET, /* gpu_mem */ 252 }, 253 .pwrsts_mem_on = { 254 [0] = PWRSTS_OFF_RET, /* gpu_mem */ 255 }, 256 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 257 }; 258 259 /* wkupaon_54xx_pwrdm: Wake-up power domain */ 260 static struct powerdomain wkupaon_54xx_pwrdm = { 261 .name = "wkupaon_pwrdm", 262 .voltdm = { .name = "wkup" }, 263 .prcm_offs = OMAP54XX_PRM_WKUPAON_INST, 264 .prcm_partition = OMAP54XX_PRM_PARTITION, 265 .pwrsts = PWRSTS_ON, 266 .banks = 1, 267 .pwrsts_mem_ret = { 268 }, 269 .pwrsts_mem_on = { 270 [0] = PWRSTS_ON, /* wkup_bank */ 271 }, 272 }; 273 274 /* iva_54xx_pwrdm: IVA-HD power domain */ 275 static struct powerdomain iva_54xx_pwrdm = { 276 .name = "iva_pwrdm", 277 .voltdm = { .name = "mm" }, 278 .prcm_offs = OMAP54XX_PRM_IVA_INST, 279 .prcm_partition = OMAP54XX_PRM_PARTITION, 280 .pwrsts = PWRSTS_OFF_RET_ON, 281 .pwrsts_logic_ret = PWRSTS_OFF, 282 .banks = 4, 283 .pwrsts_mem_ret = { 284 [0] = PWRSTS_OFF_RET, /* hwa_mem */ 285 [1] = PWRSTS_OFF_RET, /* sl2_mem */ 286 [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 287 [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 288 }, 289 .pwrsts_mem_on = { 290 [0] = PWRSTS_OFF_RET, /* hwa_mem */ 291 [1] = PWRSTS_OFF_RET, /* sl2_mem */ 292 [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 293 [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 294 }, 295 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 296 }; 297 298 /* 299 * The following power domains are not under SW control 300 * 301 * mpuaon 302 * mmaon 303 */ 304 305 /* As powerdomains are added or removed above, this list must also be changed */ 306 static struct powerdomain *powerdomains_omap54xx[] __initdata = { 307 &core_54xx_pwrdm, 308 &abe_54xx_pwrdm, 309 &coreaon_54xx_pwrdm, 310 &dss_54xx_pwrdm, 311 &cpu0_54xx_pwrdm, 312 &cpu1_54xx_pwrdm, 313 &emu_54xx_pwrdm, 314 &mpu_54xx_pwrdm, 315 &custefuse_54xx_pwrdm, 316 &dsp_54xx_pwrdm, 317 &cam_54xx_pwrdm, 318 &l3init_54xx_pwrdm, 319 &gpu_54xx_pwrdm, 320 &wkupaon_54xx_pwrdm, 321 &iva_54xx_pwrdm, 322 NULL 323 }; 324 325 void __init omap54xx_powerdomains_init(void) 326 { 327 pwrdm_register_platform_funcs(&omap4_pwrdm_operations); 328 pwrdm_register_pwrdms(powerdomains_omap54xx); 329 pwrdm_complete_init(); 330 } 331