1 /* 2 * OMAP2/3/4 powerdomain control 3 * 4 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc. 5 * Copyright (C) 2007-2011 Nokia Corporation 6 * 7 * Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * XXX This should be moved to the mach-omap2/ directory at the earliest 14 * opportunity. 15 */ 16 17 #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H 18 #define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H 19 20 #include <linux/types.h> 21 #include <linux/list.h> 22 #include <linux/spinlock.h> 23 24 /* Powerdomain basic power states */ 25 #define PWRDM_POWER_OFF 0x0 26 #define PWRDM_POWER_RET 0x1 27 #define PWRDM_POWER_INACTIVE 0x2 28 #define PWRDM_POWER_ON 0x3 29 30 #define PWRDM_MAX_PWRSTS 4 31 32 /* Powerdomain allowable state bitfields */ 33 #define PWRSTS_ON (1 << PWRDM_POWER_ON) 34 #define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE) 35 #define PWRSTS_RET (1 << PWRDM_POWER_RET) 36 #define PWRSTS_OFF (1 << PWRDM_POWER_OFF) 37 38 #define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON) 39 #define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET) 40 #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) 41 #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON) 42 43 44 /* 45 * Powerdomain flags (struct powerdomain.flags) 46 * 47 * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support 48 * 49 * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM 50 * bank 1 position. This is true for OMAP3430 51 * 52 * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state 53 * to a lower sleep state without waking up the powerdomain 54 */ 55 #define PWRDM_HAS_HDWR_SAR BIT(0) 56 #define PWRDM_HAS_MPU_QUIRK BIT(1) 57 #define PWRDM_HAS_LOWPOWERSTATECHANGE BIT(2) 58 59 /* 60 * Number of memory banks that are power-controllable. On OMAP4430, the 61 * maximum is 5. 62 */ 63 #define PWRDM_MAX_MEM_BANKS 5 64 65 /* 66 * Maximum number of clockdomains that can be associated with a powerdomain. 67 * PER powerdomain on AM33XX is the worst case 68 */ 69 #define PWRDM_MAX_CLKDMS 11 70 71 /* XXX A completely arbitrary number. What is reasonable here? */ 72 #define PWRDM_TRANSITION_BAILOUT 100000 73 74 struct clockdomain; 75 struct powerdomain; 76 struct voltagedomain; 77 78 /** 79 * struct powerdomain - OMAP powerdomain 80 * @name: Powerdomain name 81 * @voltdm: voltagedomain containing this powerdomain 82 * @prcm_offs: the address offset from CM_BASE/PRM_BASE 83 * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs 84 * @pwrsts: Possible powerdomain power states 85 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION 86 * @flags: Powerdomain flags 87 * @banks: Number of software-controllable memory banks in this powerdomain 88 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION 89 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON 90 * @pwrdm_clkdms: Clockdomains in this powerdomain 91 * @node: list_head linking all powerdomains 92 * @voltdm_node: list_head linking all powerdomains in a voltagedomain 93 * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs 94 * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs 95 * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield 96 * in @pwrstctrl_offs 97 * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs 98 * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs 99 * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs 100 * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield 101 * in @pwrstctrl_offs 102 * @state: 103 * @state_counter: 104 * @timer: 105 * @state_timer: 106 * @_lock: spinlock used to serialize powerdomain and some clockdomain ops 107 * @_lock_flags: stored flags when @_lock is taken 108 * 109 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. 110 */ 111 struct powerdomain { 112 const char *name; 113 union { 114 const char *name; 115 struct voltagedomain *ptr; 116 } voltdm; 117 const s16 prcm_offs; 118 const u8 pwrsts; 119 const u8 pwrsts_logic_ret; 120 const u8 flags; 121 const u8 banks; 122 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; 123 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; 124 const u8 prcm_partition; 125 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; 126 struct list_head node; 127 struct list_head voltdm_node; 128 int state; 129 unsigned state_counter[PWRDM_MAX_PWRSTS]; 130 unsigned ret_logic_off_counter; 131 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; 132 spinlock_t _lock; 133 unsigned long _lock_flags; 134 const u8 pwrstctrl_offs; 135 const u8 pwrstst_offs; 136 const u32 logicretstate_mask; 137 const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS]; 138 const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS]; 139 const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS]; 140 const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS]; 141 142 #ifdef CONFIG_PM_DEBUG 143 s64 timer; 144 s64 state_timer[PWRDM_MAX_PWRSTS]; 145 #endif 146 }; 147 148 /** 149 * struct pwrdm_ops - Arch specific function implementations 150 * @pwrdm_set_next_pwrst: Set the target power state for a pd 151 * @pwrdm_read_next_pwrst: Read the target power state set for a pd 152 * @pwrdm_read_pwrst: Read the current power state of a pd 153 * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd 154 * @pwrdm_set_logic_retst: Set the logic state in RET for a pd 155 * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd 156 * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd 157 * @pwrdm_read_logic_pwrst: Read the current logic state of a pd 158 * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd 159 * @pwrdm_read_logic_retst: Read the logic state in RET for a pd 160 * @pwrdm_read_mem_pwrst: Read the current memory state of a pd 161 * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd 162 * @pwrdm_read_mem_retst: Read the memory state in RET for a pd 163 * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd 164 * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd 165 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd 166 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep 167 * @pwrdm_wait_transition: Wait for a pd state transition to complete 168 * @pwrdm_has_voltdm: Check if a voltdm association is needed 169 * 170 * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family 171 * chips, a powerdomain's power state is not allowed to directly 172 * transition from one low-power state (e.g., CSWR) to another 173 * low-power state (e.g., OFF) without first waking up the 174 * powerdomain. This wastes energy. So OMAP4 chips support the 175 * ability to transition a powerdomain power state directly from one 176 * low-power state to another. The function pointed to by 177 * @pwrdm_set_lowpwrstchange is intended to configure the OMAP4 178 * hardware powerdomain state machine to enable this feature. 179 */ 180 struct pwrdm_ops { 181 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); 182 int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm); 183 int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm); 184 int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm); 185 int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst); 186 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 187 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 188 int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm); 189 int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm); 190 int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm); 191 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); 192 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); 193 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank); 194 int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm); 195 int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm); 196 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); 197 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); 198 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); 199 int (*pwrdm_has_voltdm)(void); 200 }; 201 202 int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs); 203 int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list); 204 int pwrdm_complete_init(void); 205 206 struct powerdomain *pwrdm_lookup(const char *name); 207 208 int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), 209 void *user); 210 int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), 211 void *user); 212 213 int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); 214 int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); 215 int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, 216 int (*fn)(struct powerdomain *pwrdm, 217 struct clockdomain *clkdm)); 218 struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm); 219 220 int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); 221 222 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); 223 int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); 224 int pwrdm_read_pwrst(struct powerdomain *pwrdm); 225 int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); 226 int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); 227 228 int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); 229 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 230 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 231 232 int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); 233 int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); 234 int pwrdm_read_logic_retst(struct powerdomain *pwrdm); 235 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); 236 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); 237 int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); 238 239 int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); 240 int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); 241 bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); 242 243 int pwrdm_state_switch_nolock(struct powerdomain *pwrdm); 244 int pwrdm_state_switch(struct powerdomain *pwrdm); 245 int pwrdm_pre_transition(struct powerdomain *pwrdm); 246 int pwrdm_post_transition(struct powerdomain *pwrdm); 247 int pwrdm_get_context_loss_count(struct powerdomain *pwrdm); 248 bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm); 249 250 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state); 251 252 extern void omap242x_powerdomains_init(void); 253 extern void omap243x_powerdomains_init(void); 254 extern void omap3xxx_powerdomains_init(void); 255 extern void am33xx_powerdomains_init(void); 256 extern void omap44xx_powerdomains_init(void); 257 extern void omap54xx_powerdomains_init(void); 258 extern void dra7xx_powerdomains_init(void); 259 void am43xx_powerdomains_init(void); 260 261 extern struct pwrdm_ops omap2_pwrdm_operations; 262 extern struct pwrdm_ops omap3_pwrdm_operations; 263 extern struct pwrdm_ops am33xx_pwrdm_operations; 264 extern struct pwrdm_ops omap4_pwrdm_operations; 265 266 /* Common Internal functions used across OMAP rev's */ 267 extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank); 268 extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank); 269 extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); 270 271 extern struct powerdomain wkup_omap2_pwrdm; 272 extern struct powerdomain gfx_omap2_pwrdm; 273 274 extern void pwrdm_lock(struct powerdomain *pwrdm); 275 extern void pwrdm_unlock(struct powerdomain *pwrdm); 276 277 #endif 278