xref: /linux/arch/arm/mach-omap2/powerdomain-common.c (revision d9a5f4dd437ceb007e1f118e90ba5587a5e04d20)
19b7fc907SRajendra Nayak /*
28179488aSPaul Walmsley  * Common powerdomain framework functions
39b7fc907SRajendra Nayak  *
48179488aSPaul Walmsley  * Copyright (C) 2010-2011 Texas Instruments, Inc.
59b7fc907SRajendra Nayak  * Copyright (C) 2010 Nokia Corporation
69b7fc907SRajendra Nayak  *
79b7fc907SRajendra Nayak  * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
89b7fc907SRajendra Nayak  *
99b7fc907SRajendra Nayak  * This program is free software; you can redistribute it and/or modify
109b7fc907SRajendra Nayak  * it under the terms of the GNU General Public License version 2 as
119b7fc907SRajendra Nayak  * published by the Free Software Foundation.
129b7fc907SRajendra Nayak  */
139b7fc907SRajendra Nayak 
149b7fc907SRajendra Nayak #include <linux/errno.h>
159b7fc907SRajendra Nayak #include <linux/kernel.h>
16*d9a5f4ddSTony Lindgren #include <linux/bug.h>
179b7fc907SRajendra Nayak #include "pm.h"
189b7fc907SRajendra Nayak #include "cm.h"
199b7fc907SRajendra Nayak #include "cm-regbits-34xx.h"
209b7fc907SRajendra Nayak #include "cm-regbits-44xx.h"
219b7fc907SRajendra Nayak #include "prm-regbits-34xx.h"
229b7fc907SRajendra Nayak #include "prm-regbits-44xx.h"
239b7fc907SRajendra Nayak 
249b7fc907SRajendra Nayak /*
259b7fc907SRajendra Nayak  * OMAP3 and OMAP4 specific register bit initialisations
269b7fc907SRajendra Nayak  * Notice that the names here are not according to each power
279b7fc907SRajendra Nayak  * domain but the bit mapping used applies to all of them
289b7fc907SRajendra Nayak  */
299b7fc907SRajendra Nayak /* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */
309b7fc907SRajendra Nayak #define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK
319b7fc907SRajendra Nayak #define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK
329b7fc907SRajendra Nayak #define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK
339b7fc907SRajendra Nayak #define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK
349b7fc907SRajendra Nayak #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
359b7fc907SRajendra Nayak 
369b7fc907SRajendra Nayak /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
379b7fc907SRajendra Nayak #define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK
389b7fc907SRajendra Nayak #define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK
399b7fc907SRajendra Nayak #define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK
409b7fc907SRajendra Nayak #define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK
419b7fc907SRajendra Nayak #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
429b7fc907SRajendra Nayak 
439b7fc907SRajendra Nayak /* OMAP3 and OMAP4 Memory Status bits */
449b7fc907SRajendra Nayak #define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK
459b7fc907SRajendra Nayak #define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK
469b7fc907SRajendra Nayak #define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK
479b7fc907SRajendra Nayak #define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK
489b7fc907SRajendra Nayak #define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK
499b7fc907SRajendra Nayak 
509b7fc907SRajendra Nayak /* Common Internal functions used across OMAP rev's*/
519b7fc907SRajendra Nayak u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank)
529b7fc907SRajendra Nayak {
539b7fc907SRajendra Nayak 	switch (bank) {
549b7fc907SRajendra Nayak 	case 0:
559b7fc907SRajendra Nayak 		return OMAP_MEM0_ONSTATE_MASK;
569b7fc907SRajendra Nayak 	case 1:
579b7fc907SRajendra Nayak 		return OMAP_MEM1_ONSTATE_MASK;
589b7fc907SRajendra Nayak 	case 2:
599b7fc907SRajendra Nayak 		return OMAP_MEM2_ONSTATE_MASK;
609b7fc907SRajendra Nayak 	case 3:
619b7fc907SRajendra Nayak 		return OMAP_MEM3_ONSTATE_MASK;
629b7fc907SRajendra Nayak 	case 4:
639b7fc907SRajendra Nayak 		return OMAP_MEM4_ONSTATE_MASK;
649b7fc907SRajendra Nayak 	default:
659b7fc907SRajendra Nayak 		WARN_ON(1); /* should never happen */
669b7fc907SRajendra Nayak 		return -EEXIST;
679b7fc907SRajendra Nayak 	}
689b7fc907SRajendra Nayak 	return 0;
699b7fc907SRajendra Nayak }
709b7fc907SRajendra Nayak 
719b7fc907SRajendra Nayak u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank)
729b7fc907SRajendra Nayak {
739b7fc907SRajendra Nayak 	switch (bank) {
749b7fc907SRajendra Nayak 	case 0:
759b7fc907SRajendra Nayak 		return OMAP_MEM0_RETSTATE_MASK;
769b7fc907SRajendra Nayak 	case 1:
779b7fc907SRajendra Nayak 		return OMAP_MEM1_RETSTATE_MASK;
789b7fc907SRajendra Nayak 	case 2:
799b7fc907SRajendra Nayak 		return OMAP_MEM2_RETSTATE_MASK;
809b7fc907SRajendra Nayak 	case 3:
819b7fc907SRajendra Nayak 		return OMAP_MEM3_RETSTATE_MASK;
829b7fc907SRajendra Nayak 	case 4:
839b7fc907SRajendra Nayak 		return OMAP_MEM4_RETSTATE_MASK;
849b7fc907SRajendra Nayak 	default:
859b7fc907SRajendra Nayak 		WARN_ON(1); /* should never happen */
869b7fc907SRajendra Nayak 		return -EEXIST;
879b7fc907SRajendra Nayak 	}
889b7fc907SRajendra Nayak 	return 0;
899b7fc907SRajendra Nayak }
909b7fc907SRajendra Nayak 
919b7fc907SRajendra Nayak u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank)
929b7fc907SRajendra Nayak {
939b7fc907SRajendra Nayak 	switch (bank) {
949b7fc907SRajendra Nayak 	case 0:
959b7fc907SRajendra Nayak 		return OMAP_MEM0_STATEST_MASK;
969b7fc907SRajendra Nayak 	case 1:
979b7fc907SRajendra Nayak 		return OMAP_MEM1_STATEST_MASK;
989b7fc907SRajendra Nayak 	case 2:
999b7fc907SRajendra Nayak 		return OMAP_MEM2_STATEST_MASK;
1009b7fc907SRajendra Nayak 	case 3:
1019b7fc907SRajendra Nayak 		return OMAP_MEM3_STATEST_MASK;
1029b7fc907SRajendra Nayak 	case 4:
1039b7fc907SRajendra Nayak 		return OMAP_MEM4_STATEST_MASK;
1049b7fc907SRajendra Nayak 	default:
1059b7fc907SRajendra Nayak 		WARN_ON(1); /* should never happen */
1069b7fc907SRajendra Nayak 		return -EEXIST;
1079b7fc907SRajendra Nayak 	}
1089b7fc907SRajendra Nayak 	return 0;
1099b7fc907SRajendra Nayak }
1109b7fc907SRajendra Nayak 
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