1*9b7fc907SRajendra Nayak /* 2*9b7fc907SRajendra Nayak * linux/arch/arm/mach-omap2/powerdomain-common.c 3*9b7fc907SRajendra Nayak * Contains common powerdomain framework functions 4*9b7fc907SRajendra Nayak * 5*9b7fc907SRajendra Nayak * Copyright (C) 2010 Texas Instruments, Inc. 6*9b7fc907SRajendra Nayak * Copyright (C) 2010 Nokia Corporation 7*9b7fc907SRajendra Nayak * 8*9b7fc907SRajendra Nayak * Derived from mach-omap2/powerdomain.c written by Paul Walmsley 9*9b7fc907SRajendra Nayak * 10*9b7fc907SRajendra Nayak * This program is free software; you can redistribute it and/or modify 11*9b7fc907SRajendra Nayak * it under the terms of the GNU General Public License version 2 as 12*9b7fc907SRajendra Nayak * published by the Free Software Foundation. 13*9b7fc907SRajendra Nayak */ 14*9b7fc907SRajendra Nayak 15*9b7fc907SRajendra Nayak #include <linux/errno.h> 16*9b7fc907SRajendra Nayak #include <linux/kernel.h> 17*9b7fc907SRajendra Nayak #include "pm.h" 18*9b7fc907SRajendra Nayak #include "cm.h" 19*9b7fc907SRajendra Nayak #include "cm-regbits-34xx.h" 20*9b7fc907SRajendra Nayak #include "cm-regbits-44xx.h" 21*9b7fc907SRajendra Nayak #include "prm-regbits-34xx.h" 22*9b7fc907SRajendra Nayak #include "prm-regbits-44xx.h" 23*9b7fc907SRajendra Nayak #include "powerdomains.h" 24*9b7fc907SRajendra Nayak 25*9b7fc907SRajendra Nayak /* 26*9b7fc907SRajendra Nayak * OMAP3 and OMAP4 specific register bit initialisations 27*9b7fc907SRajendra Nayak * Notice that the names here are not according to each power 28*9b7fc907SRajendra Nayak * domain but the bit mapping used applies to all of them 29*9b7fc907SRajendra Nayak */ 30*9b7fc907SRajendra Nayak /* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */ 31*9b7fc907SRajendra Nayak #define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK 32*9b7fc907SRajendra Nayak #define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK 33*9b7fc907SRajendra Nayak #define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK 34*9b7fc907SRajendra Nayak #define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK 35*9b7fc907SRajendra Nayak #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK 36*9b7fc907SRajendra Nayak 37*9b7fc907SRajendra Nayak /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */ 38*9b7fc907SRajendra Nayak #define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK 39*9b7fc907SRajendra Nayak #define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK 40*9b7fc907SRajendra Nayak #define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK 41*9b7fc907SRajendra Nayak #define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK 42*9b7fc907SRajendra Nayak #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK 43*9b7fc907SRajendra Nayak 44*9b7fc907SRajendra Nayak /* OMAP3 and OMAP4 Memory Status bits */ 45*9b7fc907SRajendra Nayak #define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK 46*9b7fc907SRajendra Nayak #define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK 47*9b7fc907SRajendra Nayak #define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK 48*9b7fc907SRajendra Nayak #define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK 49*9b7fc907SRajendra Nayak #define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK 50*9b7fc907SRajendra Nayak 51*9b7fc907SRajendra Nayak /* Common Internal functions used across OMAP rev's*/ 52*9b7fc907SRajendra Nayak u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank) 53*9b7fc907SRajendra Nayak { 54*9b7fc907SRajendra Nayak switch (bank) { 55*9b7fc907SRajendra Nayak case 0: 56*9b7fc907SRajendra Nayak return OMAP_MEM0_ONSTATE_MASK; 57*9b7fc907SRajendra Nayak case 1: 58*9b7fc907SRajendra Nayak return OMAP_MEM1_ONSTATE_MASK; 59*9b7fc907SRajendra Nayak case 2: 60*9b7fc907SRajendra Nayak return OMAP_MEM2_ONSTATE_MASK; 61*9b7fc907SRajendra Nayak case 3: 62*9b7fc907SRajendra Nayak return OMAP_MEM3_ONSTATE_MASK; 63*9b7fc907SRajendra Nayak case 4: 64*9b7fc907SRajendra Nayak return OMAP_MEM4_ONSTATE_MASK; 65*9b7fc907SRajendra Nayak default: 66*9b7fc907SRajendra Nayak WARN_ON(1); /* should never happen */ 67*9b7fc907SRajendra Nayak return -EEXIST; 68*9b7fc907SRajendra Nayak } 69*9b7fc907SRajendra Nayak return 0; 70*9b7fc907SRajendra Nayak } 71*9b7fc907SRajendra Nayak 72*9b7fc907SRajendra Nayak u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank) 73*9b7fc907SRajendra Nayak { 74*9b7fc907SRajendra Nayak switch (bank) { 75*9b7fc907SRajendra Nayak case 0: 76*9b7fc907SRajendra Nayak return OMAP_MEM0_RETSTATE_MASK; 77*9b7fc907SRajendra Nayak case 1: 78*9b7fc907SRajendra Nayak return OMAP_MEM1_RETSTATE_MASK; 79*9b7fc907SRajendra Nayak case 2: 80*9b7fc907SRajendra Nayak return OMAP_MEM2_RETSTATE_MASK; 81*9b7fc907SRajendra Nayak case 3: 82*9b7fc907SRajendra Nayak return OMAP_MEM3_RETSTATE_MASK; 83*9b7fc907SRajendra Nayak case 4: 84*9b7fc907SRajendra Nayak return OMAP_MEM4_RETSTATE_MASK; 85*9b7fc907SRajendra Nayak default: 86*9b7fc907SRajendra Nayak WARN_ON(1); /* should never happen */ 87*9b7fc907SRajendra Nayak return -EEXIST; 88*9b7fc907SRajendra Nayak } 89*9b7fc907SRajendra Nayak return 0; 90*9b7fc907SRajendra Nayak } 91*9b7fc907SRajendra Nayak 92*9b7fc907SRajendra Nayak u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank) 93*9b7fc907SRajendra Nayak { 94*9b7fc907SRajendra Nayak switch (bank) { 95*9b7fc907SRajendra Nayak case 0: 96*9b7fc907SRajendra Nayak return OMAP_MEM0_STATEST_MASK; 97*9b7fc907SRajendra Nayak case 1: 98*9b7fc907SRajendra Nayak return OMAP_MEM1_STATEST_MASK; 99*9b7fc907SRajendra Nayak case 2: 100*9b7fc907SRajendra Nayak return OMAP_MEM2_STATEST_MASK; 101*9b7fc907SRajendra Nayak case 3: 102*9b7fc907SRajendra Nayak return OMAP_MEM3_STATEST_MASK; 103*9b7fc907SRajendra Nayak case 4: 104*9b7fc907SRajendra Nayak return OMAP_MEM4_STATEST_MASK; 105*9b7fc907SRajendra Nayak default: 106*9b7fc907SRajendra Nayak WARN_ON(1); /* should never happen */ 107*9b7fc907SRajendra Nayak return -EEXIST; 108*9b7fc907SRajendra Nayak } 109*9b7fc907SRajendra Nayak return 0; 110*9b7fc907SRajendra Nayak } 111*9b7fc907SRajendra Nayak 112