xref: /linux/arch/arm/mach-omap2/powerdomain-common.c (revision 8179488a36985d4929cf89be5d9171145a769511)
19b7fc907SRajendra Nayak /*
2*8179488aSPaul Walmsley  * Common powerdomain framework functions
39b7fc907SRajendra Nayak  *
4*8179488aSPaul Walmsley  * Copyright (C) 2010-2011 Texas Instruments, Inc.
59b7fc907SRajendra Nayak  * Copyright (C) 2010 Nokia Corporation
69b7fc907SRajendra Nayak  *
79b7fc907SRajendra Nayak  * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
89b7fc907SRajendra Nayak  *
99b7fc907SRajendra Nayak  * This program is free software; you can redistribute it and/or modify
109b7fc907SRajendra Nayak  * it under the terms of the GNU General Public License version 2 as
119b7fc907SRajendra Nayak  * published by the Free Software Foundation.
129b7fc907SRajendra Nayak  */
139b7fc907SRajendra Nayak 
149b7fc907SRajendra Nayak #include <linux/errno.h>
159b7fc907SRajendra Nayak #include <linux/kernel.h>
169b7fc907SRajendra Nayak #include "pm.h"
179b7fc907SRajendra Nayak #include "cm.h"
189b7fc907SRajendra Nayak #include "cm-regbits-34xx.h"
199b7fc907SRajendra Nayak #include "cm-regbits-44xx.h"
209b7fc907SRajendra Nayak #include "prm-regbits-34xx.h"
219b7fc907SRajendra Nayak #include "prm-regbits-44xx.h"
229b7fc907SRajendra Nayak 
239b7fc907SRajendra Nayak /*
249b7fc907SRajendra Nayak  * OMAP3 and OMAP4 specific register bit initialisations
259b7fc907SRajendra Nayak  * Notice that the names here are not according to each power
269b7fc907SRajendra Nayak  * domain but the bit mapping used applies to all of them
279b7fc907SRajendra Nayak  */
289b7fc907SRajendra Nayak /* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */
299b7fc907SRajendra Nayak #define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK
309b7fc907SRajendra Nayak #define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK
319b7fc907SRajendra Nayak #define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK
329b7fc907SRajendra Nayak #define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK
339b7fc907SRajendra Nayak #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
349b7fc907SRajendra Nayak 
359b7fc907SRajendra Nayak /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
369b7fc907SRajendra Nayak #define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK
379b7fc907SRajendra Nayak #define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK
389b7fc907SRajendra Nayak #define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK
399b7fc907SRajendra Nayak #define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK
409b7fc907SRajendra Nayak #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
419b7fc907SRajendra Nayak 
429b7fc907SRajendra Nayak /* OMAP3 and OMAP4 Memory Status bits */
439b7fc907SRajendra Nayak #define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK
449b7fc907SRajendra Nayak #define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK
459b7fc907SRajendra Nayak #define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK
469b7fc907SRajendra Nayak #define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK
479b7fc907SRajendra Nayak #define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK
489b7fc907SRajendra Nayak 
499b7fc907SRajendra Nayak /* Common Internal functions used across OMAP rev's*/
509b7fc907SRajendra Nayak u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank)
519b7fc907SRajendra Nayak {
529b7fc907SRajendra Nayak 	switch (bank) {
539b7fc907SRajendra Nayak 	case 0:
549b7fc907SRajendra Nayak 		return OMAP_MEM0_ONSTATE_MASK;
559b7fc907SRajendra Nayak 	case 1:
569b7fc907SRajendra Nayak 		return OMAP_MEM1_ONSTATE_MASK;
579b7fc907SRajendra Nayak 	case 2:
589b7fc907SRajendra Nayak 		return OMAP_MEM2_ONSTATE_MASK;
599b7fc907SRajendra Nayak 	case 3:
609b7fc907SRajendra Nayak 		return OMAP_MEM3_ONSTATE_MASK;
619b7fc907SRajendra Nayak 	case 4:
629b7fc907SRajendra Nayak 		return OMAP_MEM4_ONSTATE_MASK;
639b7fc907SRajendra Nayak 	default:
649b7fc907SRajendra Nayak 		WARN_ON(1); /* should never happen */
659b7fc907SRajendra Nayak 		return -EEXIST;
669b7fc907SRajendra Nayak 	}
679b7fc907SRajendra Nayak 	return 0;
689b7fc907SRajendra Nayak }
699b7fc907SRajendra Nayak 
709b7fc907SRajendra Nayak u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank)
719b7fc907SRajendra Nayak {
729b7fc907SRajendra Nayak 	switch (bank) {
739b7fc907SRajendra Nayak 	case 0:
749b7fc907SRajendra Nayak 		return OMAP_MEM0_RETSTATE_MASK;
759b7fc907SRajendra Nayak 	case 1:
769b7fc907SRajendra Nayak 		return OMAP_MEM1_RETSTATE_MASK;
779b7fc907SRajendra Nayak 	case 2:
789b7fc907SRajendra Nayak 		return OMAP_MEM2_RETSTATE_MASK;
799b7fc907SRajendra Nayak 	case 3:
809b7fc907SRajendra Nayak 		return OMAP_MEM3_RETSTATE_MASK;
819b7fc907SRajendra Nayak 	case 4:
829b7fc907SRajendra Nayak 		return OMAP_MEM4_RETSTATE_MASK;
839b7fc907SRajendra Nayak 	default:
849b7fc907SRajendra Nayak 		WARN_ON(1); /* should never happen */
859b7fc907SRajendra Nayak 		return -EEXIST;
869b7fc907SRajendra Nayak 	}
879b7fc907SRajendra Nayak 	return 0;
889b7fc907SRajendra Nayak }
899b7fc907SRajendra Nayak 
909b7fc907SRajendra Nayak u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank)
919b7fc907SRajendra Nayak {
929b7fc907SRajendra Nayak 	switch (bank) {
939b7fc907SRajendra Nayak 	case 0:
949b7fc907SRajendra Nayak 		return OMAP_MEM0_STATEST_MASK;
959b7fc907SRajendra Nayak 	case 1:
969b7fc907SRajendra Nayak 		return OMAP_MEM1_STATEST_MASK;
979b7fc907SRajendra Nayak 	case 2:
989b7fc907SRajendra Nayak 		return OMAP_MEM2_STATEST_MASK;
999b7fc907SRajendra Nayak 	case 3:
1009b7fc907SRajendra Nayak 		return OMAP_MEM3_STATEST_MASK;
1019b7fc907SRajendra Nayak 	case 4:
1029b7fc907SRajendra Nayak 		return OMAP_MEM4_STATEST_MASK;
1039b7fc907SRajendra Nayak 	default:
1049b7fc907SRajendra Nayak 		WARN_ON(1); /* should never happen */
1059b7fc907SRajendra Nayak 		return -EEXIST;
1069b7fc907SRajendra Nayak 	}
1079b7fc907SRajendra Nayak 	return 0;
1089b7fc907SRajendra Nayak }
1099b7fc907SRajendra Nayak 
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