1 /* 2 * OMAP3 Power Management Routines 3 * 4 * Copyright (C) 2006-2008 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * Jouni Hogander 7 * 8 * Copyright (C) 2007 Texas Instruments, Inc. 9 * Rajendra Nayak <rnayak@ti.com> 10 * 11 * Copyright (C) 2005 Texas Instruments, Inc. 12 * Richard Woodruff <r-woodruff2@ti.com> 13 * 14 * Based on pm.c for omap1 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as 18 * published by the Free Software Foundation. 19 */ 20 21 #include <linux/pm.h> 22 #include <linux/suspend.h> 23 #include <linux/interrupt.h> 24 #include <linux/module.h> 25 #include <linux/list.h> 26 #include <linux/err.h> 27 #include <linux/gpio.h> 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 31 #include <plat/sram.h> 32 #include <plat/clockdomain.h> 33 #include <plat/powerdomain.h> 34 #include <plat/control.h> 35 #include <plat/serial.h> 36 #include <plat/sdrc.h> 37 #include <plat/prcm.h> 38 #include <plat/gpmc.h> 39 #include <plat/dma.h> 40 #include <plat/dmtimer.h> 41 42 #include <asm/tlbflush.h> 43 44 #include "cm.h" 45 #include "cm-regbits-34xx.h" 46 #include "prm-regbits-34xx.h" 47 48 #include "prm.h" 49 #include "pm.h" 50 #include "sdrc.h" 51 52 /* Scratchpad offsets */ 53 #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31 54 #define OMAP343X_TABLE_VALUE_OFFSET 0x30 55 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 56 57 u32 enable_off_mode; 58 u32 sleep_while_idle; 59 u32 wakeup_timer_seconds; 60 61 struct power_state { 62 struct powerdomain *pwrdm; 63 u32 next_state; 64 #ifdef CONFIG_SUSPEND 65 u32 saved_state; 66 #endif 67 struct list_head node; 68 }; 69 70 static LIST_HEAD(pwrst_list); 71 72 static void (*_omap_sram_idle)(u32 *addr, int save_state); 73 74 static int (*_omap_save_secure_sram)(u32 *addr); 75 76 static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 77 static struct powerdomain *core_pwrdm, *per_pwrdm; 78 static struct powerdomain *cam_pwrdm; 79 80 static inline void omap3_per_save_context(void) 81 { 82 omap_gpio_save_context(); 83 } 84 85 static inline void omap3_per_restore_context(void) 86 { 87 omap_gpio_restore_context(); 88 } 89 90 static void omap3_enable_io_chain(void) 91 { 92 int timeout = 0; 93 94 if (omap_rev() >= OMAP3430_REV_ES3_1) { 95 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 96 /* Do a readback to assure write has been done */ 97 prm_read_mod_reg(WKUP_MOD, PM_WKEN); 98 99 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) & 100 OMAP3430_ST_IO_CHAIN)) { 101 timeout++; 102 if (timeout > 1000) { 103 printk(KERN_ERR "Wake up daisy chain " 104 "activation failed.\n"); 105 return; 106 } 107 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN, 108 WKUP_MOD, PM_WKST); 109 } 110 } 111 } 112 113 static void omap3_disable_io_chain(void) 114 { 115 if (omap_rev() >= OMAP3430_REV_ES3_1) 116 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 117 } 118 119 static void omap3_core_save_context(void) 120 { 121 u32 control_padconf_off; 122 123 /* Save the padconf registers */ 124 control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 125 control_padconf_off |= START_PADCONF_SAVE; 126 omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); 127 /* wait for the save to complete */ 128 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 129 & PADCONF_SAVE_DONE)) 130 udelay(1); 131 132 /* 133 * Force write last pad into memory, as this can fail in some 134 * cases according to erratas 1.157, 1.185 135 */ 136 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 137 OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 138 139 /* Save the Interrupt controller context */ 140 omap_intc_save_context(); 141 /* Save the GPMC context */ 142 omap3_gpmc_save_context(); 143 /* Save the system control module context, padconf already save above*/ 144 omap3_control_save_context(); 145 omap_dma_global_context_save(); 146 } 147 148 static void omap3_core_restore_context(void) 149 { 150 /* Restore the control module context, padconf restored by h/w */ 151 omap3_control_restore_context(); 152 /* Restore the GPMC context */ 153 omap3_gpmc_restore_context(); 154 /* Restore the interrupt controller context */ 155 omap_intc_restore_context(); 156 omap_dma_global_context_restore(); 157 } 158 159 /* 160 * FIXME: This function should be called before entering off-mode after 161 * OMAP3 secure services have been accessed. Currently it is only called 162 * once during boot sequence, but this works as we are not using secure 163 * services. 164 */ 165 static void omap3_save_secure_ram_context(u32 target_mpu_state) 166 { 167 u32 ret; 168 169 if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 170 /* 171 * MPU next state must be set to POWER_ON temporarily, 172 * otherwise the WFI executed inside the ROM code 173 * will hang the system. 174 */ 175 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 176 ret = _omap_save_secure_sram((u32 *) 177 __pa(omap3_secure_ram_storage)); 178 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); 179 /* Following is for error tracking, it should not happen */ 180 if (ret) { 181 printk(KERN_ERR "save_secure_sram() returns %08x\n", 182 ret); 183 while (1) 184 ; 185 } 186 } 187 } 188 189 /* 190 * PRCM Interrupt Handler Helper Function 191 * 192 * The purpose of this function is to clear any wake-up events latched 193 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 194 * may occur whilst attempting to clear a PM_WKST_x register and thus 195 * set another bit in this register. A while loop is used to ensure 196 * that any peripheral wake-up events occurring while attempting to 197 * clear the PM_WKST_x are detected and cleared. 198 */ 199 static int prcm_clear_mod_irqs(s16 module, u8 regs) 200 { 201 u32 wkst, fclk, iclk, clken; 202 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 203 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 204 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 205 u16 grpsel_off = (regs == 3) ? 206 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 207 int c = 0; 208 209 wkst = prm_read_mod_reg(module, wkst_off); 210 wkst &= prm_read_mod_reg(module, grpsel_off); 211 if (wkst) { 212 iclk = cm_read_mod_reg(module, iclk_off); 213 fclk = cm_read_mod_reg(module, fclk_off); 214 while (wkst) { 215 clken = wkst; 216 cm_set_mod_reg_bits(clken, module, iclk_off); 217 /* 218 * For USBHOST, we don't know whether HOST1 or 219 * HOST2 woke us up, so enable both f-clocks 220 */ 221 if (module == OMAP3430ES2_USBHOST_MOD) 222 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 223 cm_set_mod_reg_bits(clken, module, fclk_off); 224 prm_write_mod_reg(wkst, module, wkst_off); 225 wkst = prm_read_mod_reg(module, wkst_off); 226 c++; 227 } 228 cm_write_mod_reg(iclk, module, iclk_off); 229 cm_write_mod_reg(fclk, module, fclk_off); 230 } 231 232 return c; 233 } 234 235 static int _prcm_int_handle_wakeup(void) 236 { 237 int c; 238 239 c = prcm_clear_mod_irqs(WKUP_MOD, 1); 240 c += prcm_clear_mod_irqs(CORE_MOD, 1); 241 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 242 if (omap_rev() > OMAP3430_REV_ES1_0) { 243 c += prcm_clear_mod_irqs(CORE_MOD, 3); 244 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 245 } 246 247 return c; 248 } 249 250 /* 251 * PRCM Interrupt Handler 252 * 253 * The PRM_IRQSTATUS_MPU register indicates if there are any pending 254 * interrupts from the PRCM for the MPU. These bits must be cleared in 255 * order to clear the PRCM interrupt. The PRCM interrupt handler is 256 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 257 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 258 * register indicates that a wake-up event is pending for the MPU and 259 * this bit can only be cleared if the all the wake-up events latched 260 * in the various PM_WKST_x registers have been cleared. The interrupt 261 * handler is implemented using a do-while loop so that if a wake-up 262 * event occurred during the processing of the prcm interrupt handler 263 * (setting a bit in the corresponding PM_WKST_x register and thus 264 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 265 * this would be handled. 266 */ 267 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 268 { 269 u32 irqstatus_mpu; 270 int c = 0; 271 272 do { 273 irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 274 OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 275 276 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) { 277 c = _prcm_int_handle_wakeup(); 278 279 /* 280 * Is the MPU PRCM interrupt handler racing with the 281 * IVA2 PRCM interrupt handler ? 282 */ 283 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 284 "but no wakeup sources are marked\n"); 285 } else { 286 /* XXX we need to expand our PRCM interrupt handler */ 287 WARN(1, "prcm: WARNING: PRCM interrupt received, but " 288 "no code to handle it (%08x)\n", irqstatus_mpu); 289 } 290 291 prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 292 OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 293 294 } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); 295 296 return IRQ_HANDLED; 297 } 298 299 static void restore_control_register(u32 val) 300 { 301 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); 302 } 303 304 /* Function to restore the table entry that was modified for enabling MMU */ 305 static void restore_table_entry(void) 306 { 307 u32 *scratchpad_address; 308 u32 previous_value, control_reg_value; 309 u32 *address; 310 311 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 312 313 /* Get address of entry that was modified */ 314 address = (u32 *)__raw_readl(scratchpad_address + 315 OMAP343X_TABLE_ADDRESS_OFFSET); 316 /* Get the previous value which needs to be restored */ 317 previous_value = __raw_readl(scratchpad_address + 318 OMAP343X_TABLE_VALUE_OFFSET); 319 address = __va(address); 320 *address = previous_value; 321 flush_tlb_all(); 322 control_reg_value = __raw_readl(scratchpad_address 323 + OMAP343X_CONTROL_REG_VALUE_OFFSET); 324 /* This will enable caches and prediction */ 325 restore_control_register(control_reg_value); 326 } 327 328 void omap_sram_idle(void) 329 { 330 /* Variable to tell what needs to be saved and restored 331 * in omap_sram_idle*/ 332 /* save_state = 0 => Nothing to save and restored */ 333 /* save_state = 1 => Only L1 and logic lost */ 334 /* save_state = 2 => Only L2 lost */ 335 /* save_state = 3 => L1, L2 and logic lost */ 336 int save_state = 0; 337 int mpu_next_state = PWRDM_POWER_ON; 338 int per_next_state = PWRDM_POWER_ON; 339 int core_next_state = PWRDM_POWER_ON; 340 int core_prev_state, per_prev_state; 341 u32 sdrc_pwr = 0; 342 int per_state_modified = 0; 343 344 if (!_omap_sram_idle) 345 return; 346 347 pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 348 pwrdm_clear_all_prev_pwrst(neon_pwrdm); 349 pwrdm_clear_all_prev_pwrst(core_pwrdm); 350 pwrdm_clear_all_prev_pwrst(per_pwrdm); 351 352 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 353 switch (mpu_next_state) { 354 case PWRDM_POWER_ON: 355 case PWRDM_POWER_RET: 356 /* No need to save context */ 357 save_state = 0; 358 break; 359 case PWRDM_POWER_OFF: 360 save_state = 3; 361 break; 362 default: 363 /* Invalid state */ 364 printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 365 return; 366 } 367 pwrdm_pre_transition(); 368 369 /* NEON control */ 370 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 371 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 372 373 /* PER */ 374 per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 375 core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 376 if (per_next_state < PWRDM_POWER_ON) { 377 omap_uart_prepare_idle(2); 378 omap2_gpio_prepare_for_retention(); 379 if (per_next_state == PWRDM_POWER_OFF) { 380 if (core_next_state == PWRDM_POWER_ON) { 381 per_next_state = PWRDM_POWER_RET; 382 pwrdm_set_next_pwrst(per_pwrdm, per_next_state); 383 per_state_modified = 1; 384 } else 385 omap3_per_save_context(); 386 } 387 } 388 389 if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) 390 omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]); 391 392 /* CORE */ 393 if (core_next_state < PWRDM_POWER_ON) { 394 omap_uart_prepare_idle(0); 395 omap_uart_prepare_idle(1); 396 if (core_next_state == PWRDM_POWER_OFF) { 397 omap3_core_save_context(); 398 omap3_prcm_save_context(); 399 } 400 /* Enable IO-PAD and IO-CHAIN wakeups */ 401 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 402 omap3_enable_io_chain(); 403 } 404 omap3_intc_prepare_idle(); 405 406 /* 407 * On EMU/HS devices ROM code restores a SRDC value 408 * from scratchpad which has automatic self refresh on timeout 409 * of AUTO_CNT = 1 enabled. This takes care of errata 1.142. 410 * Hence store/restore the SDRC_POWER register here. 411 */ 412 if (omap_rev() >= OMAP3430_REV_ES3_0 && 413 omap_type() != OMAP2_DEVICE_TYPE_GP && 414 core_next_state == PWRDM_POWER_OFF) 415 sdrc_pwr = sdrc_read_reg(SDRC_POWER); 416 417 /* 418 * omap3_arm_context is the location where ARM registers 419 * get saved. The restore path then reads from this 420 * location and restores them back. 421 */ 422 _omap_sram_idle(omap3_arm_context, save_state); 423 cpu_init(); 424 425 /* Restore normal SDRC POWER settings */ 426 if (omap_rev() >= OMAP3430_REV_ES3_0 && 427 omap_type() != OMAP2_DEVICE_TYPE_GP && 428 core_next_state == PWRDM_POWER_OFF) 429 sdrc_write_reg(sdrc_pwr, SDRC_POWER); 430 431 /* Restore table entry modified during MMU restoration */ 432 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) 433 restore_table_entry(); 434 435 /* CORE */ 436 if (core_next_state < PWRDM_POWER_ON) { 437 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 438 if (core_prev_state == PWRDM_POWER_OFF) { 439 omap3_core_restore_context(); 440 omap3_prcm_restore_context(); 441 omap3_sram_restore_context(); 442 omap2_sms_restore_context(); 443 } 444 omap_uart_resume_idle(0); 445 omap_uart_resume_idle(1); 446 if (core_next_state == PWRDM_POWER_OFF) 447 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF, 448 OMAP3430_GR_MOD, 449 OMAP3_PRM_VOLTCTRL_OFFSET); 450 } 451 omap3_intc_resume_idle(); 452 453 /* PER */ 454 if (per_next_state < PWRDM_POWER_ON) { 455 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 456 if (per_prev_state == PWRDM_POWER_OFF) 457 omap3_per_restore_context(); 458 omap2_gpio_resume_after_retention(); 459 omap_uart_resume_idle(2); 460 if (per_state_modified) 461 pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); 462 } 463 464 /* Disable IO-PAD and IO-CHAIN wakeup */ 465 if (core_next_state < PWRDM_POWER_ON) { 466 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 467 omap3_disable_io_chain(); 468 } 469 470 pwrdm_post_transition(); 471 472 omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 473 } 474 475 int omap3_can_sleep(void) 476 { 477 if (!sleep_while_idle) 478 return 0; 479 if (!omap_uart_can_sleep()) 480 return 0; 481 return 1; 482 } 483 484 /* This sets pwrdm state (other than mpu & core. Currently only ON & 485 * RET are supported. Function is assuming that clkdm doesn't have 486 * hw_sup mode enabled. */ 487 int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) 488 { 489 u32 cur_state; 490 int sleep_switch = 0; 491 int ret = 0; 492 493 if (pwrdm == NULL || IS_ERR(pwrdm)) 494 return -EINVAL; 495 496 while (!(pwrdm->pwrsts & (1 << state))) { 497 if (state == PWRDM_POWER_OFF) 498 return ret; 499 state--; 500 } 501 502 cur_state = pwrdm_read_next_pwrst(pwrdm); 503 if (cur_state == state) 504 return ret; 505 506 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { 507 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); 508 sleep_switch = 1; 509 pwrdm_wait_transition(pwrdm); 510 } 511 512 ret = pwrdm_set_next_pwrst(pwrdm, state); 513 if (ret) { 514 printk(KERN_ERR "Unable to set state of powerdomain: %s\n", 515 pwrdm->name); 516 goto err; 517 } 518 519 if (sleep_switch) { 520 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); 521 pwrdm_wait_transition(pwrdm); 522 pwrdm_state_switch(pwrdm); 523 } 524 525 err: 526 return ret; 527 } 528 529 static void omap3_pm_idle(void) 530 { 531 local_irq_disable(); 532 local_fiq_disable(); 533 534 if (!omap3_can_sleep()) 535 goto out; 536 537 if (omap_irq_pending() || need_resched()) 538 goto out; 539 540 omap_sram_idle(); 541 542 out: 543 local_fiq_enable(); 544 local_irq_enable(); 545 } 546 547 #ifdef CONFIG_SUSPEND 548 static suspend_state_t suspend_state; 549 550 static void omap2_pm_wakeup_on_timer(u32 seconds) 551 { 552 u32 tick_rate, cycles; 553 554 if (!seconds) 555 return; 556 557 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); 558 cycles = tick_rate * seconds; 559 omap_dm_timer_stop(gptimer_wakeup); 560 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); 561 562 pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n", 563 seconds, cycles, tick_rate); 564 } 565 566 static int omap3_pm_prepare(void) 567 { 568 disable_hlt(); 569 return 0; 570 } 571 572 static int omap3_pm_suspend(void) 573 { 574 struct power_state *pwrst; 575 int state, ret = 0; 576 577 if (wakeup_timer_seconds) 578 omap2_pm_wakeup_on_timer(wakeup_timer_seconds); 579 580 /* Read current next_pwrsts */ 581 list_for_each_entry(pwrst, &pwrst_list, node) 582 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 583 /* Set ones wanted by suspend */ 584 list_for_each_entry(pwrst, &pwrst_list, node) { 585 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 586 goto restore; 587 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 588 goto restore; 589 } 590 591 omap_uart_prepare_suspend(); 592 omap3_intc_suspend(); 593 594 omap_sram_idle(); 595 596 restore: 597 /* Restore next_pwrsts */ 598 list_for_each_entry(pwrst, &pwrst_list, node) { 599 state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 600 if (state > pwrst->next_state) { 601 printk(KERN_INFO "Powerdomain (%s) didn't enter " 602 "target state %d\n", 603 pwrst->pwrdm->name, pwrst->next_state); 604 ret = -1; 605 } 606 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 607 } 608 if (ret) 609 printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 610 else 611 printk(KERN_INFO "Successfully put all powerdomains " 612 "to target state\n"); 613 614 return ret; 615 } 616 617 static int omap3_pm_enter(suspend_state_t unused) 618 { 619 int ret = 0; 620 621 switch (suspend_state) { 622 case PM_SUSPEND_STANDBY: 623 case PM_SUSPEND_MEM: 624 ret = omap3_pm_suspend(); 625 break; 626 default: 627 ret = -EINVAL; 628 } 629 630 return ret; 631 } 632 633 static void omap3_pm_finish(void) 634 { 635 enable_hlt(); 636 } 637 638 /* Hooks to enable / disable UART interrupts during suspend */ 639 static int omap3_pm_begin(suspend_state_t state) 640 { 641 suspend_state = state; 642 omap_uart_enable_irqs(0); 643 return 0; 644 } 645 646 static void omap3_pm_end(void) 647 { 648 suspend_state = PM_SUSPEND_ON; 649 omap_uart_enable_irqs(1); 650 return; 651 } 652 653 static struct platform_suspend_ops omap_pm_ops = { 654 .begin = omap3_pm_begin, 655 .end = omap3_pm_end, 656 .prepare = omap3_pm_prepare, 657 .enter = omap3_pm_enter, 658 .finish = omap3_pm_finish, 659 .valid = suspend_valid_only_mem, 660 }; 661 #endif /* CONFIG_SUSPEND */ 662 663 664 /** 665 * omap3_iva_idle(): ensure IVA is in idle so it can be put into 666 * retention 667 * 668 * In cases where IVA2 is activated by bootcode, it may prevent 669 * full-chip retention or off-mode because it is not idle. This 670 * function forces the IVA2 into idle state so it can go 671 * into retention/off and thus allow full-chip retention/off. 672 * 673 **/ 674 static void __init omap3_iva_idle(void) 675 { 676 /* ensure IVA2 clock is disabled */ 677 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 678 679 /* if no clock activity, nothing else to do */ 680 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 681 OMAP3430_CLKACTIVITY_IVA2_MASK)) 682 return; 683 684 /* Reset IVA2 */ 685 prm_write_mod_reg(OMAP3430_RST1_IVA2 | 686 OMAP3430_RST2_IVA2 | 687 OMAP3430_RST3_IVA2, 688 OMAP3430_IVA2_MOD, RM_RSTCTRL); 689 690 /* Enable IVA2 clock */ 691 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, 692 OMAP3430_IVA2_MOD, CM_FCLKEN); 693 694 /* Set IVA2 boot mode to 'idle' */ 695 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 696 OMAP343X_CONTROL_IVA2_BOOTMOD); 697 698 /* Un-reset IVA2 */ 699 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); 700 701 /* Disable IVA2 clock */ 702 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 703 704 /* Reset IVA2 */ 705 prm_write_mod_reg(OMAP3430_RST1_IVA2 | 706 OMAP3430_RST2_IVA2 | 707 OMAP3430_RST3_IVA2, 708 OMAP3430_IVA2_MOD, RM_RSTCTRL); 709 } 710 711 static void __init omap3_d2d_idle(void) 712 { 713 u16 mask, padconf; 714 715 /* In a stand alone OMAP3430 where there is not a stacked 716 * modem for the D2D Idle Ack and D2D MStandby must be pulled 717 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 718 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 719 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 720 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 721 padconf |= mask; 722 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 723 724 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 725 padconf |= mask; 726 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 727 728 /* reset modem */ 729 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | 730 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, 731 CORE_MOD, RM_RSTCTRL); 732 prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); 733 } 734 735 static void __init prcm_setup_regs(void) 736 { 737 /* XXX Reset all wkdeps. This should be done when initializing 738 * powerdomains */ 739 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 740 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 741 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 742 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 743 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 744 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 745 if (omap_rev() > OMAP3430_REV_ES1_0) { 746 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 747 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 748 } else 749 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 750 751 /* 752 * Enable interface clock autoidle for all modules. 753 * Note that in the long run this should be done by clockfw 754 */ 755 cm_write_mod_reg( 756 OMAP3430_AUTO_MODEM | 757 OMAP3430ES2_AUTO_MMC3 | 758 OMAP3430ES2_AUTO_ICR | 759 OMAP3430_AUTO_AES2 | 760 OMAP3430_AUTO_SHA12 | 761 OMAP3430_AUTO_DES2 | 762 OMAP3430_AUTO_MMC2 | 763 OMAP3430_AUTO_MMC1 | 764 OMAP3430_AUTO_MSPRO | 765 OMAP3430_AUTO_HDQ | 766 OMAP3430_AUTO_MCSPI4 | 767 OMAP3430_AUTO_MCSPI3 | 768 OMAP3430_AUTO_MCSPI2 | 769 OMAP3430_AUTO_MCSPI1 | 770 OMAP3430_AUTO_I2C3 | 771 OMAP3430_AUTO_I2C2 | 772 OMAP3430_AUTO_I2C1 | 773 OMAP3430_AUTO_UART2 | 774 OMAP3430_AUTO_UART1 | 775 OMAP3430_AUTO_GPT11 | 776 OMAP3430_AUTO_GPT10 | 777 OMAP3430_AUTO_MCBSP5 | 778 OMAP3430_AUTO_MCBSP1 | 779 OMAP3430ES1_AUTO_FAC | /* This is es1 only */ 780 OMAP3430_AUTO_MAILBOXES | 781 OMAP3430_AUTO_OMAPCTRL | 782 OMAP3430ES1_AUTO_FSHOSTUSB | 783 OMAP3430_AUTO_HSOTGUSB | 784 OMAP3430_AUTO_SAD2D | 785 OMAP3430_AUTO_SSI, 786 CORE_MOD, CM_AUTOIDLE1); 787 788 cm_write_mod_reg( 789 OMAP3430_AUTO_PKA | 790 OMAP3430_AUTO_AES1 | 791 OMAP3430_AUTO_RNG | 792 OMAP3430_AUTO_SHA11 | 793 OMAP3430_AUTO_DES1, 794 CORE_MOD, CM_AUTOIDLE2); 795 796 if (omap_rev() > OMAP3430_REV_ES1_0) { 797 cm_write_mod_reg( 798 OMAP3430_AUTO_MAD2D | 799 OMAP3430ES2_AUTO_USBTLL, 800 CORE_MOD, CM_AUTOIDLE3); 801 } 802 803 cm_write_mod_reg( 804 OMAP3430_AUTO_WDT2 | 805 OMAP3430_AUTO_WDT1 | 806 OMAP3430_AUTO_GPIO1 | 807 OMAP3430_AUTO_32KSYNC | 808 OMAP3430_AUTO_GPT12 | 809 OMAP3430_AUTO_GPT1 , 810 WKUP_MOD, CM_AUTOIDLE); 811 812 cm_write_mod_reg( 813 OMAP3430_AUTO_DSS, 814 OMAP3430_DSS_MOD, 815 CM_AUTOIDLE); 816 817 cm_write_mod_reg( 818 OMAP3430_AUTO_CAM, 819 OMAP3430_CAM_MOD, 820 CM_AUTOIDLE); 821 822 cm_write_mod_reg( 823 OMAP3430_AUTO_GPIO6 | 824 OMAP3430_AUTO_GPIO5 | 825 OMAP3430_AUTO_GPIO4 | 826 OMAP3430_AUTO_GPIO3 | 827 OMAP3430_AUTO_GPIO2 | 828 OMAP3430_AUTO_WDT3 | 829 OMAP3430_AUTO_UART3 | 830 OMAP3430_AUTO_GPT9 | 831 OMAP3430_AUTO_GPT8 | 832 OMAP3430_AUTO_GPT7 | 833 OMAP3430_AUTO_GPT6 | 834 OMAP3430_AUTO_GPT5 | 835 OMAP3430_AUTO_GPT4 | 836 OMAP3430_AUTO_GPT3 | 837 OMAP3430_AUTO_GPT2 | 838 OMAP3430_AUTO_MCBSP4 | 839 OMAP3430_AUTO_MCBSP3 | 840 OMAP3430_AUTO_MCBSP2, 841 OMAP3430_PER_MOD, 842 CM_AUTOIDLE); 843 844 if (omap_rev() > OMAP3430_REV_ES1_0) { 845 cm_write_mod_reg( 846 OMAP3430ES2_AUTO_USBHOST, 847 OMAP3430ES2_USBHOST_MOD, 848 CM_AUTOIDLE); 849 } 850 851 omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG); 852 853 /* 854 * Set all plls to autoidle. This is needed until autoidle is 855 * enabled by clockfw 856 */ 857 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 858 OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 859 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 860 MPU_MOD, 861 CM_AUTOIDLE2); 862 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 863 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 864 PLL_MOD, 865 CM_AUTOIDLE); 866 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 867 PLL_MOD, 868 CM_AUTOIDLE2); 869 870 /* 871 * Enable control of expternal oscillator through 872 * sys_clkreq. In the long run clock framework should 873 * take care of this. 874 */ 875 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 876 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 877 OMAP3430_GR_MOD, 878 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 879 880 /* setup wakup source */ 881 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | 882 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, 883 WKUP_MOD, PM_WKEN); 884 /* No need to write EN_IO, that is always enabled */ 885 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | 886 OMAP3430_EN_GPT12, 887 WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 888 /* For some reason IO doesn't generate wakeup event even if 889 * it is selected to mpu wakeup goup */ 890 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 891 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 892 893 /* Enable PM_WKEN to support DSS LPR */ 894 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS, 895 OMAP3430_DSS_MOD, PM_WKEN); 896 897 /* Enable wakeups in PER */ 898 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | 899 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | 900 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 | 901 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | 902 OMAP3430_EN_MCBSP4, 903 OMAP3430_PER_MOD, PM_WKEN); 904 /* and allow them to wake up MPU */ 905 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | 906 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | 907 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 | 908 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | 909 OMAP3430_EN_MCBSP4, 910 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 911 912 /* Don't attach IVA interrupts */ 913 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 914 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 915 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 916 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 917 918 /* Clear any pending 'reset' flags */ 919 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 920 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 921 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 922 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 923 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 924 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 925 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 926 927 /* Clear any pending PRCM interrupts */ 928 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 929 930 omap3_iva_idle(); 931 omap3_d2d_idle(); 932 } 933 934 void omap3_pm_off_mode_enable(int enable) 935 { 936 struct power_state *pwrst; 937 u32 state; 938 939 if (enable) 940 state = PWRDM_POWER_OFF; 941 else 942 state = PWRDM_POWER_RET; 943 944 list_for_each_entry(pwrst, &pwrst_list, node) { 945 pwrst->next_state = state; 946 set_pwrdm_state(pwrst->pwrdm, state); 947 } 948 } 949 950 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 951 { 952 struct power_state *pwrst; 953 954 list_for_each_entry(pwrst, &pwrst_list, node) { 955 if (pwrst->pwrdm == pwrdm) 956 return pwrst->next_state; 957 } 958 return -EINVAL; 959 } 960 961 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 962 { 963 struct power_state *pwrst; 964 965 list_for_each_entry(pwrst, &pwrst_list, node) { 966 if (pwrst->pwrdm == pwrdm) { 967 pwrst->next_state = state; 968 return 0; 969 } 970 } 971 return -EINVAL; 972 } 973 974 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 975 { 976 struct power_state *pwrst; 977 978 if (!pwrdm->pwrsts) 979 return 0; 980 981 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 982 if (!pwrst) 983 return -ENOMEM; 984 pwrst->pwrdm = pwrdm; 985 pwrst->next_state = PWRDM_POWER_RET; 986 list_add(&pwrst->node, &pwrst_list); 987 988 if (pwrdm_has_hdwr_sar(pwrdm)) 989 pwrdm_enable_hdwr_sar(pwrdm); 990 991 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 992 } 993 994 /* 995 * Enable hw supervised mode for all clockdomains if it's 996 * supported. Initiate sleep transition for other clockdomains, if 997 * they are not used 998 */ 999 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 1000 { 1001 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 1002 omap2_clkdm_allow_idle(clkdm); 1003 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 1004 atomic_read(&clkdm->usecount) == 0) 1005 omap2_clkdm_sleep(clkdm); 1006 return 0; 1007 } 1008 1009 void omap_push_sram_idle(void) 1010 { 1011 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 1012 omap34xx_cpu_suspend_sz); 1013 if (omap_type() != OMAP2_DEVICE_TYPE_GP) 1014 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 1015 save_secure_ram_context_sz); 1016 } 1017 1018 static int __init omap3_pm_init(void) 1019 { 1020 struct power_state *pwrst, *tmp; 1021 int ret; 1022 1023 if (!cpu_is_omap34xx()) 1024 return -ENODEV; 1025 1026 printk(KERN_ERR "Power Management for TI OMAP3.\n"); 1027 1028 /* XXX prcm_setup_regs needs to be before enabling hw 1029 * supervised mode for powerdomains */ 1030 prcm_setup_regs(); 1031 1032 ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 1033 (irq_handler_t)prcm_interrupt_handler, 1034 IRQF_DISABLED, "prcm", NULL); 1035 if (ret) { 1036 printk(KERN_ERR "request_irq failed to register for 0x%x\n", 1037 INT_34XX_PRCM_MPU_IRQ); 1038 goto err1; 1039 } 1040 1041 ret = pwrdm_for_each(pwrdms_setup, NULL); 1042 if (ret) { 1043 printk(KERN_ERR "Failed to setup powerdomains\n"); 1044 goto err2; 1045 } 1046 1047 (void) clkdm_for_each(clkdms_setup, NULL); 1048 1049 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 1050 if (mpu_pwrdm == NULL) { 1051 printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 1052 goto err2; 1053 } 1054 1055 neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 1056 per_pwrdm = pwrdm_lookup("per_pwrdm"); 1057 core_pwrdm = pwrdm_lookup("core_pwrdm"); 1058 cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 1059 1060 omap_push_sram_idle(); 1061 #ifdef CONFIG_SUSPEND 1062 suspend_set_ops(&omap_pm_ops); 1063 #endif /* CONFIG_SUSPEND */ 1064 1065 pm_idle = omap3_pm_idle; 1066 omap3_idle_init(); 1067 1068 pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm); 1069 /* 1070 * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for 1071 * IO-pad wakeup. Otherwise it will unnecessarily waste power 1072 * waking up PER with every CORE wakeup - see 1073 * http://marc.info/?l=linux-omap&m=121852150710062&w=2 1074 */ 1075 pwrdm_add_wkdep(per_pwrdm, core_pwrdm); 1076 1077 if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 1078 omap3_secure_ram_storage = 1079 kmalloc(0x803F, GFP_KERNEL); 1080 if (!omap3_secure_ram_storage) 1081 printk(KERN_ERR "Memory allocation failed when" 1082 "allocating for secure sram context\n"); 1083 1084 local_irq_disable(); 1085 local_fiq_disable(); 1086 1087 omap_dma_global_context_save(); 1088 omap3_save_secure_ram_context(PWRDM_POWER_ON); 1089 omap_dma_global_context_restore(); 1090 1091 local_irq_enable(); 1092 local_fiq_enable(); 1093 } 1094 1095 omap3_save_scratchpad_contents(); 1096 err1: 1097 return ret; 1098 err2: 1099 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 1100 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 1101 list_del(&pwrst->node); 1102 kfree(pwrst); 1103 } 1104 return ret; 1105 } 1106 1107 late_initcall(omap3_pm_init); 1108