1 /* 2 * OMAP3 Power Management Routines 3 * 4 * Copyright (C) 2006-2008 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * Jouni Hogander 7 * 8 * Copyright (C) 2007 Texas Instruments, Inc. 9 * Rajendra Nayak <rnayak@ti.com> 10 * 11 * Copyright (C) 2005 Texas Instruments, Inc. 12 * Richard Woodruff <r-woodruff2@ti.com> 13 * 14 * Based on pm.c for omap1 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as 18 * published by the Free Software Foundation. 19 */ 20 21 #include <linux/pm.h> 22 #include <linux/suspend.h> 23 #include <linux/interrupt.h> 24 #include <linux/module.h> 25 #include <linux/list.h> 26 #include <linux/err.h> 27 #include <linux/gpio.h> 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 #include <linux/slab.h> 31 #include <trace/events/power.h> 32 33 #include <asm/suspend.h> 34 #include <asm/system_misc.h> 35 36 #include <plat/sram.h> 37 #include "clockdomain.h" 38 #include "powerdomain.h" 39 #include <plat/sdrc.h> 40 #include <plat/prcm.h> 41 #include <plat/gpmc.h> 42 #include <plat/dma.h> 43 44 #include "common.h" 45 #include "cm2xxx_3xxx.h" 46 #include "cm-regbits-34xx.h" 47 #include "prm-regbits-34xx.h" 48 49 #include "prm2xxx_3xxx.h" 50 #include "pm.h" 51 #include "sdrc.h" 52 #include "control.h" 53 54 /* pm34xx errata defined in pm.h */ 55 u16 pm34xx_errata; 56 57 struct power_state { 58 struct powerdomain *pwrdm; 59 u32 next_state; 60 #ifdef CONFIG_SUSPEND 61 u32 saved_state; 62 #endif 63 struct list_head node; 64 }; 65 66 static LIST_HEAD(pwrst_list); 67 68 static int (*_omap_save_secure_sram)(u32 *addr); 69 void (*omap3_do_wfi_sram)(void); 70 71 static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 72 static struct powerdomain *core_pwrdm, *per_pwrdm; 73 static struct powerdomain *cam_pwrdm; 74 75 static void omap3_enable_io_chain(void) 76 { 77 int timeout = 0; 78 79 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 80 PM_WKEN); 81 /* Do a readback to assure write has been done */ 82 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); 83 84 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & 85 OMAP3430_ST_IO_CHAIN_MASK)) { 86 timeout++; 87 if (timeout > 1000) { 88 pr_err("Wake up daisy chain activation failed.\n"); 89 return; 90 } 91 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, 92 WKUP_MOD, PM_WKEN); 93 } 94 } 95 96 static void omap3_disable_io_chain(void) 97 { 98 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 99 PM_WKEN); 100 } 101 102 static void omap3_core_save_context(void) 103 { 104 omap3_ctrl_save_padconf(); 105 106 /* 107 * Force write last pad into memory, as this can fail in some 108 * cases according to errata 1.157, 1.185 109 */ 110 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 111 OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 112 113 /* Save the Interrupt controller context */ 114 omap_intc_save_context(); 115 /* Save the GPMC context */ 116 omap3_gpmc_save_context(); 117 /* Save the system control module context, padconf already save above*/ 118 omap3_control_save_context(); 119 omap_dma_global_context_save(); 120 } 121 122 static void omap3_core_restore_context(void) 123 { 124 /* Restore the control module context, padconf restored by h/w */ 125 omap3_control_restore_context(); 126 /* Restore the GPMC context */ 127 omap3_gpmc_restore_context(); 128 /* Restore the interrupt controller context */ 129 omap_intc_restore_context(); 130 omap_dma_global_context_restore(); 131 } 132 133 /* 134 * FIXME: This function should be called before entering off-mode after 135 * OMAP3 secure services have been accessed. Currently it is only called 136 * once during boot sequence, but this works as we are not using secure 137 * services. 138 */ 139 static void omap3_save_secure_ram_context(void) 140 { 141 u32 ret; 142 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 143 144 if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 145 /* 146 * MPU next state must be set to POWER_ON temporarily, 147 * otherwise the WFI executed inside the ROM code 148 * will hang the system. 149 */ 150 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 151 ret = _omap_save_secure_sram((u32 *) 152 __pa(omap3_secure_ram_storage)); 153 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 154 /* Following is for error tracking, it should not happen */ 155 if (ret) { 156 pr_err("save_secure_sram() returns %08x\n", ret); 157 while (1) 158 ; 159 } 160 } 161 } 162 163 /* 164 * PRCM Interrupt Handler Helper Function 165 * 166 * The purpose of this function is to clear any wake-up events latched 167 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 168 * may occur whilst attempting to clear a PM_WKST_x register and thus 169 * set another bit in this register. A while loop is used to ensure 170 * that any peripheral wake-up events occurring while attempting to 171 * clear the PM_WKST_x are detected and cleared. 172 */ 173 static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) 174 { 175 u32 wkst, fclk, iclk, clken; 176 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 177 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 178 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 179 u16 grpsel_off = (regs == 3) ? 180 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 181 int c = 0; 182 183 wkst = omap2_prm_read_mod_reg(module, wkst_off); 184 wkst &= omap2_prm_read_mod_reg(module, grpsel_off); 185 wkst &= ~ignore_bits; 186 if (wkst) { 187 iclk = omap2_cm_read_mod_reg(module, iclk_off); 188 fclk = omap2_cm_read_mod_reg(module, fclk_off); 189 while (wkst) { 190 clken = wkst; 191 omap2_cm_set_mod_reg_bits(clken, module, iclk_off); 192 /* 193 * For USBHOST, we don't know whether HOST1 or 194 * HOST2 woke us up, so enable both f-clocks 195 */ 196 if (module == OMAP3430ES2_USBHOST_MOD) 197 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 198 omap2_cm_set_mod_reg_bits(clken, module, fclk_off); 199 omap2_prm_write_mod_reg(wkst, module, wkst_off); 200 wkst = omap2_prm_read_mod_reg(module, wkst_off); 201 wkst &= ~ignore_bits; 202 c++; 203 } 204 omap2_cm_write_mod_reg(iclk, module, iclk_off); 205 omap2_cm_write_mod_reg(fclk, module, fclk_off); 206 } 207 208 return c; 209 } 210 211 static irqreturn_t _prcm_int_handle_io(int irq, void *unused) 212 { 213 int c; 214 215 c = prcm_clear_mod_irqs(WKUP_MOD, 1, 216 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK)); 217 218 return c ? IRQ_HANDLED : IRQ_NONE; 219 } 220 221 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) 222 { 223 int c; 224 225 /* 226 * Clear all except ST_IO and ST_IO_CHAIN for wkup module, 227 * these are handled in a separate handler to avoid acking 228 * IO events before parsing in mux code 229 */ 230 c = prcm_clear_mod_irqs(WKUP_MOD, 1, 231 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK); 232 c += prcm_clear_mod_irqs(CORE_MOD, 1, 0); 233 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); 234 if (omap_rev() > OMAP3430_REV_ES1_0) { 235 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0); 236 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); 237 } 238 239 return c ? IRQ_HANDLED : IRQ_NONE; 240 } 241 242 static void omap34xx_save_context(u32 *save) 243 { 244 u32 val; 245 246 /* Read Auxiliary Control Register */ 247 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); 248 *save++ = 1; 249 *save++ = val; 250 251 /* Read L2 AUX ctrl register */ 252 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); 253 *save++ = 1; 254 *save++ = val; 255 } 256 257 static int omap34xx_do_sram_idle(unsigned long save_state) 258 { 259 omap34xx_cpu_suspend(save_state); 260 return 0; 261 } 262 263 void omap_sram_idle(void) 264 { 265 /* Variable to tell what needs to be saved and restored 266 * in omap_sram_idle*/ 267 /* save_state = 0 => Nothing to save and restored */ 268 /* save_state = 1 => Only L1 and logic lost */ 269 /* save_state = 2 => Only L2 lost */ 270 /* save_state = 3 => L1, L2 and logic lost */ 271 int save_state = 0; 272 int mpu_next_state = PWRDM_POWER_ON; 273 int per_next_state = PWRDM_POWER_ON; 274 int core_next_state = PWRDM_POWER_ON; 275 int per_going_off; 276 int core_prev_state; 277 u32 sdrc_pwr = 0; 278 279 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 280 switch (mpu_next_state) { 281 case PWRDM_POWER_ON: 282 case PWRDM_POWER_RET: 283 /* No need to save context */ 284 save_state = 0; 285 break; 286 case PWRDM_POWER_OFF: 287 save_state = 3; 288 break; 289 default: 290 /* Invalid state */ 291 pr_err("Invalid mpu state in sram_idle\n"); 292 return; 293 } 294 295 /* NEON control */ 296 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 297 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 298 299 /* Enable IO-PAD and IO-CHAIN wakeups */ 300 per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 301 core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 302 if (omap3_has_io_wakeup() && 303 (per_next_state < PWRDM_POWER_ON || 304 core_next_state < PWRDM_POWER_ON)) { 305 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 306 if (omap3_has_io_chain_ctrl()) 307 omap3_enable_io_chain(); 308 } 309 310 pwrdm_pre_transition(); 311 312 /* PER */ 313 if (per_next_state < PWRDM_POWER_ON) { 314 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; 315 omap2_gpio_prepare_for_idle(per_going_off); 316 } 317 318 /* CORE */ 319 if (core_next_state < PWRDM_POWER_ON) { 320 if (core_next_state == PWRDM_POWER_OFF) { 321 omap3_core_save_context(); 322 omap3_cm_save_context(); 323 } 324 } 325 326 omap3_intc_prepare_idle(); 327 328 /* 329 * On EMU/HS devices ROM code restores a SRDC value 330 * from scratchpad which has automatic self refresh on timeout 331 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 332 * Hence store/restore the SDRC_POWER register here. 333 */ 334 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 335 (omap_type() == OMAP2_DEVICE_TYPE_EMU || 336 omap_type() == OMAP2_DEVICE_TYPE_SEC) && 337 core_next_state == PWRDM_POWER_OFF) 338 sdrc_pwr = sdrc_read_reg(SDRC_POWER); 339 340 /* 341 * omap3_arm_context is the location where some ARM context 342 * get saved. The rest is placed on the stack, and restored 343 * from there before resuming. 344 */ 345 if (save_state) 346 omap34xx_save_context(omap3_arm_context); 347 if (save_state == 1 || save_state == 3) 348 cpu_suspend(save_state, omap34xx_do_sram_idle); 349 else 350 omap34xx_do_sram_idle(save_state); 351 352 /* Restore normal SDRC POWER settings */ 353 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 354 (omap_type() == OMAP2_DEVICE_TYPE_EMU || 355 omap_type() == OMAP2_DEVICE_TYPE_SEC) && 356 core_next_state == PWRDM_POWER_OFF) 357 sdrc_write_reg(sdrc_pwr, SDRC_POWER); 358 359 /* CORE */ 360 if (core_next_state < PWRDM_POWER_ON) { 361 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 362 if (core_prev_state == PWRDM_POWER_OFF) { 363 omap3_core_restore_context(); 364 omap3_cm_restore_context(); 365 omap3_sram_restore_context(); 366 omap2_sms_restore_context(); 367 } 368 if (core_next_state == PWRDM_POWER_OFF) 369 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 370 OMAP3430_GR_MOD, 371 OMAP3_PRM_VOLTCTRL_OFFSET); 372 } 373 omap3_intc_resume_idle(); 374 375 pwrdm_post_transition(); 376 377 /* PER */ 378 if (per_next_state < PWRDM_POWER_ON) 379 omap2_gpio_resume_after_idle(); 380 381 /* Disable IO-PAD and IO-CHAIN wakeup */ 382 if (omap3_has_io_wakeup() && 383 (per_next_state < PWRDM_POWER_ON || 384 core_next_state < PWRDM_POWER_ON)) { 385 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, 386 PM_WKEN); 387 if (omap3_has_io_chain_ctrl()) 388 omap3_disable_io_chain(); 389 } 390 391 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 392 } 393 394 static void omap3_pm_idle(void) 395 { 396 local_fiq_disable(); 397 398 if (omap_irq_pending()) 399 goto out; 400 401 trace_power_start(POWER_CSTATE, 1, smp_processor_id()); 402 trace_cpu_idle(1, smp_processor_id()); 403 404 omap_sram_idle(); 405 406 trace_power_end(smp_processor_id()); 407 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); 408 409 out: 410 local_fiq_enable(); 411 } 412 413 #ifdef CONFIG_SUSPEND 414 static int omap3_pm_suspend(void) 415 { 416 struct power_state *pwrst; 417 int state, ret = 0; 418 419 /* Read current next_pwrsts */ 420 list_for_each_entry(pwrst, &pwrst_list, node) 421 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 422 /* Set ones wanted by suspend */ 423 list_for_each_entry(pwrst, &pwrst_list, node) { 424 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 425 goto restore; 426 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 427 goto restore; 428 } 429 430 omap3_intc_suspend(); 431 432 omap_sram_idle(); 433 434 restore: 435 /* Restore next_pwrsts */ 436 list_for_each_entry(pwrst, &pwrst_list, node) { 437 state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 438 if (state > pwrst->next_state) { 439 pr_info("Powerdomain (%s) didn't enter " 440 "target state %d\n", 441 pwrst->pwrdm->name, pwrst->next_state); 442 ret = -1; 443 } 444 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 445 } 446 if (ret) 447 pr_err("Could not enter target state in pm_suspend\n"); 448 else 449 pr_info("Successfully put all powerdomains to target state\n"); 450 451 return ret; 452 } 453 454 #endif /* CONFIG_SUSPEND */ 455 456 457 /** 458 * omap3_iva_idle(): ensure IVA is in idle so it can be put into 459 * retention 460 * 461 * In cases where IVA2 is activated by bootcode, it may prevent 462 * full-chip retention or off-mode because it is not idle. This 463 * function forces the IVA2 into idle state so it can go 464 * into retention/off and thus allow full-chip retention/off. 465 * 466 **/ 467 static void __init omap3_iva_idle(void) 468 { 469 /* ensure IVA2 clock is disabled */ 470 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 471 472 /* if no clock activity, nothing else to do */ 473 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 474 OMAP3430_CLKACTIVITY_IVA2_MASK)) 475 return; 476 477 /* Reset IVA2 */ 478 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 479 OMAP3430_RST2_IVA2_MASK | 480 OMAP3430_RST3_IVA2_MASK, 481 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 482 483 /* Enable IVA2 clock */ 484 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 485 OMAP3430_IVA2_MOD, CM_FCLKEN); 486 487 /* Set IVA2 boot mode to 'idle' */ 488 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 489 OMAP343X_CONTROL_IVA2_BOOTMOD); 490 491 /* Un-reset IVA2 */ 492 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 493 494 /* Disable IVA2 clock */ 495 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 496 497 /* Reset IVA2 */ 498 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 499 OMAP3430_RST2_IVA2_MASK | 500 OMAP3430_RST3_IVA2_MASK, 501 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 502 } 503 504 static void __init omap3_d2d_idle(void) 505 { 506 u16 mask, padconf; 507 508 /* In a stand alone OMAP3430 where there is not a stacked 509 * modem for the D2D Idle Ack and D2D MStandby must be pulled 510 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 511 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 512 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 513 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 514 padconf |= mask; 515 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 516 517 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 518 padconf |= mask; 519 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 520 521 /* reset modem */ 522 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 523 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 524 CORE_MOD, OMAP2_RM_RSTCTRL); 525 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 526 } 527 528 static void __init prcm_setup_regs(void) 529 { 530 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 531 OMAP3630_EN_UART4_MASK : 0; 532 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 533 OMAP3630_GRPSEL_UART4_MASK : 0; 534 535 /* XXX This should be handled by hwmod code or SCM init code */ 536 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 537 538 /* 539 * Enable control of expternal oscillator through 540 * sys_clkreq. In the long run clock framework should 541 * take care of this. 542 */ 543 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 544 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 545 OMAP3430_GR_MOD, 546 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 547 548 /* setup wakup source */ 549 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 550 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 551 WKUP_MOD, PM_WKEN); 552 /* No need to write EN_IO, that is always enabled */ 553 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 554 OMAP3430_GRPSEL_GPT1_MASK | 555 OMAP3430_GRPSEL_GPT12_MASK, 556 WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 557 558 /* Enable PM_WKEN to support DSS LPR */ 559 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 560 OMAP3430_DSS_MOD, PM_WKEN); 561 562 /* Enable wakeups in PER */ 563 omap2_prm_write_mod_reg(omap3630_en_uart4_mask | 564 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 565 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 566 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 567 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | 568 OMAP3430_EN_MCBSP4_MASK, 569 OMAP3430_PER_MOD, PM_WKEN); 570 /* and allow them to wake up MPU */ 571 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | 572 OMAP3430_GRPSEL_GPIO2_MASK | 573 OMAP3430_GRPSEL_GPIO3_MASK | 574 OMAP3430_GRPSEL_GPIO4_MASK | 575 OMAP3430_GRPSEL_GPIO5_MASK | 576 OMAP3430_GRPSEL_GPIO6_MASK | 577 OMAP3430_GRPSEL_UART3_MASK | 578 OMAP3430_GRPSEL_MCBSP2_MASK | 579 OMAP3430_GRPSEL_MCBSP3_MASK | 580 OMAP3430_GRPSEL_MCBSP4_MASK, 581 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 582 583 /* Don't attach IVA interrupts */ 584 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 585 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 586 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 587 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 588 589 /* Clear any pending 'reset' flags */ 590 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 591 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 592 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 593 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 594 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 595 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 596 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 597 598 /* Clear any pending PRCM interrupts */ 599 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 600 601 omap3_iva_idle(); 602 omap3_d2d_idle(); 603 } 604 605 void omap3_pm_off_mode_enable(int enable) 606 { 607 struct power_state *pwrst; 608 u32 state; 609 610 if (enable) 611 state = PWRDM_POWER_OFF; 612 else 613 state = PWRDM_POWER_RET; 614 615 list_for_each_entry(pwrst, &pwrst_list, node) { 616 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 617 pwrst->pwrdm == core_pwrdm && 618 state == PWRDM_POWER_OFF) { 619 pwrst->next_state = PWRDM_POWER_RET; 620 pr_warn("%s: Core OFF disabled due to errata i583\n", 621 __func__); 622 } else { 623 pwrst->next_state = state; 624 } 625 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 626 } 627 } 628 629 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 630 { 631 struct power_state *pwrst; 632 633 list_for_each_entry(pwrst, &pwrst_list, node) { 634 if (pwrst->pwrdm == pwrdm) 635 return pwrst->next_state; 636 } 637 return -EINVAL; 638 } 639 640 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 641 { 642 struct power_state *pwrst; 643 644 list_for_each_entry(pwrst, &pwrst_list, node) { 645 if (pwrst->pwrdm == pwrdm) { 646 pwrst->next_state = state; 647 return 0; 648 } 649 } 650 return -EINVAL; 651 } 652 653 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 654 { 655 struct power_state *pwrst; 656 657 if (!pwrdm->pwrsts) 658 return 0; 659 660 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 661 if (!pwrst) 662 return -ENOMEM; 663 pwrst->pwrdm = pwrdm; 664 pwrst->next_state = PWRDM_POWER_RET; 665 list_add(&pwrst->node, &pwrst_list); 666 667 if (pwrdm_has_hdwr_sar(pwrdm)) 668 pwrdm_enable_hdwr_sar(pwrdm); 669 670 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 671 } 672 673 /* 674 * Push functions to SRAM 675 * 676 * The minimum set of functions is pushed to SRAM for execution: 677 * - omap3_do_wfi for erratum i581 WA, 678 * - save_secure_ram_context for security extensions. 679 */ 680 void omap_push_sram_idle(void) 681 { 682 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); 683 684 if (omap_type() != OMAP2_DEVICE_TYPE_GP) 685 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 686 save_secure_ram_context_sz); 687 } 688 689 static void __init pm_errata_configure(void) 690 { 691 if (cpu_is_omap3630()) { 692 pm34xx_errata |= PM_RTA_ERRATUM_i608; 693 /* Enable the l2 cache toggling in sleep logic */ 694 enable_omap3630_toggle_l2_on_restore(); 695 if (omap_rev() < OMAP3630_REV_ES1_2) 696 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; 697 } 698 } 699 700 static int __init omap3_pm_init(void) 701 { 702 struct power_state *pwrst, *tmp; 703 struct clockdomain *neon_clkdm, *mpu_clkdm; 704 int ret; 705 706 if (!cpu_is_omap34xx()) 707 return -ENODEV; 708 709 if (!omap3_has_io_chain_ctrl()) 710 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n"); 711 712 pm_errata_configure(); 713 714 /* XXX prcm_setup_regs needs to be before enabling hw 715 * supervised mode for powerdomains */ 716 prcm_setup_regs(); 717 718 ret = request_irq(omap_prcm_event_to_irq("wkup"), 719 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); 720 721 if (ret) { 722 pr_err("pm: Failed to request pm_wkup irq\n"); 723 goto err1; 724 } 725 726 /* IO interrupt is shared with mux code */ 727 ret = request_irq(omap_prcm_event_to_irq("io"), 728 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", 729 omap3_pm_init); 730 731 if (ret) { 732 pr_err("pm: Failed to request pm_io irq\n"); 733 goto err2; 734 } 735 736 ret = pwrdm_for_each(pwrdms_setup, NULL); 737 if (ret) { 738 pr_err("Failed to setup powerdomains\n"); 739 goto err3; 740 } 741 742 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); 743 744 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 745 if (mpu_pwrdm == NULL) { 746 pr_err("Failed to get mpu_pwrdm\n"); 747 ret = -EINVAL; 748 goto err3; 749 } 750 751 neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 752 per_pwrdm = pwrdm_lookup("per_pwrdm"); 753 core_pwrdm = pwrdm_lookup("core_pwrdm"); 754 cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 755 756 neon_clkdm = clkdm_lookup("neon_clkdm"); 757 mpu_clkdm = clkdm_lookup("mpu_clkdm"); 758 759 #ifdef CONFIG_SUSPEND 760 omap_pm_suspend = omap3_pm_suspend; 761 #endif 762 763 arm_pm_idle = omap3_pm_idle; 764 omap3_idle_init(); 765 766 /* 767 * RTA is disabled during initialization as per erratum i608 768 * it is safer to disable RTA by the bootloader, but we would like 769 * to be doubly sure here and prevent any mishaps. 770 */ 771 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 772 omap3630_ctrl_disable_rta(); 773 774 clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 775 if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 776 omap3_secure_ram_storage = 777 kmalloc(0x803F, GFP_KERNEL); 778 if (!omap3_secure_ram_storage) 779 pr_err("Memory allocation failed when " 780 "allocating for secure sram context\n"); 781 782 local_irq_disable(); 783 local_fiq_disable(); 784 785 omap_dma_global_context_save(); 786 omap3_save_secure_ram_context(); 787 omap_dma_global_context_restore(); 788 789 local_irq_enable(); 790 local_fiq_enable(); 791 } 792 793 omap3_save_scratchpad_contents(); 794 return ret; 795 796 err3: 797 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 798 list_del(&pwrst->node); 799 kfree(pwrst); 800 } 801 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init); 802 err2: 803 free_irq(omap_prcm_event_to_irq("wkup"), NULL); 804 err1: 805 return ret; 806 } 807 808 late_initcall(omap3_pm_init); 809