1 /* 2 * opp2420_data.c - old-style "OPP" table for OMAP2420 3 * 4 * Copyright (C) 2005-2009 Texas Instruments, Inc. 5 * Copyright (C) 2004-2009 Nokia Corporation 6 * 7 * Richard Woodruff <r-woodruff2@ti.com> 8 * 9 * The OMAP2 processor can be run at several discrete 'PRCM configurations'. 10 * These configurations are characterized by voltage and speed for clocks. 11 * The device is only validated for certain combinations. One way to express 12 * these combinations is via the 'ratios' which the clocks operate with 13 * respect to each other. These ratio sets are for a given voltage/DPLL 14 * setting. All configurations can be described by a DPLL setting and a ratio. 15 * 16 * XXX Missing voltage data. 17 * XXX Missing 19.2MHz sys_clk rate sets (needed for N800/N810) 18 * 19 * THe format described in this file is deprecated. Once a reasonable 20 * OPP API exists, the data in this file should be converted to use it. 21 * 22 * This is technically part of the OMAP2xxx clock code. 23 * 24 * Considerable work is still needed to fully support dynamic frequency 25 * changes on OMAP2xxx-series chips. Readers interested in such a 26 * project are encouraged to review the Maemo Diablo RX-34 and RX-44 27 * kernel source at: 28 * http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/ 29 */ 30 31 #include "opp2xxx.h" 32 #include "sdrc.h" 33 #include "clock.h" 34 35 /* 36 * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated. 37 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, 38 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, 39 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM 40 * 41 * Filling in table based on H4 boards available. There are quite a 42 * few more rate combinations which could be defined. 43 * 44 * When multiple values are defined the start up will try and choose 45 * the fastest one. If a 'fast' value is defined, then automatically, 46 * the /2 one should be included as it can be used. Generally having 47 * more than one fast set does not make sense, as static timings need 48 * to be changed to change the set. The exception is the bypass 49 * setting which is available for low power bypass. 50 * 51 * Note: This table needs to be sorted, fastest to slowest. 52 **/ 53 const struct prcm_config omap2420_rate_table[] = { 54 /* PRCM I - FAST */ 55 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ 56 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL, 57 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL, 58 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz, 59 RATE_IN_242X}, 60 61 /* PRCM II - FAST */ 62 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ 63 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, 64 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, 65 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, 66 RATE_IN_242X}, 67 68 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ 69 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, 70 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, 71 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, 72 RATE_IN_242X}, 73 74 /* PRCM III - FAST */ 75 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ 76 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, 77 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, 78 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, 79 RATE_IN_242X}, 80 81 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ 82 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, 83 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, 84 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, 85 RATE_IN_242X}, 86 87 /* PRCM II - SLOW */ 88 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ 89 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, 90 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, 91 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, 92 RATE_IN_242X}, 93 94 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ 95 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, 96 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, 97 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, 98 RATE_IN_242X}, 99 100 /* PRCM III - SLOW */ 101 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ 102 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, 103 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, 104 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, 105 RATE_IN_242X}, 106 107 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ 108 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, 109 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, 110 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, 111 RATE_IN_242X}, 112 113 /* PRCM-VII (boot-bypass) */ 114 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ 115 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, 116 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, 117 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, 118 RATE_IN_242X}, 119 120 /* PRCM-VII (boot-bypass) */ 121 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ 122 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, 123 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, 124 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, 125 RATE_IN_242X}, 126 127 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 128 }; 129