1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 4 * 5 * Copyright (C) 2009-2011 Nokia Corporation 6 * Copyright (C) 2012 Texas Instruments, Inc. 7 * Paul Walmsley 8 * 9 * The data in this file should be completely autogeneratable from 10 * the TI hardware database or other technical documentation. 11 * 12 * XXX these should be marked initdata for multi-OMAP kernels 13 */ 14 15 #include <linux/platform_data/i2c-omap.h> 16 #include <linux/power/smartreflex.h> 17 #include <linux/platform_data/hsmmc-omap.h> 18 19 #include "l3_3xxx.h" 20 #include "l4_3xxx.h" 21 22 #include "soc.h" 23 #include "omap_hwmod.h" 24 #include "omap_hwmod_common_data.h" 25 #include "prm-regbits-34xx.h" 26 #include "cm-regbits-34xx.h" 27 28 #include "i2c.h" 29 #include "wd_timer.h" 30 #include "serial.h" 31 32 /* 33 * OMAP3xxx hardware module integration data 34 * 35 * All of the data in this section should be autogeneratable from the 36 * TI hardware database or other technical documentation. Data that 37 * is driver-specific or driver-kernel integration-specific belongs 38 * elsewhere. 39 */ 40 41 #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 42 43 /* 44 * IP blocks 45 */ 46 47 /* L3 */ 48 49 static struct omap_hwmod omap3xxx_l3_main_hwmod = { 50 .name = "l3_main", 51 .class = &l3_hwmod_class, 52 .flags = HWMOD_NO_IDLEST, 53 }; 54 55 /* L4 CORE */ 56 static struct omap_hwmod omap3xxx_l4_core_hwmod = { 57 .name = "l4_core", 58 .class = &l4_hwmod_class, 59 .flags = HWMOD_NO_IDLEST, 60 }; 61 62 /* L4 PER */ 63 static struct omap_hwmod omap3xxx_l4_per_hwmod = { 64 .name = "l4_per", 65 .class = &l4_hwmod_class, 66 .flags = HWMOD_NO_IDLEST, 67 }; 68 69 /* L4 WKUP */ 70 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 71 .name = "l4_wkup", 72 .class = &l4_hwmod_class, 73 .flags = HWMOD_NO_IDLEST, 74 }; 75 76 /* L4 SEC */ 77 static struct omap_hwmod omap3xxx_l4_sec_hwmod = { 78 .name = "l4_sec", 79 .class = &l4_hwmod_class, 80 .flags = HWMOD_NO_IDLEST, 81 }; 82 83 /* MPU */ 84 85 static struct omap_hwmod omap3xxx_mpu_hwmod = { 86 .name = "mpu", 87 .class = &mpu_hwmod_class, 88 .main_clk = "arm_fck", 89 }; 90 91 /* IVA2 (IVA2) */ 92 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { 93 { .name = "logic", .rst_shift = 0, .st_shift = 8 }, 94 { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, 95 { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, 96 }; 97 98 static struct omap_hwmod omap3xxx_iva_hwmod = { 99 .name = "iva", 100 .class = &iva_hwmod_class, 101 .clkdm_name = "iva2_clkdm", 102 .rst_lines = omap3xxx_iva_resets, 103 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), 104 .main_clk = "iva2_ck", 105 .prcm = { 106 .omap2 = { 107 .module_offs = OMAP3430_IVA2_MOD, 108 .idlest_reg_id = 1, 109 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, 110 }, 111 }, 112 }; 113 114 /* 115 * 'debugss' class 116 * debug and emulation sub system 117 */ 118 119 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = { 120 .name = "debugss", 121 }; 122 123 /* debugss */ 124 static struct omap_hwmod omap3xxx_debugss_hwmod = { 125 .name = "debugss", 126 .class = &omap3xxx_debugss_hwmod_class, 127 .clkdm_name = "emu_clkdm", 128 .main_clk = "emu_src_ck", 129 .flags = HWMOD_NO_IDLEST, 130 }; 131 132 /* timer class */ 133 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { 134 .rev_offs = 0x0000, 135 .sysc_offs = 0x0010, 136 .syss_offs = 0x0014, 137 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 138 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 139 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | 140 SYSS_HAS_RESET_STATUS), 141 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 142 .sysc_fields = &omap_hwmod_sysc_type1, 143 }; 144 145 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { 146 .name = "timer", 147 .sysc = &omap3xxx_timer_sysc, 148 }; 149 150 /* timer3 */ 151 static struct omap_hwmod omap3xxx_timer3_hwmod = { 152 .name = "timer3", 153 .main_clk = "gpt3_fck", 154 .prcm = { 155 .omap2 = { 156 .module_offs = OMAP3430_PER_MOD, 157 .idlest_reg_id = 1, 158 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, 159 }, 160 }, 161 .class = &omap3xxx_timer_hwmod_class, 162 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 163 }; 164 165 /* timer4 */ 166 static struct omap_hwmod omap3xxx_timer4_hwmod = { 167 .name = "timer4", 168 .main_clk = "gpt4_fck", 169 .prcm = { 170 .omap2 = { 171 .module_offs = OMAP3430_PER_MOD, 172 .idlest_reg_id = 1, 173 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, 174 }, 175 }, 176 .class = &omap3xxx_timer_hwmod_class, 177 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 178 }; 179 180 /* timer5 */ 181 static struct omap_hwmod omap3xxx_timer5_hwmod = { 182 .name = "timer5", 183 .main_clk = "gpt5_fck", 184 .prcm = { 185 .omap2 = { 186 .module_offs = OMAP3430_PER_MOD, 187 .idlest_reg_id = 1, 188 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, 189 }, 190 }, 191 .class = &omap3xxx_timer_hwmod_class, 192 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 193 }; 194 195 /* timer6 */ 196 static struct omap_hwmod omap3xxx_timer6_hwmod = { 197 .name = "timer6", 198 .main_clk = "gpt6_fck", 199 .prcm = { 200 .omap2 = { 201 .module_offs = OMAP3430_PER_MOD, 202 .idlest_reg_id = 1, 203 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, 204 }, 205 }, 206 .class = &omap3xxx_timer_hwmod_class, 207 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 208 }; 209 210 /* timer7 */ 211 static struct omap_hwmod omap3xxx_timer7_hwmod = { 212 .name = "timer7", 213 .main_clk = "gpt7_fck", 214 .prcm = { 215 .omap2 = { 216 .module_offs = OMAP3430_PER_MOD, 217 .idlest_reg_id = 1, 218 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, 219 }, 220 }, 221 .class = &omap3xxx_timer_hwmod_class, 222 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 223 }; 224 225 /* timer8 */ 226 static struct omap_hwmod omap3xxx_timer8_hwmod = { 227 .name = "timer8", 228 .main_clk = "gpt8_fck", 229 .prcm = { 230 .omap2 = { 231 .module_offs = OMAP3430_PER_MOD, 232 .idlest_reg_id = 1, 233 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, 234 }, 235 }, 236 .class = &omap3xxx_timer_hwmod_class, 237 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 238 }; 239 240 /* timer9 */ 241 static struct omap_hwmod omap3xxx_timer9_hwmod = { 242 .name = "timer9", 243 .main_clk = "gpt9_fck", 244 .prcm = { 245 .omap2 = { 246 .module_offs = OMAP3430_PER_MOD, 247 .idlest_reg_id = 1, 248 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, 249 }, 250 }, 251 .class = &omap3xxx_timer_hwmod_class, 252 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 253 }; 254 255 /* timer10 */ 256 static struct omap_hwmod omap3xxx_timer10_hwmod = { 257 .name = "timer10", 258 .main_clk = "gpt10_fck", 259 .prcm = { 260 .omap2 = { 261 .module_offs = CORE_MOD, 262 .idlest_reg_id = 1, 263 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, 264 }, 265 }, 266 .class = &omap3xxx_timer_hwmod_class, 267 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 268 }; 269 270 /* timer11 */ 271 static struct omap_hwmod omap3xxx_timer11_hwmod = { 272 .name = "timer11", 273 .main_clk = "gpt11_fck", 274 .prcm = { 275 .omap2 = { 276 .module_offs = CORE_MOD, 277 .idlest_reg_id = 1, 278 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, 279 }, 280 }, 281 .class = &omap3xxx_timer_hwmod_class, 282 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 283 }; 284 285 /* 286 * 'wd_timer' class 287 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 288 * overflow condition 289 */ 290 291 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { 292 .rev_offs = 0x0000, 293 .sysc_offs = 0x0010, 294 .syss_offs = 0x0014, 295 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | 296 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 297 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 298 SYSS_HAS_RESET_STATUS), 299 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 300 .sysc_fields = &omap_hwmod_sysc_type1, 301 }; 302 303 /* I2C common */ 304 static struct omap_hwmod_class_sysconfig i2c_sysc = { 305 .rev_offs = 0x00, 306 .sysc_offs = 0x20, 307 .syss_offs = 0x10, 308 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 309 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 310 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 311 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 312 .sysc_fields = &omap_hwmod_sysc_type1, 313 }; 314 315 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { 316 .name = "wd_timer", 317 .sysc = &omap3xxx_wd_timer_sysc, 318 .pre_shutdown = &omap2_wd_timer_disable, 319 .reset = &omap2_wd_timer_reset, 320 }; 321 322 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { 323 .name = "wd_timer2", 324 .class = &omap3xxx_wd_timer_hwmod_class, 325 .main_clk = "wdt2_fck", 326 .prcm = { 327 .omap2 = { 328 .module_offs = WKUP_MOD, 329 .idlest_reg_id = 1, 330 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, 331 }, 332 }, 333 /* 334 * XXX: Use software supervised mode, HW supervised smartidle seems to 335 * block CORE power domain idle transitions. Maybe a HW bug in wdt2? 336 */ 337 .flags = HWMOD_SWSUP_SIDLE, 338 }; 339 340 /* UART1 */ 341 static struct omap_hwmod omap3xxx_uart1_hwmod = { 342 .name = "uart1", 343 .main_clk = "uart1_fck", 344 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE, 345 .prcm = { 346 .omap2 = { 347 .module_offs = CORE_MOD, 348 .idlest_reg_id = 1, 349 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, 350 }, 351 }, 352 .class = &omap2_uart_class, 353 }; 354 355 /* UART2 */ 356 static struct omap_hwmod omap3xxx_uart2_hwmod = { 357 .name = "uart2", 358 .main_clk = "uart2_fck", 359 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE, 360 .prcm = { 361 .omap2 = { 362 .module_offs = CORE_MOD, 363 .idlest_reg_id = 1, 364 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, 365 }, 366 }, 367 .class = &omap2_uart_class, 368 }; 369 370 /* UART3 */ 371 static struct omap_hwmod omap3xxx_uart3_hwmod = { 372 .name = "uart3", 373 .main_clk = "uart3_fck", 374 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS | 375 HWMOD_SWSUP_SIDLE, 376 .prcm = { 377 .omap2 = { 378 .module_offs = OMAP3430_PER_MOD, 379 .idlest_reg_id = 1, 380 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, 381 }, 382 }, 383 .class = &omap2_uart_class, 384 }; 385 386 /* UART4 */ 387 388 389 static struct omap_hwmod omap36xx_uart4_hwmod = { 390 .name = "uart4", 391 .main_clk = "uart4_fck", 392 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE, 393 .prcm = { 394 .omap2 = { 395 .module_offs = OMAP3430_PER_MOD, 396 .idlest_reg_id = 1, 397 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, 398 }, 399 }, 400 .class = &omap2_uart_class, 401 }; 402 403 404 405 /* 406 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or 407 * uart2_fck being enabled. So we add uart1_fck as an optional clock, 408 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really 409 * should not be needed. The functional clock structure of the AM35xx 410 * UART4 is extremely unclear and opaque; it is unclear what the role 411 * of uart1/2_fck is for the UART4. Any clarification from either 412 * empirical testing or the AM3505/3517 hardware designers would be 413 * most welcome. 414 */ 415 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { 416 { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, 417 }; 418 419 static struct omap_hwmod am35xx_uart4_hwmod = { 420 .name = "uart4", 421 .main_clk = "uart4_fck", 422 .prcm = { 423 .omap2 = { 424 .module_offs = CORE_MOD, 425 .idlest_reg_id = 1, 426 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, 427 }, 428 }, 429 .opt_clks = am35xx_uart4_opt_clks, 430 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), 431 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 432 .class = &omap2_uart_class, 433 }; 434 435 static struct omap_hwmod_class i2c_class = { 436 .name = "i2c", 437 .sysc = &i2c_sysc, 438 .reset = &omap_i2c_reset, 439 }; 440 441 /* dss */ 442 static struct omap_hwmod_opt_clk dss_opt_clks[] = { 443 /* 444 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 445 * driver does not use these clocks. 446 */ 447 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 448 { .role = "tv_clk", .clk = "dss_tv_fck" }, 449 /* required only on OMAP3430 */ 450 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 451 }; 452 453 static struct omap_hwmod omap3430es1_dss_core_hwmod = { 454 .name = "dss_core", 455 .class = &omap2_dss_hwmod_class, 456 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 457 .prcm = { 458 .omap2 = { 459 .module_offs = OMAP3430_DSS_MOD, 460 .idlest_reg_id = 1, 461 }, 462 }, 463 .opt_clks = dss_opt_clks, 464 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 465 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, 466 }; 467 468 static struct omap_hwmod omap3xxx_dss_core_hwmod = { 469 .name = "dss_core", 470 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 471 .class = &omap2_dss_hwmod_class, 472 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 473 .prcm = { 474 .omap2 = { 475 .module_offs = OMAP3430_DSS_MOD, 476 .idlest_reg_id = 1, 477 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, 478 }, 479 }, 480 .opt_clks = dss_opt_clks, 481 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 482 }; 483 484 /* 485 * 'dispc' class 486 * display controller 487 */ 488 489 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { 490 .rev_offs = 0x0000, 491 .sysc_offs = 0x0010, 492 .syss_offs = 0x0014, 493 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 494 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 495 SYSC_HAS_ENAWAKEUP), 496 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 497 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 498 .sysc_fields = &omap_hwmod_sysc_type1, 499 }; 500 501 static struct omap_hwmod_class omap3_dispc_hwmod_class = { 502 .name = "dispc", 503 .sysc = &omap3_dispc_sysc, 504 }; 505 506 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 507 .name = "dss_dispc", 508 .class = &omap3_dispc_hwmod_class, 509 .main_clk = "dss1_alwon_fck", 510 .prcm = { 511 .omap2 = { 512 .module_offs = OMAP3430_DSS_MOD, 513 }, 514 }, 515 .flags = HWMOD_NO_IDLEST, 516 .dev_attr = &omap2_3_dss_dispc_dev_attr, 517 }; 518 519 /* 520 * 'dsi' class 521 * display serial interface controller 522 */ 523 524 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = { 525 .rev_offs = 0x0000, 526 .sysc_offs = 0x0010, 527 .syss_offs = 0x0014, 528 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 529 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 530 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 531 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 532 .sysc_fields = &omap_hwmod_sysc_type1, 533 }; 534 535 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { 536 .name = "dsi", 537 .sysc = &omap3xxx_dsi_sysc, 538 }; 539 540 /* dss_dsi1 */ 541 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 542 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 543 }; 544 545 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { 546 .name = "dss_dsi1", 547 .class = &omap3xxx_dsi_hwmod_class, 548 .main_clk = "dss1_alwon_fck", 549 .prcm = { 550 .omap2 = { 551 .module_offs = OMAP3430_DSS_MOD, 552 }, 553 }, 554 .opt_clks = dss_dsi1_opt_clks, 555 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 556 .flags = HWMOD_NO_IDLEST, 557 }; 558 559 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 560 { .role = "ick", .clk = "dss_ick" }, 561 }; 562 563 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { 564 .name = "dss_rfbi", 565 .class = &omap2_rfbi_hwmod_class, 566 .main_clk = "dss1_alwon_fck", 567 .prcm = { 568 .omap2 = { 569 .module_offs = OMAP3430_DSS_MOD, 570 }, 571 }, 572 .opt_clks = dss_rfbi_opt_clks, 573 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 574 .flags = HWMOD_NO_IDLEST, 575 }; 576 577 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { 578 /* required only on OMAP3430 */ 579 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 580 }; 581 582 static struct omap_hwmod omap3xxx_dss_venc_hwmod = { 583 .name = "dss_venc", 584 .class = &omap2_venc_hwmod_class, 585 .main_clk = "dss_tv_fck", 586 .prcm = { 587 .omap2 = { 588 .module_offs = OMAP3430_DSS_MOD, 589 }, 590 }, 591 .opt_clks = dss_venc_opt_clks, 592 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), 593 .flags = HWMOD_NO_IDLEST, 594 }; 595 596 /* I2C1 */ 597 static struct omap_hwmod omap3xxx_i2c1_hwmod = { 598 .name = "i2c1", 599 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 600 .main_clk = "i2c1_fck", 601 .prcm = { 602 .omap2 = { 603 .module_offs = CORE_MOD, 604 .idlest_reg_id = 1, 605 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, 606 }, 607 }, 608 .class = &i2c_class, 609 }; 610 611 /* I2C2 */ 612 static struct omap_hwmod omap3xxx_i2c2_hwmod = { 613 .name = "i2c2", 614 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 615 .main_clk = "i2c2_fck", 616 .prcm = { 617 .omap2 = { 618 .module_offs = CORE_MOD, 619 .idlest_reg_id = 1, 620 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, 621 }, 622 }, 623 .class = &i2c_class, 624 }; 625 626 /* I2C3 */ 627 static struct omap_hwmod omap3xxx_i2c3_hwmod = { 628 .name = "i2c3", 629 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 630 .main_clk = "i2c3_fck", 631 .prcm = { 632 .omap2 = { 633 .module_offs = CORE_MOD, 634 .idlest_reg_id = 1, 635 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, 636 }, 637 }, 638 .class = &i2c_class, 639 }; 640 641 /* 642 * 'gpio' class 643 * general purpose io module 644 */ 645 646 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { 647 .rev_offs = 0x0000, 648 .sysc_offs = 0x0010, 649 .syss_offs = 0x0014, 650 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 651 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 652 SYSS_HAS_RESET_STATUS), 653 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 654 .sysc_fields = &omap_hwmod_sysc_type1, 655 }; 656 657 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { 658 .name = "gpio", 659 .sysc = &omap3xxx_gpio_sysc, 660 }; 661 662 /* gpio1 */ 663 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 664 { .role = "dbclk", .clk = "gpio1_dbck", }, 665 }; 666 667 static struct omap_hwmod omap3xxx_gpio1_hwmod = { 668 .name = "gpio1", 669 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 670 .main_clk = "gpio1_ick", 671 .opt_clks = gpio1_opt_clks, 672 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 673 .prcm = { 674 .omap2 = { 675 .module_offs = WKUP_MOD, 676 .idlest_reg_id = 1, 677 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, 678 }, 679 }, 680 .class = &omap3xxx_gpio_hwmod_class, 681 }; 682 683 /* gpio2 */ 684 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 685 { .role = "dbclk", .clk = "gpio2_dbck", }, 686 }; 687 688 static struct omap_hwmod omap3xxx_gpio2_hwmod = { 689 .name = "gpio2", 690 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 691 .main_clk = "gpio2_ick", 692 .opt_clks = gpio2_opt_clks, 693 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 694 .prcm = { 695 .omap2 = { 696 .module_offs = OMAP3430_PER_MOD, 697 .idlest_reg_id = 1, 698 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, 699 }, 700 }, 701 .class = &omap3xxx_gpio_hwmod_class, 702 }; 703 704 /* gpio3 */ 705 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 706 { .role = "dbclk", .clk = "gpio3_dbck", }, 707 }; 708 709 static struct omap_hwmod omap3xxx_gpio3_hwmod = { 710 .name = "gpio3", 711 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 712 .main_clk = "gpio3_ick", 713 .opt_clks = gpio3_opt_clks, 714 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 715 .prcm = { 716 .omap2 = { 717 .module_offs = OMAP3430_PER_MOD, 718 .idlest_reg_id = 1, 719 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, 720 }, 721 }, 722 .class = &omap3xxx_gpio_hwmod_class, 723 }; 724 725 /* gpio4 */ 726 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 727 { .role = "dbclk", .clk = "gpio4_dbck", }, 728 }; 729 730 static struct omap_hwmod omap3xxx_gpio4_hwmod = { 731 .name = "gpio4", 732 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 733 .main_clk = "gpio4_ick", 734 .opt_clks = gpio4_opt_clks, 735 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 736 .prcm = { 737 .omap2 = { 738 .module_offs = OMAP3430_PER_MOD, 739 .idlest_reg_id = 1, 740 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, 741 }, 742 }, 743 .class = &omap3xxx_gpio_hwmod_class, 744 }; 745 746 /* gpio5 */ 747 748 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 749 { .role = "dbclk", .clk = "gpio5_dbck", }, 750 }; 751 752 static struct omap_hwmod omap3xxx_gpio5_hwmod = { 753 .name = "gpio5", 754 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 755 .main_clk = "gpio5_ick", 756 .opt_clks = gpio5_opt_clks, 757 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 758 .prcm = { 759 .omap2 = { 760 .module_offs = OMAP3430_PER_MOD, 761 .idlest_reg_id = 1, 762 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, 763 }, 764 }, 765 .class = &omap3xxx_gpio_hwmod_class, 766 }; 767 768 /* gpio6 */ 769 770 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 771 { .role = "dbclk", .clk = "gpio6_dbck", }, 772 }; 773 774 static struct omap_hwmod omap3xxx_gpio6_hwmod = { 775 .name = "gpio6", 776 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 777 .main_clk = "gpio6_ick", 778 .opt_clks = gpio6_opt_clks, 779 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 780 .prcm = { 781 .omap2 = { 782 .module_offs = OMAP3430_PER_MOD, 783 .idlest_reg_id = 1, 784 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, 785 }, 786 }, 787 .class = &omap3xxx_gpio_hwmod_class, 788 }; 789 790 /* 791 * 'mcbsp' class 792 * multi channel buffered serial port controller 793 */ 794 795 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { 796 .rev_offs = -ENODEV, 797 .sysc_offs = 0x008c, 798 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | 799 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 800 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 801 .sysc_fields = &omap_hwmod_sysc_type1, 802 }; 803 804 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { 805 .name = "mcbsp", 806 .sysc = &omap3xxx_mcbsp_sysc, 807 }; 808 809 /* McBSP functional clock mapping */ 810 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { 811 { .role = "pad_fck", .clk = "mcbsp_clks" }, 812 { .role = "prcm_fck", .clk = "core_96m_fck" }, 813 }; 814 815 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { 816 { .role = "pad_fck", .clk = "mcbsp_clks" }, 817 { .role = "prcm_fck", .clk = "per_96m_fck" }, 818 }; 819 820 /* mcbsp1 */ 821 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { 822 .name = "mcbsp1", 823 .class = &omap3xxx_mcbsp_hwmod_class, 824 .main_clk = "mcbsp1_fck", 825 .prcm = { 826 .omap2 = { 827 .module_offs = CORE_MOD, 828 .idlest_reg_id = 1, 829 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, 830 }, 831 }, 832 .opt_clks = mcbsp15_opt_clks, 833 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), 834 }; 835 836 /* mcbsp2 */ 837 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { 838 .name = "mcbsp2", 839 .class = &omap3xxx_mcbsp_hwmod_class, 840 .main_clk = "mcbsp2_fck", 841 .prcm = { 842 .omap2 = { 843 .module_offs = OMAP3430_PER_MOD, 844 .idlest_reg_id = 1, 845 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 846 }, 847 }, 848 .opt_clks = mcbsp234_opt_clks, 849 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 850 }; 851 852 /* mcbsp3 */ 853 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { 854 .name = "mcbsp3", 855 .class = &omap3xxx_mcbsp_hwmod_class, 856 .main_clk = "mcbsp3_fck", 857 .prcm = { 858 .omap2 = { 859 .module_offs = OMAP3430_PER_MOD, 860 .idlest_reg_id = 1, 861 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 862 }, 863 }, 864 .opt_clks = mcbsp234_opt_clks, 865 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 866 }; 867 868 /* mcbsp4 */ 869 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { 870 .name = "mcbsp4", 871 .class = &omap3xxx_mcbsp_hwmod_class, 872 .main_clk = "mcbsp4_fck", 873 .prcm = { 874 .omap2 = { 875 .module_offs = OMAP3430_PER_MOD, 876 .idlest_reg_id = 1, 877 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, 878 }, 879 }, 880 .opt_clks = mcbsp234_opt_clks, 881 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 882 }; 883 884 /* mcbsp5 */ 885 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { 886 .name = "mcbsp5", 887 .class = &omap3xxx_mcbsp_hwmod_class, 888 .main_clk = "mcbsp5_fck", 889 .prcm = { 890 .omap2 = { 891 .module_offs = CORE_MOD, 892 .idlest_reg_id = 1, 893 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, 894 }, 895 }, 896 .opt_clks = mcbsp15_opt_clks, 897 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), 898 }; 899 900 /* 'mcbsp sidetone' class */ 901 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { 902 .rev_offs = -ENODEV, 903 .sysc_offs = 0x0010, 904 .sysc_flags = SYSC_HAS_AUTOIDLE, 905 .sysc_fields = &omap_hwmod_sysc_type1, 906 }; 907 908 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { 909 .name = "mcbsp_sidetone", 910 .sysc = &omap3xxx_mcbsp_sidetone_sysc, 911 }; 912 913 /* mcbsp2_sidetone */ 914 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { 915 .name = "mcbsp2_sidetone", 916 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 917 .main_clk = "mcbsp2_ick", 918 .flags = HWMOD_NO_IDLEST, 919 }; 920 921 /* mcbsp3_sidetone */ 922 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { 923 .name = "mcbsp3_sidetone", 924 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 925 .main_clk = "mcbsp3_ick", 926 .flags = HWMOD_NO_IDLEST, 927 }; 928 929 /* SR common */ 930 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { 931 .rev_offs = -ENODEV, 932 .sysc_offs = 0x24, 933 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), 934 .sysc_fields = &omap34xx_sr_sysc_fields, 935 }; 936 937 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { 938 .name = "smartreflex", 939 .sysc = &omap34xx_sr_sysc, 940 }; 941 942 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { 943 .rev_offs = -ENODEV, 944 .sysc_offs = 0x38, 945 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 946 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 947 SYSC_NO_CACHE), 948 .sysc_fields = &omap36xx_sr_sysc_fields, 949 }; 950 951 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { 952 .name = "smartreflex", 953 .sysc = &omap36xx_sr_sysc, 954 }; 955 956 /* SR1 */ 957 static struct omap_smartreflex_dev_attr sr1_dev_attr = { 958 .sensor_voltdm_name = "mpu_iva", 959 }; 960 961 962 static struct omap_hwmod omap34xx_sr1_hwmod = { 963 .name = "smartreflex_mpu_iva", 964 .class = &omap34xx_smartreflex_hwmod_class, 965 .main_clk = "sr1_fck", 966 .prcm = { 967 .omap2 = { 968 .module_offs = WKUP_MOD, 969 .idlest_reg_id = 1, 970 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 971 }, 972 }, 973 .dev_attr = &sr1_dev_attr, 974 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 975 }; 976 977 static struct omap_hwmod omap36xx_sr1_hwmod = { 978 .name = "smartreflex_mpu_iva", 979 .class = &omap36xx_smartreflex_hwmod_class, 980 .main_clk = "sr1_fck", 981 .prcm = { 982 .omap2 = { 983 .module_offs = WKUP_MOD, 984 .idlest_reg_id = 1, 985 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 986 }, 987 }, 988 .dev_attr = &sr1_dev_attr, 989 }; 990 991 /* SR2 */ 992 static struct omap_smartreflex_dev_attr sr2_dev_attr = { 993 .sensor_voltdm_name = "core", 994 }; 995 996 997 static struct omap_hwmod omap34xx_sr2_hwmod = { 998 .name = "smartreflex_core", 999 .class = &omap34xx_smartreflex_hwmod_class, 1000 .main_clk = "sr2_fck", 1001 .prcm = { 1002 .omap2 = { 1003 .module_offs = WKUP_MOD, 1004 .idlest_reg_id = 1, 1005 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1006 }, 1007 }, 1008 .dev_attr = &sr2_dev_attr, 1009 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1010 }; 1011 1012 static struct omap_hwmod omap36xx_sr2_hwmod = { 1013 .name = "smartreflex_core", 1014 .class = &omap36xx_smartreflex_hwmod_class, 1015 .main_clk = "sr2_fck", 1016 .prcm = { 1017 .omap2 = { 1018 .module_offs = WKUP_MOD, 1019 .idlest_reg_id = 1, 1020 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1021 }, 1022 }, 1023 .dev_attr = &sr2_dev_attr, 1024 }; 1025 1026 /* 1027 * 'mailbox' class 1028 * mailbox module allowing communication between the on-chip processors 1029 * using a queued mailbox-interrupt mechanism. 1030 */ 1031 1032 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { 1033 .rev_offs = 0x000, 1034 .sysc_offs = 0x010, 1035 .syss_offs = 0x014, 1036 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1037 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1038 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1039 .sysc_fields = &omap_hwmod_sysc_type1, 1040 }; 1041 1042 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { 1043 .name = "mailbox", 1044 .sysc = &omap3xxx_mailbox_sysc, 1045 }; 1046 1047 static struct omap_hwmod omap3xxx_mailbox_hwmod = { 1048 .name = "mailbox", 1049 .class = &omap3xxx_mailbox_hwmod_class, 1050 .main_clk = "mailboxes_ick", 1051 .prcm = { 1052 .omap2 = { 1053 .module_offs = CORE_MOD, 1054 .idlest_reg_id = 1, 1055 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, 1056 }, 1057 }, 1058 }; 1059 1060 /* 1061 * 'mcspi' class 1062 * multichannel serial port interface (mcspi) / master/slave synchronous serial 1063 * bus 1064 */ 1065 1066 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { 1067 .rev_offs = 0x0000, 1068 .sysc_offs = 0x0010, 1069 .syss_offs = 0x0014, 1070 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1071 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1072 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1073 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1074 .sysc_fields = &omap_hwmod_sysc_type1, 1075 }; 1076 1077 static struct omap_hwmod_class omap34xx_mcspi_class = { 1078 .name = "mcspi", 1079 .sysc = &omap34xx_mcspi_sysc, 1080 }; 1081 1082 /* mcspi1 */ 1083 static struct omap_hwmod omap34xx_mcspi1 = { 1084 .name = "mcspi1", 1085 .main_clk = "mcspi1_fck", 1086 .prcm = { 1087 .omap2 = { 1088 .module_offs = CORE_MOD, 1089 .idlest_reg_id = 1, 1090 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, 1091 }, 1092 }, 1093 .class = &omap34xx_mcspi_class, 1094 }; 1095 1096 /* mcspi2 */ 1097 static struct omap_hwmod omap34xx_mcspi2 = { 1098 .name = "mcspi2", 1099 .main_clk = "mcspi2_fck", 1100 .prcm = { 1101 .omap2 = { 1102 .module_offs = CORE_MOD, 1103 .idlest_reg_id = 1, 1104 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, 1105 }, 1106 }, 1107 .class = &omap34xx_mcspi_class, 1108 }; 1109 1110 /* mcspi3 */ 1111 static struct omap_hwmod omap34xx_mcspi3 = { 1112 .name = "mcspi3", 1113 .main_clk = "mcspi3_fck", 1114 .prcm = { 1115 .omap2 = { 1116 .module_offs = CORE_MOD, 1117 .idlest_reg_id = 1, 1118 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, 1119 }, 1120 }, 1121 .class = &omap34xx_mcspi_class, 1122 }; 1123 1124 /* mcspi4 */ 1125 static struct omap_hwmod omap34xx_mcspi4 = { 1126 .name = "mcspi4", 1127 .main_clk = "mcspi4_fck", 1128 .prcm = { 1129 .omap2 = { 1130 .module_offs = CORE_MOD, 1131 .idlest_reg_id = 1, 1132 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, 1133 }, 1134 }, 1135 .class = &omap34xx_mcspi_class, 1136 }; 1137 1138 /* MMC/SD/SDIO common */ 1139 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { 1140 .rev_offs = 0x1fc, 1141 .sysc_offs = 0x10, 1142 .syss_offs = 0x14, 1143 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1144 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1145 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1146 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1147 .sysc_fields = &omap_hwmod_sysc_type1, 1148 }; 1149 1150 static struct omap_hwmod_class omap34xx_mmc_class = { 1151 .name = "mmc", 1152 .sysc = &omap34xx_mmc_sysc, 1153 }; 1154 1155 /* MMC/SD/SDIO1 */ 1156 1157 1158 1159 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { 1160 { .role = "dbck", .clk = "omap_32k_fck", }, 1161 }; 1162 1163 static struct omap_hsmmc_dev_attr mmc1_dev_attr = { 1164 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1165 }; 1166 1167 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1168 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = { 1169 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | 1170 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), 1171 }; 1172 1173 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { 1174 .name = "mmc1", 1175 .opt_clks = omap34xx_mmc1_opt_clks, 1176 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1177 .main_clk = "mmchs1_fck", 1178 .prcm = { 1179 .omap2 = { 1180 .module_offs = CORE_MOD, 1181 .idlest_reg_id = 1, 1182 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 1183 }, 1184 }, 1185 .dev_attr = &mmc1_pre_es3_dev_attr, 1186 .class = &omap34xx_mmc_class, 1187 }; 1188 1189 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { 1190 .name = "mmc1", 1191 .opt_clks = omap34xx_mmc1_opt_clks, 1192 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1193 .main_clk = "mmchs1_fck", 1194 .prcm = { 1195 .omap2 = { 1196 .module_offs = CORE_MOD, 1197 .idlest_reg_id = 1, 1198 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 1199 }, 1200 }, 1201 .dev_attr = &mmc1_dev_attr, 1202 .class = &omap34xx_mmc_class, 1203 }; 1204 1205 /* MMC/SD/SDIO2 */ 1206 1207 1208 1209 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { 1210 { .role = "dbck", .clk = "omap_32k_fck", }, 1211 }; 1212 1213 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1214 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = { 1215 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1216 }; 1217 1218 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { 1219 .name = "mmc2", 1220 .opt_clks = omap34xx_mmc2_opt_clks, 1221 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1222 .main_clk = "mmchs2_fck", 1223 .prcm = { 1224 .omap2 = { 1225 .module_offs = CORE_MOD, 1226 .idlest_reg_id = 1, 1227 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1228 }, 1229 }, 1230 .dev_attr = &mmc2_pre_es3_dev_attr, 1231 .class = &omap34xx_mmc_class, 1232 }; 1233 1234 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { 1235 .name = "mmc2", 1236 .opt_clks = omap34xx_mmc2_opt_clks, 1237 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1238 .main_clk = "mmchs2_fck", 1239 .prcm = { 1240 .omap2 = { 1241 .module_offs = CORE_MOD, 1242 .idlest_reg_id = 1, 1243 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1244 }, 1245 }, 1246 .class = &omap34xx_mmc_class, 1247 }; 1248 1249 /* MMC/SD/SDIO3 */ 1250 1251 1252 1253 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { 1254 { .role = "dbck", .clk = "omap_32k_fck", }, 1255 }; 1256 1257 static struct omap_hwmod omap3xxx_mmc3_hwmod = { 1258 .name = "mmc3", 1259 .opt_clks = omap34xx_mmc3_opt_clks, 1260 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), 1261 .main_clk = "mmchs3_fck", 1262 .prcm = { 1263 .omap2 = { 1264 .module_offs = CORE_MOD, 1265 .idlest_reg_id = 1, 1266 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, 1267 }, 1268 }, 1269 .class = &omap34xx_mmc_class, 1270 }; 1271 1272 /* 1273 * 'usb_host_hs' class 1274 * high-speed multi-port usb host controller 1275 */ 1276 1277 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { 1278 .rev_offs = 0x0000, 1279 .sysc_offs = 0x0010, 1280 .syss_offs = 0x0014, 1281 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 1282 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 1283 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 1284 SYSS_HAS_RESET_STATUS), 1285 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1286 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1287 .sysc_fields = &omap_hwmod_sysc_type1, 1288 }; 1289 1290 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { 1291 .name = "usb_host_hs", 1292 .sysc = &omap3xxx_usb_host_hs_sysc, 1293 }; 1294 1295 1296 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { 1297 .name = "usb_host_hs", 1298 .class = &omap3xxx_usb_host_hs_hwmod_class, 1299 .clkdm_name = "usbhost_clkdm", 1300 .main_clk = "usbhost_48m_fck", 1301 .prcm = { 1302 .omap2 = { 1303 .module_offs = OMAP3430ES2_USBHOST_MOD, 1304 .idlest_reg_id = 1, 1305 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, 1306 }, 1307 }, 1308 1309 /* 1310 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 1311 * id: i660 1312 * 1313 * Description: 1314 * In the following configuration : 1315 * - USBHOST module is set to smart-idle mode 1316 * - PRCM asserts idle_req to the USBHOST module ( This typically 1317 * happens when the system is going to a low power mode : all ports 1318 * have been suspended, the master part of the USBHOST module has 1319 * entered the standby state, and SW has cut the functional clocks) 1320 * - an USBHOST interrupt occurs before the module is able to answer 1321 * idle_ack, typically a remote wakeup IRQ. 1322 * Then the USB HOST module will enter a deadlock situation where it 1323 * is no more accessible nor functional. 1324 * 1325 * Workaround: 1326 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE 1327 */ 1328 1329 /* 1330 * Errata: USB host EHCI may stall when entering smart-standby mode 1331 * Id: i571 1332 * 1333 * Description: 1334 * When the USBHOST module is set to smart-standby mode, and when it is 1335 * ready to enter the standby state (i.e. all ports are suspended and 1336 * all attached devices are in suspend mode), then it can wrongly assert 1337 * the Mstandby signal too early while there are still some residual OCP 1338 * transactions ongoing. If this condition occurs, the internal state 1339 * machine may go to an undefined state and the USB link may be stuck 1340 * upon the next resume. 1341 * 1342 * Workaround: 1343 * Don't use smart standby; use only force standby, 1344 * hence HWMOD_SWSUP_MSTANDBY 1345 */ 1346 1347 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 1348 }; 1349 1350 /* 1351 * 'usb_tll_hs' class 1352 * usb_tll_hs module is the adapter on the usb_host_hs ports 1353 */ 1354 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { 1355 .rev_offs = 0x0000, 1356 .sysc_offs = 0x0010, 1357 .syss_offs = 0x0014, 1358 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1359 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1360 SYSC_HAS_AUTOIDLE), 1361 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1362 .sysc_fields = &omap_hwmod_sysc_type1, 1363 }; 1364 1365 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { 1366 .name = "usb_tll_hs", 1367 .sysc = &omap3xxx_usb_tll_hs_sysc, 1368 }; 1369 1370 1371 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { 1372 .name = "usb_tll_hs", 1373 .class = &omap3xxx_usb_tll_hs_hwmod_class, 1374 .clkdm_name = "core_l4_clkdm", 1375 .main_clk = "usbtll_fck", 1376 .prcm = { 1377 .omap2 = { 1378 .module_offs = CORE_MOD, 1379 .idlest_reg_id = 3, 1380 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, 1381 }, 1382 }, 1383 }; 1384 1385 static struct omap_hwmod omap3xxx_hdq1w_hwmod = { 1386 .name = "hdq1w", 1387 .main_clk = "hdq_fck", 1388 .prcm = { 1389 .omap2 = { 1390 .module_offs = CORE_MOD, 1391 .idlest_reg_id = 1, 1392 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, 1393 }, 1394 }, 1395 .class = &omap2_hdq1w_class, 1396 }; 1397 1398 /* SAD2D */ 1399 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { 1400 { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, 1401 { .name = "rst_modem_sw", .rst_shift = 1 }, 1402 }; 1403 1404 static struct omap_hwmod_class omap3xxx_sad2d_class = { 1405 .name = "sad2d", 1406 }; 1407 1408 static struct omap_hwmod omap3xxx_sad2d_hwmod = { 1409 .name = "sad2d", 1410 .rst_lines = omap3xxx_sad2d_resets, 1411 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), 1412 .main_clk = "sad2d_ick", 1413 .prcm = { 1414 .omap2 = { 1415 .module_offs = CORE_MOD, 1416 .idlest_reg_id = 1, 1417 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, 1418 }, 1419 }, 1420 .class = &omap3xxx_sad2d_class, 1421 }; 1422 1423 /* 1424 * 'gpmc' class 1425 * general purpose memory controller 1426 */ 1427 1428 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = { 1429 .rev_offs = 0x0000, 1430 .sysc_offs = 0x0010, 1431 .syss_offs = 0x0014, 1432 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | 1433 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 1434 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1435 .sysc_fields = &omap_hwmod_sysc_type1, 1436 }; 1437 1438 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { 1439 .name = "gpmc", 1440 .sysc = &omap3xxx_gpmc_sysc, 1441 }; 1442 1443 static struct omap_hwmod omap3xxx_gpmc_hwmod = { 1444 .name = "gpmc", 1445 .class = &omap3xxx_gpmc_hwmod_class, 1446 .clkdm_name = "core_l3_clkdm", 1447 .main_clk = "gpmc_fck", 1448 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 1449 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS, 1450 }; 1451 1452 /* 1453 * interfaces 1454 */ 1455 1456 /* L3 -> L4_CORE interface */ 1457 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { 1458 .master = &omap3xxx_l3_main_hwmod, 1459 .slave = &omap3xxx_l4_core_hwmod, 1460 .user = OCP_USER_MPU | OCP_USER_SDMA, 1461 }; 1462 1463 /* L3 -> L4_PER interface */ 1464 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { 1465 .master = &omap3xxx_l3_main_hwmod, 1466 .slave = &omap3xxx_l4_per_hwmod, 1467 .user = OCP_USER_MPU | OCP_USER_SDMA, 1468 }; 1469 1470 1471 /* MPU -> L3 interface */ 1472 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { 1473 .master = &omap3xxx_mpu_hwmod, 1474 .slave = &omap3xxx_l3_main_hwmod, 1475 .user = OCP_USER_MPU, 1476 }; 1477 1478 1479 /* l3 -> debugss */ 1480 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { 1481 .master = &omap3xxx_l3_main_hwmod, 1482 .slave = &omap3xxx_debugss_hwmod, 1483 .user = OCP_USER_MPU, 1484 }; 1485 1486 /* DSS -> l3 */ 1487 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { 1488 .master = &omap3430es1_dss_core_hwmod, 1489 .slave = &omap3xxx_l3_main_hwmod, 1490 .user = OCP_USER_MPU | OCP_USER_SDMA, 1491 }; 1492 1493 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { 1494 .master = &omap3xxx_dss_core_hwmod, 1495 .slave = &omap3xxx_l3_main_hwmod, 1496 .fw = { 1497 .omap2 = { 1498 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, 1499 .flags = OMAP_FIREWALL_L3, 1500 }, 1501 }, 1502 .user = OCP_USER_MPU | OCP_USER_SDMA, 1503 }; 1504 1505 /* l3_core -> sad2d interface */ 1506 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { 1507 .master = &omap3xxx_sad2d_hwmod, 1508 .slave = &omap3xxx_l3_main_hwmod, 1509 .clk = "core_l3_ick", 1510 .user = OCP_USER_MPU, 1511 }; 1512 1513 /* L4_CORE -> L4_WKUP interface */ 1514 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { 1515 .master = &omap3xxx_l4_core_hwmod, 1516 .slave = &omap3xxx_l4_wkup_hwmod, 1517 .user = OCP_USER_MPU | OCP_USER_SDMA, 1518 }; 1519 1520 /* L4 CORE -> MMC1 interface */ 1521 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { 1522 .master = &omap3xxx_l4_core_hwmod, 1523 .slave = &omap3xxx_pre_es3_mmc1_hwmod, 1524 .clk = "mmchs1_ick", 1525 .user = OCP_USER_MPU | OCP_USER_SDMA, 1526 .flags = OMAP_FIREWALL_L4, 1527 }; 1528 1529 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { 1530 .master = &omap3xxx_l4_core_hwmod, 1531 .slave = &omap3xxx_es3plus_mmc1_hwmod, 1532 .clk = "mmchs1_ick", 1533 .user = OCP_USER_MPU | OCP_USER_SDMA, 1534 .flags = OMAP_FIREWALL_L4, 1535 }; 1536 1537 /* L4 CORE -> MMC2 interface */ 1538 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { 1539 .master = &omap3xxx_l4_core_hwmod, 1540 .slave = &omap3xxx_pre_es3_mmc2_hwmod, 1541 .clk = "mmchs2_ick", 1542 .user = OCP_USER_MPU | OCP_USER_SDMA, 1543 .flags = OMAP_FIREWALL_L4, 1544 }; 1545 1546 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { 1547 .master = &omap3xxx_l4_core_hwmod, 1548 .slave = &omap3xxx_es3plus_mmc2_hwmod, 1549 .clk = "mmchs2_ick", 1550 .user = OCP_USER_MPU | OCP_USER_SDMA, 1551 .flags = OMAP_FIREWALL_L4, 1552 }; 1553 1554 /* L4 CORE -> MMC3 interface */ 1555 1556 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { 1557 .master = &omap3xxx_l4_core_hwmod, 1558 .slave = &omap3xxx_mmc3_hwmod, 1559 .clk = "mmchs3_ick", 1560 .user = OCP_USER_MPU | OCP_USER_SDMA, 1561 .flags = OMAP_FIREWALL_L4, 1562 }; 1563 1564 /* L4 CORE -> UART1 interface */ 1565 1566 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { 1567 .master = &omap3xxx_l4_core_hwmod, 1568 .slave = &omap3xxx_uart1_hwmod, 1569 .clk = "uart1_ick", 1570 .user = OCP_USER_MPU | OCP_USER_SDMA, 1571 }; 1572 1573 /* L4 CORE -> UART2 interface */ 1574 1575 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { 1576 .master = &omap3xxx_l4_core_hwmod, 1577 .slave = &omap3xxx_uart2_hwmod, 1578 .clk = "uart2_ick", 1579 .user = OCP_USER_MPU | OCP_USER_SDMA, 1580 }; 1581 1582 /* L4 PER -> UART3 interface */ 1583 1584 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { 1585 .master = &omap3xxx_l4_per_hwmod, 1586 .slave = &omap3xxx_uart3_hwmod, 1587 .clk = "uart3_ick", 1588 .user = OCP_USER_MPU | OCP_USER_SDMA, 1589 }; 1590 1591 /* L4 PER -> UART4 interface */ 1592 1593 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { 1594 .master = &omap3xxx_l4_per_hwmod, 1595 .slave = &omap36xx_uart4_hwmod, 1596 .clk = "uart4_ick", 1597 .user = OCP_USER_MPU | OCP_USER_SDMA, 1598 }; 1599 1600 /* AM35xx: L4 CORE -> UART4 interface */ 1601 1602 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { 1603 .master = &omap3xxx_l4_core_hwmod, 1604 .slave = &am35xx_uart4_hwmod, 1605 .clk = "uart4_ick", 1606 .user = OCP_USER_MPU | OCP_USER_SDMA, 1607 }; 1608 1609 /* L4 CORE -> I2C1 interface */ 1610 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { 1611 .master = &omap3xxx_l4_core_hwmod, 1612 .slave = &omap3xxx_i2c1_hwmod, 1613 .clk = "i2c1_ick", 1614 .fw = { 1615 .omap2 = { 1616 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, 1617 .l4_prot_group = 7, 1618 .flags = OMAP_FIREWALL_L4, 1619 }, 1620 }, 1621 .user = OCP_USER_MPU | OCP_USER_SDMA, 1622 }; 1623 1624 /* L4 CORE -> I2C2 interface */ 1625 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { 1626 .master = &omap3xxx_l4_core_hwmod, 1627 .slave = &omap3xxx_i2c2_hwmod, 1628 .clk = "i2c2_ick", 1629 .fw = { 1630 .omap2 = { 1631 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, 1632 .l4_prot_group = 7, 1633 .flags = OMAP_FIREWALL_L4, 1634 }, 1635 }, 1636 .user = OCP_USER_MPU | OCP_USER_SDMA, 1637 }; 1638 1639 /* L4 CORE -> I2C3 interface */ 1640 1641 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { 1642 .master = &omap3xxx_l4_core_hwmod, 1643 .slave = &omap3xxx_i2c3_hwmod, 1644 .clk = "i2c3_ick", 1645 .fw = { 1646 .omap2 = { 1647 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, 1648 .l4_prot_group = 7, 1649 .flags = OMAP_FIREWALL_L4, 1650 }, 1651 }, 1652 .user = OCP_USER_MPU | OCP_USER_SDMA, 1653 }; 1654 1655 /* L4 CORE -> SR1 interface */ 1656 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { 1657 .master = &omap3xxx_l4_core_hwmod, 1658 .slave = &omap34xx_sr1_hwmod, 1659 .clk = "sr_l4_ick", 1660 .user = OCP_USER_MPU, 1661 }; 1662 1663 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { 1664 .master = &omap3xxx_l4_core_hwmod, 1665 .slave = &omap36xx_sr1_hwmod, 1666 .clk = "sr_l4_ick", 1667 .user = OCP_USER_MPU, 1668 }; 1669 1670 /* L4 CORE -> SR2 interface */ 1671 1672 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { 1673 .master = &omap3xxx_l4_core_hwmod, 1674 .slave = &omap34xx_sr2_hwmod, 1675 .clk = "sr_l4_ick", 1676 .user = OCP_USER_MPU, 1677 }; 1678 1679 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { 1680 .master = &omap3xxx_l4_core_hwmod, 1681 .slave = &omap36xx_sr2_hwmod, 1682 .clk = "sr_l4_ick", 1683 .user = OCP_USER_MPU, 1684 }; 1685 1686 /* L4_WKUP -> L4_SEC interface */ 1687 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { 1688 .master = &omap3xxx_l4_wkup_hwmod, 1689 .slave = &omap3xxx_l4_sec_hwmod, 1690 .user = OCP_USER_MPU | OCP_USER_SDMA, 1691 }; 1692 1693 /* IVA2 <- L3 interface */ 1694 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { 1695 .master = &omap3xxx_l3_main_hwmod, 1696 .slave = &omap3xxx_iva_hwmod, 1697 .clk = "core_l3_ick", 1698 .user = OCP_USER_MPU | OCP_USER_SDMA, 1699 }; 1700 1701 /* l4_per -> timer3 */ 1702 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { 1703 .master = &omap3xxx_l4_per_hwmod, 1704 .slave = &omap3xxx_timer3_hwmod, 1705 .clk = "gpt3_ick", 1706 .user = OCP_USER_MPU | OCP_USER_SDMA, 1707 }; 1708 1709 1710 /* l4_per -> timer4 */ 1711 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { 1712 .master = &omap3xxx_l4_per_hwmod, 1713 .slave = &omap3xxx_timer4_hwmod, 1714 .clk = "gpt4_ick", 1715 .user = OCP_USER_MPU | OCP_USER_SDMA, 1716 }; 1717 1718 1719 /* l4_per -> timer5 */ 1720 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { 1721 .master = &omap3xxx_l4_per_hwmod, 1722 .slave = &omap3xxx_timer5_hwmod, 1723 .clk = "gpt5_ick", 1724 .user = OCP_USER_MPU | OCP_USER_SDMA, 1725 }; 1726 1727 1728 /* l4_per -> timer6 */ 1729 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { 1730 .master = &omap3xxx_l4_per_hwmod, 1731 .slave = &omap3xxx_timer6_hwmod, 1732 .clk = "gpt6_ick", 1733 .user = OCP_USER_MPU | OCP_USER_SDMA, 1734 }; 1735 1736 1737 /* l4_per -> timer7 */ 1738 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { 1739 .master = &omap3xxx_l4_per_hwmod, 1740 .slave = &omap3xxx_timer7_hwmod, 1741 .clk = "gpt7_ick", 1742 .user = OCP_USER_MPU | OCP_USER_SDMA, 1743 }; 1744 1745 1746 /* l4_per -> timer8 */ 1747 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { 1748 .master = &omap3xxx_l4_per_hwmod, 1749 .slave = &omap3xxx_timer8_hwmod, 1750 .clk = "gpt8_ick", 1751 .user = OCP_USER_MPU | OCP_USER_SDMA, 1752 }; 1753 1754 1755 /* l4_per -> timer9 */ 1756 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { 1757 .master = &omap3xxx_l4_per_hwmod, 1758 .slave = &omap3xxx_timer9_hwmod, 1759 .clk = "gpt9_ick", 1760 .user = OCP_USER_MPU | OCP_USER_SDMA, 1761 }; 1762 1763 /* l4_core -> timer10 */ 1764 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { 1765 .master = &omap3xxx_l4_core_hwmod, 1766 .slave = &omap3xxx_timer10_hwmod, 1767 .clk = "gpt10_ick", 1768 .user = OCP_USER_MPU | OCP_USER_SDMA, 1769 }; 1770 1771 /* l4_core -> timer11 */ 1772 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { 1773 .master = &omap3xxx_l4_core_hwmod, 1774 .slave = &omap3xxx_timer11_hwmod, 1775 .clk = "gpt11_ick", 1776 .user = OCP_USER_MPU | OCP_USER_SDMA, 1777 }; 1778 1779 /* l4_wkup -> wd_timer2 */ 1780 1781 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { 1782 .master = &omap3xxx_l4_wkup_hwmod, 1783 .slave = &omap3xxx_wd_timer2_hwmod, 1784 .clk = "wdt2_ick", 1785 .user = OCP_USER_MPU | OCP_USER_SDMA, 1786 }; 1787 1788 /* l4_core -> dss */ 1789 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { 1790 .master = &omap3xxx_l4_core_hwmod, 1791 .slave = &omap3430es1_dss_core_hwmod, 1792 .clk = "dss_ick", 1793 .fw = { 1794 .omap2 = { 1795 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, 1796 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 1797 .flags = OMAP_FIREWALL_L4, 1798 }, 1799 }, 1800 .user = OCP_USER_MPU | OCP_USER_SDMA, 1801 }; 1802 1803 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { 1804 .master = &omap3xxx_l4_core_hwmod, 1805 .slave = &omap3xxx_dss_core_hwmod, 1806 .clk = "dss_ick", 1807 .fw = { 1808 .omap2 = { 1809 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, 1810 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 1811 .flags = OMAP_FIREWALL_L4, 1812 }, 1813 }, 1814 .user = OCP_USER_MPU | OCP_USER_SDMA, 1815 }; 1816 1817 /* l4_core -> dss_dispc */ 1818 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { 1819 .master = &omap3xxx_l4_core_hwmod, 1820 .slave = &omap3xxx_dss_dispc_hwmod, 1821 .clk = "dss_ick", 1822 .fw = { 1823 .omap2 = { 1824 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, 1825 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 1826 .flags = OMAP_FIREWALL_L4, 1827 }, 1828 }, 1829 .user = OCP_USER_MPU | OCP_USER_SDMA, 1830 }; 1831 1832 /* l4_core -> dss_dsi1 */ 1833 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { 1834 .master = &omap3xxx_l4_core_hwmod, 1835 .slave = &omap3xxx_dss_dsi1_hwmod, 1836 .clk = "dss_ick", 1837 .fw = { 1838 .omap2 = { 1839 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, 1840 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 1841 .flags = OMAP_FIREWALL_L4, 1842 }, 1843 }, 1844 .user = OCP_USER_MPU | OCP_USER_SDMA, 1845 }; 1846 1847 /* l4_core -> dss_rfbi */ 1848 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { 1849 .master = &omap3xxx_l4_core_hwmod, 1850 .slave = &omap3xxx_dss_rfbi_hwmod, 1851 .clk = "dss_ick", 1852 .fw = { 1853 .omap2 = { 1854 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, 1855 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , 1856 .flags = OMAP_FIREWALL_L4, 1857 }, 1858 }, 1859 .user = OCP_USER_MPU | OCP_USER_SDMA, 1860 }; 1861 1862 /* l4_core -> dss_venc */ 1863 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { 1864 .master = &omap3xxx_l4_core_hwmod, 1865 .slave = &omap3xxx_dss_venc_hwmod, 1866 .clk = "dss_ick", 1867 .fw = { 1868 .omap2 = { 1869 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, 1870 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 1871 .flags = OMAP_FIREWALL_L4, 1872 }, 1873 }, 1874 .flags = OCPIF_SWSUP_IDLE, 1875 .user = OCP_USER_MPU | OCP_USER_SDMA, 1876 }; 1877 1878 /* l4_wkup -> gpio1 */ 1879 1880 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { 1881 .master = &omap3xxx_l4_wkup_hwmod, 1882 .slave = &omap3xxx_gpio1_hwmod, 1883 .user = OCP_USER_MPU | OCP_USER_SDMA, 1884 }; 1885 1886 /* l4_per -> gpio2 */ 1887 1888 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { 1889 .master = &omap3xxx_l4_per_hwmod, 1890 .slave = &omap3xxx_gpio2_hwmod, 1891 .user = OCP_USER_MPU | OCP_USER_SDMA, 1892 }; 1893 1894 /* l4_per -> gpio3 */ 1895 1896 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { 1897 .master = &omap3xxx_l4_per_hwmod, 1898 .slave = &omap3xxx_gpio3_hwmod, 1899 .user = OCP_USER_MPU | OCP_USER_SDMA, 1900 }; 1901 1902 /* 1903 * 'mmu' class 1904 * The memory management unit performs virtual to physical address translation 1905 * for its requestors. 1906 */ 1907 1908 static struct omap_hwmod_class_sysconfig mmu_sysc = { 1909 .rev_offs = 0x000, 1910 .sysc_offs = 0x010, 1911 .syss_offs = 0x014, 1912 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1913 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1914 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1915 .sysc_fields = &omap_hwmod_sysc_type1, 1916 }; 1917 1918 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { 1919 .name = "mmu", 1920 .sysc = &mmu_sysc, 1921 }; 1922 1923 /* mmu isp */ 1924 static struct omap_hwmod omap3xxx_mmu_isp_hwmod; 1925 1926 /* l4_core -> mmu isp */ 1927 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { 1928 .master = &omap3xxx_l4_core_hwmod, 1929 .slave = &omap3xxx_mmu_isp_hwmod, 1930 .user = OCP_USER_MPU | OCP_USER_SDMA, 1931 }; 1932 1933 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { 1934 .name = "mmu_isp", 1935 .class = &omap3xxx_mmu_hwmod_class, 1936 .main_clk = "cam_ick", 1937 .flags = HWMOD_NO_IDLEST, 1938 }; 1939 1940 /* mmu iva */ 1941 1942 static struct omap_hwmod omap3xxx_mmu_iva_hwmod; 1943 1944 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { 1945 { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, 1946 }; 1947 1948 /* l3_main -> iva mmu */ 1949 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { 1950 .master = &omap3xxx_l3_main_hwmod, 1951 .slave = &omap3xxx_mmu_iva_hwmod, 1952 .user = OCP_USER_MPU | OCP_USER_SDMA, 1953 }; 1954 1955 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { 1956 .name = "mmu_iva", 1957 .class = &omap3xxx_mmu_hwmod_class, 1958 .clkdm_name = "iva2_clkdm", 1959 .rst_lines = omap3xxx_mmu_iva_resets, 1960 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), 1961 .main_clk = "iva2_ck", 1962 .prcm = { 1963 .omap2 = { 1964 .module_offs = OMAP3430_IVA2_MOD, 1965 .idlest_reg_id = 1, 1966 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, 1967 }, 1968 }, 1969 .flags = HWMOD_NO_IDLEST, 1970 }; 1971 1972 /* l4_per -> gpio4 */ 1973 1974 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { 1975 .master = &omap3xxx_l4_per_hwmod, 1976 .slave = &omap3xxx_gpio4_hwmod, 1977 .user = OCP_USER_MPU | OCP_USER_SDMA, 1978 }; 1979 1980 /* l4_per -> gpio5 */ 1981 1982 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { 1983 .master = &omap3xxx_l4_per_hwmod, 1984 .slave = &omap3xxx_gpio5_hwmod, 1985 .user = OCP_USER_MPU | OCP_USER_SDMA, 1986 }; 1987 1988 /* l4_per -> gpio6 */ 1989 1990 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { 1991 .master = &omap3xxx_l4_per_hwmod, 1992 .slave = &omap3xxx_gpio6_hwmod, 1993 .user = OCP_USER_MPU | OCP_USER_SDMA, 1994 }; 1995 1996 /* l4_core -> mcbsp1 */ 1997 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { 1998 .master = &omap3xxx_l4_core_hwmod, 1999 .slave = &omap3xxx_mcbsp1_hwmod, 2000 .clk = "mcbsp1_ick", 2001 .user = OCP_USER_MPU | OCP_USER_SDMA, 2002 }; 2003 2004 2005 /* l4_per -> mcbsp2 */ 2006 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { 2007 .master = &omap3xxx_l4_per_hwmod, 2008 .slave = &omap3xxx_mcbsp2_hwmod, 2009 .clk = "mcbsp2_ick", 2010 .user = OCP_USER_MPU | OCP_USER_SDMA, 2011 }; 2012 2013 2014 /* l4_per -> mcbsp3 */ 2015 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { 2016 .master = &omap3xxx_l4_per_hwmod, 2017 .slave = &omap3xxx_mcbsp3_hwmod, 2018 .clk = "mcbsp3_ick", 2019 .user = OCP_USER_MPU | OCP_USER_SDMA, 2020 }; 2021 2022 2023 /* l4_per -> mcbsp4 */ 2024 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { 2025 .master = &omap3xxx_l4_per_hwmod, 2026 .slave = &omap3xxx_mcbsp4_hwmod, 2027 .clk = "mcbsp4_ick", 2028 .user = OCP_USER_MPU | OCP_USER_SDMA, 2029 }; 2030 2031 2032 /* l4_core -> mcbsp5 */ 2033 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { 2034 .master = &omap3xxx_l4_core_hwmod, 2035 .slave = &omap3xxx_mcbsp5_hwmod, 2036 .clk = "mcbsp5_ick", 2037 .user = OCP_USER_MPU | OCP_USER_SDMA, 2038 }; 2039 2040 2041 /* l4_per -> mcbsp2_sidetone */ 2042 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { 2043 .master = &omap3xxx_l4_per_hwmod, 2044 .slave = &omap3xxx_mcbsp2_sidetone_hwmod, 2045 .clk = "mcbsp2_ick", 2046 .user = OCP_USER_MPU, 2047 }; 2048 2049 2050 /* l4_per -> mcbsp3_sidetone */ 2051 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { 2052 .master = &omap3xxx_l4_per_hwmod, 2053 .slave = &omap3xxx_mcbsp3_sidetone_hwmod, 2054 .clk = "mcbsp3_ick", 2055 .user = OCP_USER_MPU, 2056 }; 2057 2058 /* l4_core -> mailbox */ 2059 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { 2060 .master = &omap3xxx_l4_core_hwmod, 2061 .slave = &omap3xxx_mailbox_hwmod, 2062 .user = OCP_USER_MPU | OCP_USER_SDMA, 2063 }; 2064 2065 /* l4 core -> mcspi1 interface */ 2066 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { 2067 .master = &omap3xxx_l4_core_hwmod, 2068 .slave = &omap34xx_mcspi1, 2069 .clk = "mcspi1_ick", 2070 .user = OCP_USER_MPU | OCP_USER_SDMA, 2071 }; 2072 2073 /* l4 core -> mcspi2 interface */ 2074 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { 2075 .master = &omap3xxx_l4_core_hwmod, 2076 .slave = &omap34xx_mcspi2, 2077 .clk = "mcspi2_ick", 2078 .user = OCP_USER_MPU | OCP_USER_SDMA, 2079 }; 2080 2081 /* l4 core -> mcspi3 interface */ 2082 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { 2083 .master = &omap3xxx_l4_core_hwmod, 2084 .slave = &omap34xx_mcspi3, 2085 .clk = "mcspi3_ick", 2086 .user = OCP_USER_MPU | OCP_USER_SDMA, 2087 }; 2088 2089 /* l4 core -> mcspi4 interface */ 2090 2091 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { 2092 .master = &omap3xxx_l4_core_hwmod, 2093 .slave = &omap34xx_mcspi4, 2094 .clk = "mcspi4_ick", 2095 .user = OCP_USER_MPU | OCP_USER_SDMA, 2096 }; 2097 2098 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { 2099 .master = &omap3xxx_usb_host_hs_hwmod, 2100 .slave = &omap3xxx_l3_main_hwmod, 2101 .clk = "core_l3_ick", 2102 .user = OCP_USER_MPU, 2103 }; 2104 2105 2106 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { 2107 .master = &omap3xxx_l4_core_hwmod, 2108 .slave = &omap3xxx_usb_host_hs_hwmod, 2109 .clk = "usbhost_ick", 2110 .user = OCP_USER_MPU | OCP_USER_SDMA, 2111 }; 2112 2113 2114 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { 2115 .master = &omap3xxx_l4_core_hwmod, 2116 .slave = &omap3xxx_usb_tll_hs_hwmod, 2117 .clk = "usbtll_ick", 2118 .user = OCP_USER_MPU | OCP_USER_SDMA, 2119 }; 2120 2121 /* l4_core -> hdq1w interface */ 2122 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { 2123 .master = &omap3xxx_l4_core_hwmod, 2124 .slave = &omap3xxx_hdq1w_hwmod, 2125 .clk = "hdq_ick", 2126 .user = OCP_USER_MPU | OCP_USER_SDMA, 2127 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 2128 }; 2129 2130 /* am35xx has Davinci MDIO & EMAC */ 2131 static struct omap_hwmod_class am35xx_mdio_class = { 2132 .name = "davinci_mdio", 2133 }; 2134 2135 static struct omap_hwmod am35xx_mdio_hwmod = { 2136 .name = "davinci_mdio", 2137 .class = &am35xx_mdio_class, 2138 .flags = HWMOD_NO_IDLEST, 2139 }; 2140 2141 /* 2142 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 2143 * but this will probably require some additional hwmod core support, 2144 * so is left as a future to-do item. 2145 */ 2146 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { 2147 .master = &am35xx_mdio_hwmod, 2148 .slave = &omap3xxx_l3_main_hwmod, 2149 .clk = "emac_fck", 2150 .user = OCP_USER_MPU, 2151 }; 2152 2153 /* l4_core -> davinci mdio */ 2154 /* 2155 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 2156 * but this will probably require some additional hwmod core support, 2157 * so is left as a future to-do item. 2158 */ 2159 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { 2160 .master = &omap3xxx_l4_core_hwmod, 2161 .slave = &am35xx_mdio_hwmod, 2162 .clk = "emac_fck", 2163 .user = OCP_USER_MPU, 2164 }; 2165 2166 static struct omap_hwmod_class am35xx_emac_class = { 2167 .name = "davinci_emac", 2168 }; 2169 2170 static struct omap_hwmod am35xx_emac_hwmod = { 2171 .name = "davinci_emac", 2172 .class = &am35xx_emac_class, 2173 /* 2174 * According to Mark Greer, the MPU will not return from WFI 2175 * when the EMAC signals an interrupt. 2176 * http://www.spinics.net/lists/arm-kernel/msg174734.html 2177 */ 2178 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI), 2179 }; 2180 2181 /* l3_core -> davinci emac interface */ 2182 /* 2183 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 2184 * but this will probably require some additional hwmod core support, 2185 * so is left as a future to-do item. 2186 */ 2187 static struct omap_hwmod_ocp_if am35xx_emac__l3 = { 2188 .master = &am35xx_emac_hwmod, 2189 .slave = &omap3xxx_l3_main_hwmod, 2190 .clk = "emac_ick", 2191 .user = OCP_USER_MPU, 2192 }; 2193 2194 /* l4_core -> davinci emac */ 2195 /* 2196 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 2197 * but this will probably require some additional hwmod core support, 2198 * so is left as a future to-do item. 2199 */ 2200 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { 2201 .master = &omap3xxx_l4_core_hwmod, 2202 .slave = &am35xx_emac_hwmod, 2203 .clk = "emac_ick", 2204 .user = OCP_USER_MPU, 2205 }; 2206 2207 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { 2208 .master = &omap3xxx_l3_main_hwmod, 2209 .slave = &omap3xxx_gpmc_hwmod, 2210 .clk = "core_l3_ick", 2211 .user = OCP_USER_MPU | OCP_USER_SDMA, 2212 }; 2213 2214 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */ 2215 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = { 2216 .rev_offs = 0x5c, 2217 .sysc_offs = 0x60, 2218 .syss_offs = 0x64, 2219 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 2220 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 2221 .sysc_fields = &omap3_sham_sysc_fields, 2222 }; 2223 2224 static struct omap_hwmod_class omap3xxx_sham_class = { 2225 .name = "sham", 2226 .sysc = &omap3_sham_sysc, 2227 }; 2228 2229 2230 2231 static struct omap_hwmod omap3xxx_sham_hwmod = { 2232 .name = "sham", 2233 .main_clk = "sha12_ick", 2234 .prcm = { 2235 .omap2 = { 2236 .module_offs = CORE_MOD, 2237 .idlest_reg_id = 1, 2238 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT, 2239 }, 2240 }, 2241 .class = &omap3xxx_sham_class, 2242 }; 2243 2244 2245 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { 2246 .master = &omap3xxx_l4_core_hwmod, 2247 .slave = &omap3xxx_sham_hwmod, 2248 .clk = "sha12_ick", 2249 .user = OCP_USER_MPU | OCP_USER_SDMA, 2250 }; 2251 2252 /* 2253 * 'ssi' class 2254 * synchronous serial interface (multichannel and full-duplex serial if) 2255 */ 2256 2257 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = { 2258 .rev_offs = 0x0000, 2259 .sysc_offs = 0x0010, 2260 .syss_offs = 0x0014, 2261 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE | 2262 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 2263 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2264 .sysc_fields = &omap_hwmod_sysc_type1, 2265 }; 2266 2267 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = { 2268 .name = "ssi", 2269 .sysc = &omap34xx_ssi_sysc, 2270 }; 2271 2272 static struct omap_hwmod omap3xxx_ssi_hwmod = { 2273 .name = "ssi", 2274 .class = &omap3xxx_ssi_hwmod_class, 2275 .clkdm_name = "core_l4_clkdm", 2276 .main_clk = "ssi_ssr_fck", 2277 .prcm = { 2278 .omap2 = { 2279 .module_offs = CORE_MOD, 2280 .idlest_reg_id = 1, 2281 .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT, 2282 }, 2283 }, 2284 }; 2285 2286 /* L4 CORE -> SSI */ 2287 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = { 2288 .master = &omap3xxx_l4_core_hwmod, 2289 .slave = &omap3xxx_ssi_hwmod, 2290 .clk = "ssi_ick", 2291 .user = OCP_USER_MPU | OCP_USER_SDMA, 2292 }; 2293 2294 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { 2295 &omap3xxx_l3_main__l4_core, 2296 &omap3xxx_l3_main__l4_per, 2297 &omap3xxx_mpu__l3_main, 2298 &omap3xxx_l3_main__l4_debugss, 2299 &omap3xxx_l4_core__l4_wkup, 2300 &omap3xxx_l4_core__mmc3, 2301 &omap3_l4_core__uart1, 2302 &omap3_l4_core__uart2, 2303 &omap3_l4_per__uart3, 2304 &omap3_l4_core__i2c1, 2305 &omap3_l4_core__i2c2, 2306 &omap3_l4_core__i2c3, 2307 &omap3xxx_l4_wkup__l4_sec, 2308 &omap3xxx_l4_per__timer3, 2309 &omap3xxx_l4_per__timer4, 2310 &omap3xxx_l4_per__timer5, 2311 &omap3xxx_l4_per__timer6, 2312 &omap3xxx_l4_per__timer7, 2313 &omap3xxx_l4_per__timer8, 2314 &omap3xxx_l4_per__timer9, 2315 &omap3xxx_l4_core__timer10, 2316 &omap3xxx_l4_core__timer11, 2317 &omap3xxx_l4_wkup__wd_timer2, 2318 &omap3xxx_l4_wkup__gpio1, 2319 &omap3xxx_l4_per__gpio2, 2320 &omap3xxx_l4_per__gpio3, 2321 &omap3xxx_l4_per__gpio4, 2322 &omap3xxx_l4_per__gpio5, 2323 &omap3xxx_l4_per__gpio6, 2324 &omap3xxx_l4_core__mcbsp1, 2325 &omap3xxx_l4_per__mcbsp2, 2326 &omap3xxx_l4_per__mcbsp3, 2327 &omap3xxx_l4_per__mcbsp4, 2328 &omap3xxx_l4_core__mcbsp5, 2329 &omap3xxx_l4_per__mcbsp2_sidetone, 2330 &omap3xxx_l4_per__mcbsp3_sidetone, 2331 &omap34xx_l4_core__mcspi1, 2332 &omap34xx_l4_core__mcspi2, 2333 &omap34xx_l4_core__mcspi3, 2334 &omap34xx_l4_core__mcspi4, 2335 &omap3xxx_l3_main__gpmc, 2336 NULL, 2337 }; 2338 2339 /* crypto hwmod links */ 2340 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = { 2341 &omap3xxx_l4_core__sham, 2342 NULL, 2343 }; 2344 2345 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = { 2346 &omap3xxx_l4_core__sham, 2347 NULL 2348 }; 2349 2350 2351 /* 2352 * Apparently the SHA/MD5 and AES accelerator IP blocks are 2353 * only present on some AM35xx chips, and no one knows which 2354 * ones. See 2355 * http://www.spinics.net/lists/arm-kernel/msg215466.html So 2356 * if you need these IP blocks on an AM35xx, try uncommenting 2357 * the following lines. 2358 */ 2359 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = { 2360 /* &omap3xxx_l4_core__sham, */ 2361 NULL 2362 }; 2363 2364 /* 3430ES1-only hwmod links */ 2365 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { 2366 &omap3430es1_dss__l3, 2367 &omap3430es1_l4_core__dss, 2368 NULL, 2369 }; 2370 2371 /* 3430ES2+-only hwmod links */ 2372 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { 2373 &omap3xxx_dss__l3, 2374 &omap3xxx_l4_core__dss, 2375 &omap3xxx_usb_host_hs__l3_main_2, 2376 &omap3xxx_l4_core__usb_host_hs, 2377 &omap3xxx_l4_core__usb_tll_hs, 2378 NULL, 2379 }; 2380 2381 /* <= 3430ES3-only hwmod links */ 2382 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { 2383 &omap3xxx_l4_core__pre_es3_mmc1, 2384 &omap3xxx_l4_core__pre_es3_mmc2, 2385 NULL, 2386 }; 2387 2388 /* 3430ES3+-only hwmod links */ 2389 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { 2390 &omap3xxx_l4_core__es3plus_mmc1, 2391 &omap3xxx_l4_core__es3plus_mmc2, 2392 NULL, 2393 }; 2394 2395 /* 34xx-only hwmod links (all ES revisions) */ 2396 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { 2397 &omap3xxx_l3__iva, 2398 &omap34xx_l4_core__sr1, 2399 &omap34xx_l4_core__sr2, 2400 &omap3xxx_l4_core__mailbox, 2401 &omap3xxx_l4_core__hdq1w, 2402 &omap3xxx_sad2d__l3, 2403 &omap3xxx_l4_core__mmu_isp, 2404 &omap3xxx_l3_main__mmu_iva, 2405 &omap3xxx_l4_core__ssi, 2406 NULL, 2407 }; 2408 2409 /* 36xx-only hwmod links (all ES revisions) */ 2410 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { 2411 &omap3xxx_l3__iva, 2412 &omap36xx_l4_per__uart4, 2413 &omap3xxx_dss__l3, 2414 &omap3xxx_l4_core__dss, 2415 &omap36xx_l4_core__sr1, 2416 &omap36xx_l4_core__sr2, 2417 &omap3xxx_l4_core__mailbox, 2418 &omap3xxx_usb_host_hs__l3_main_2, 2419 &omap3xxx_l4_core__usb_host_hs, 2420 &omap3xxx_l4_core__usb_tll_hs, 2421 &omap3xxx_l4_core__es3plus_mmc1, 2422 &omap3xxx_l4_core__es3plus_mmc2, 2423 &omap3xxx_l4_core__hdq1w, 2424 &omap3xxx_sad2d__l3, 2425 &omap3xxx_l4_core__mmu_isp, 2426 &omap3xxx_l3_main__mmu_iva, 2427 &omap3xxx_l4_core__ssi, 2428 NULL, 2429 }; 2430 2431 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { 2432 &omap3xxx_dss__l3, 2433 &omap3xxx_l4_core__dss, 2434 &am35xx_l4_core__uart4, 2435 &omap3xxx_usb_host_hs__l3_main_2, 2436 &omap3xxx_l4_core__usb_host_hs, 2437 &omap3xxx_l4_core__usb_tll_hs, 2438 &omap3xxx_l4_core__es3plus_mmc1, 2439 &omap3xxx_l4_core__es3plus_mmc2, 2440 &omap3xxx_l4_core__hdq1w, 2441 &am35xx_mdio__l3, 2442 &am35xx_l4_core__mdio, 2443 &am35xx_emac__l3, 2444 &am35xx_l4_core__emac, 2445 NULL, 2446 }; 2447 2448 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { 2449 &omap3xxx_l4_core__dss_dispc, 2450 &omap3xxx_l4_core__dss_dsi1, 2451 &omap3xxx_l4_core__dss_rfbi, 2452 &omap3xxx_l4_core__dss_venc, 2453 NULL, 2454 }; 2455 2456 /** 2457 * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible? 2458 * @bus: struct device_node * for the top-level OMAP DT data 2459 * @dev_name: device name used in the DT file 2460 * 2461 * Determine whether a "secure" IP block @dev_name is usable by Linux. 2462 * There doesn't appear to be a 100% reliable way to determine this, 2463 * so we rely on heuristics. If @bus is null, meaning there's no DT 2464 * data, then we only assume the IP block is accessible if the OMAP is 2465 * fused as a 'general-purpose' SoC. If however DT data is present, 2466 * test to see if the IP block is described in the DT data and set to 2467 * 'status = "okay"'. If so then we assume the ODM has configured the 2468 * OMAP firewalls to allow access to the IP block. 2469 * 2470 * Return: 0 if device named @dev_name is not likely to be accessible, 2471 * or 1 if it is likely to be accessible. 2472 */ 2473 static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus, 2474 const char *dev_name) 2475 { 2476 struct device_node *node; 2477 bool available; 2478 2479 if (!bus) 2480 return omap_type() == OMAP2_DEVICE_TYPE_GP; 2481 2482 node = of_get_child_by_name(bus, dev_name); 2483 available = of_device_is_available(node); 2484 of_node_put(node); 2485 2486 return available; 2487 } 2488 2489 int __init omap3xxx_hwmod_init(void) 2490 { 2491 int r; 2492 struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL; 2493 struct device_node *bus; 2494 unsigned int rev; 2495 2496 omap_hwmod_init(); 2497 2498 /* Register hwmod links common to all OMAP3 */ 2499 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); 2500 if (r < 0) 2501 return r; 2502 2503 rev = omap_rev(); 2504 2505 /* 2506 * Register hwmod links common to individual OMAP3 families, all 2507 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) 2508 * All possible revisions should be included in this conditional. 2509 */ 2510 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 2511 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || 2512 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { 2513 h = omap34xx_hwmod_ocp_ifs; 2514 h_sham = omap34xx_sham_hwmod_ocp_ifs; 2515 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { 2516 h = am35xx_hwmod_ocp_ifs; 2517 h_sham = am35xx_sham_hwmod_ocp_ifs; 2518 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || 2519 rev == OMAP3630_REV_ES1_2) { 2520 h = omap36xx_hwmod_ocp_ifs; 2521 h_sham = omap36xx_sham_hwmod_ocp_ifs; 2522 } else { 2523 WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); 2524 return -EINVAL; 2525 } 2526 2527 r = omap_hwmod_register_links(h); 2528 if (r < 0) 2529 return r; 2530 2531 /* 2532 * Register crypto hwmod links only if they are not disabled in DT. 2533 * If DT information is missing, enable them only for GP devices. 2534 */ 2535 2536 bus = of_find_node_by_name(NULL, "ocp"); 2537 2538 if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) { 2539 r = omap_hwmod_register_links(h_sham); 2540 if (r < 0) 2541 goto put_node; 2542 } 2543 2544 of_node_put(bus); 2545 2546 /* 2547 * Register hwmod links specific to certain ES levels of a 2548 * particular family of silicon (e.g., 34xx ES1.0) 2549 */ 2550 h = NULL; 2551 if (rev == OMAP3430_REV_ES1_0) { 2552 h = omap3430es1_hwmod_ocp_ifs; 2553 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || 2554 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 2555 rev == OMAP3430_REV_ES3_1_2) { 2556 h = omap3430es2plus_hwmod_ocp_ifs; 2557 } 2558 2559 if (h) { 2560 r = omap_hwmod_register_links(h); 2561 if (r < 0) 2562 return r; 2563 } 2564 2565 h = NULL; 2566 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 2567 rev == OMAP3430_REV_ES2_1) { 2568 h = omap3430_pre_es3_hwmod_ocp_ifs; 2569 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 2570 rev == OMAP3430_REV_ES3_1_2) { 2571 h = omap3430_es3plus_hwmod_ocp_ifs; 2572 } 2573 2574 if (h) 2575 r = omap_hwmod_register_links(h); 2576 if (r < 0) 2577 return r; 2578 2579 /* 2580 * DSS code presumes that dss_core hwmod is handled first, 2581 * _before_ any other DSS related hwmods so register common 2582 * DSS hwmod links last to ensure that dss_core is already 2583 * registered. Otherwise some change things may happen, for 2584 * ex. if dispc is handled before dss_core and DSS is enabled 2585 * in bootloader DISPC will be reset with outputs enabled 2586 * which sometimes leads to unrecoverable L3 error. XXX The 2587 * long-term fix to this is to ensure hwmods are set up in 2588 * dependency order in the hwmod core code. 2589 */ 2590 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); 2591 2592 return r; 2593 2594 put_node: 2595 of_node_put(bus); 2596 return r; 2597 } 2598